rt2x00: Implement HW encryption (rt61pci)
rt61pci supports hardware encryption. rt61pci supports up to 4 shared keys and up to 64 pairwise keys. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
2bb057d07a
commit
61e754f44b
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@ -107,6 +107,7 @@ config RT61PCI
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depends on PCI
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select RT2X00_LIB_PCI
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select RT2X00_LIB_FIRMWARE
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select RT2X00_LIB_CRYPTO
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select CRC_ITU_T
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select EEPROM_93CX6
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---help---
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@ -346,6 +346,204 @@ static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
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/*
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* Configuration handlers.
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*/
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static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
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struct rt2x00lib_crypto *crypto,
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struct ieee80211_key_conf *key)
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{
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struct hw_key_entry key_entry;
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struct rt2x00_field32 field;
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u32 mask;
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u32 reg;
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if (crypto->cmd == SET_KEY) {
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/*
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* rt2x00lib can't determine the correct free
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* key_idx for shared keys. We have 1 register
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* with key valid bits. The goal is simple, read
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* the register, if that is full we have no slots
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* left.
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* Note that each BSS is allowed to have up to 4
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* shared keys, so put a mask over the allowed
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* entries.
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*/
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mask = (0xf << crypto->bssidx);
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rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
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reg &= mask;
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if (reg && reg == mask)
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return -ENOSPC;
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key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
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/*
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* Upload key to hardware
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*/
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memcpy(key_entry.key, crypto->key,
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sizeof(key_entry.key));
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memcpy(key_entry.tx_mic, crypto->tx_mic,
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sizeof(key_entry.tx_mic));
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memcpy(key_entry.rx_mic, crypto->rx_mic,
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sizeof(key_entry.rx_mic));
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reg = SHARED_KEY_ENTRY(key->hw_key_idx);
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rt2x00pci_register_multiwrite(rt2x00dev, reg,
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&key_entry, sizeof(key_entry));
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/*
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* The cipher types are stored over 2 registers.
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* bssidx 0 and 1 keys are stored in SEC_CSR1 and
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* bssidx 1 and 2 keys are stored in SEC_CSR5.
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* Using the correct defines correctly will cause overhead,
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* so just calculate the correct offset.
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*/
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if (key->hw_key_idx < 8) {
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field.bit_offset = (3 * key->hw_key_idx);
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field.bit_mask = 0x7 << field.bit_offset;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®);
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rt2x00_set_field32(®, field, crypto->cipher);
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rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
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} else {
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field.bit_offset = (3 * (key->hw_key_idx - 8));
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field.bit_mask = 0x7 << field.bit_offset;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®);
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rt2x00_set_field32(®, field, crypto->cipher);
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rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
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}
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/*
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* The driver does not support the IV/EIV generation
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* in hardware. However it doesn't support the IV/EIV
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* inside the ieee80211 frame either, but requires it
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* to be provided seperately for the descriptor.
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* rt2x00lib will cut the IV/EIV data out of all frames
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* given to us by mac80211, but we must tell mac80211
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* to generate the IV/EIV data.
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*/
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key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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}
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/*
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* SEC_CSR0 contains only single-bit fields to indicate
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* a particular key is valid. Because using the FIELD32()
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* defines directly will cause a lot of overhead we use
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* a calculation to determine the correct bit directly.
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*/
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mask = 1 << key->hw_key_idx;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
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if (crypto->cmd == SET_KEY)
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reg |= mask;
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else if (crypto->cmd == DISABLE_KEY)
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reg &= ~mask;
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rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
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return 0;
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}
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static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
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struct rt2x00lib_crypto *crypto,
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struct ieee80211_key_conf *key)
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{
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struct hw_pairwise_ta_entry addr_entry;
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struct hw_key_entry key_entry;
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u32 mask;
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u32 reg;
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if (crypto->cmd == SET_KEY) {
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/*
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* rt2x00lib can't determine the correct free
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* key_idx for pairwise keys. We have 2 registers
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* with key valid bits. The goal is simple, read
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* the first register, if that is full move to
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* the next register.
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* When both registers are full, we drop the key,
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* otherwise we use the first invalid entry.
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*/
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rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
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if (reg && reg == ~0) {
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key->hw_key_idx = 32;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
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if (reg && reg == ~0)
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return -ENOSPC;
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}
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key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
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/*
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* Upload key to hardware
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*/
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memcpy(key_entry.key, crypto->key,
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sizeof(key_entry.key));
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memcpy(key_entry.tx_mic, crypto->tx_mic,
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sizeof(key_entry.tx_mic));
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memcpy(key_entry.rx_mic, crypto->rx_mic,
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sizeof(key_entry.rx_mic));
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memset(&addr_entry, 0, sizeof(addr_entry));
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memcpy(&addr_entry, crypto->address, ETH_ALEN);
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addr_entry.cipher = crypto->cipher;
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reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
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rt2x00pci_register_multiwrite(rt2x00dev, reg,
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&key_entry, sizeof(key_entry));
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reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
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rt2x00pci_register_multiwrite(rt2x00dev, reg,
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&addr_entry, sizeof(addr_entry));
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/*
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* Enable pairwise lookup table for given BSS idx,
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* without this received frames will not be decrypted
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* by the hardware.
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*/
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rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®);
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reg |= (1 << crypto->bssidx);
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rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
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/*
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* The driver does not support the IV/EIV generation
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* in hardware. However it doesn't support the IV/EIV
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* inside the ieee80211 frame either, but requires it
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* to be provided seperately for the descriptor.
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* rt2x00lib will cut the IV/EIV data out of all frames
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* given to us by mac80211, but we must tell mac80211
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* to generate the IV/EIV data.
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*/
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key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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}
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/*
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* SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
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* a particular key is valid. Because using the FIELD32()
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* defines directly will cause a lot of overhead we use
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* a calculation to determine the correct bit directly.
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*/
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if (key->hw_key_idx < 32) {
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mask = 1 << key->hw_key_idx;
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rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
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if (crypto->cmd == SET_KEY)
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reg |= mask;
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else if (crypto->cmd == DISABLE_KEY)
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reg &= ~mask;
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rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
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} else {
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mask = 1 << (key->hw_key_idx - 32);
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rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
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if (crypto->cmd == SET_KEY)
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reg |= mask;
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else if (crypto->cmd == DISABLE_KEY)
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reg &= ~mask;
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rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
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}
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return 0;
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}
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static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
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const unsigned int filter_flags)
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{
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@ -1533,8 +1731,8 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
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* TX descriptor initialization
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*/
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static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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struct sk_buff *skb,
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struct txentry_desc *txdesc)
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struct sk_buff *skb,
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struct txentry_desc *txdesc)
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{
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struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
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__le32 *txd = skbdesc->desc;
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@ -1548,7 +1746,7 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
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rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
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rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
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rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
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@ -1561,6 +1759,11 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
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rt2x00_desc_write(txd, 2, word);
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if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
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_rt2x00_desc_write(txd, 3, skbdesc->iv);
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_rt2x00_desc_write(txd, 4, skbdesc->eiv);
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}
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rt2x00_desc_read(txd, 5, &word);
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rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
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rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
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@ -1595,11 +1798,15 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
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rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
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test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
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rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
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test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
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test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
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rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
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rt2x00_set_field32(&word, TXD_W0_BURST,
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test_bit(ENTRY_TXD_BURST, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
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rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
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rt2x00_desc_write(txd, 0, word);
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}
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@ -1718,6 +1925,7 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
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static void rt61pci_fill_rxdone(struct queue_entry *entry,
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struct rxdone_entry_desc *rxdesc)
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{
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struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
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struct queue_entry_priv_pci *entry_priv = entry->priv_data;
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u32 word0;
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u32 word1;
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@ -1728,6 +1936,38 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
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if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
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rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
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if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
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rxdesc->cipher =
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rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
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rxdesc->cipher_status =
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rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
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}
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if (rxdesc->cipher != CIPHER_NONE) {
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_rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
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_rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
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_rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
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/*
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* Hardware has stripped IV/EIV data from 802.11 frame during
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* decryption. It has provided the data seperately but rt2x00lib
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* should decide if it should be reinserted.
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*/
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rxdesc->flags |= RX_FLAG_IV_STRIPPED;
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/*
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* FIXME: Legacy driver indicates that the frame does
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* contain the Michael Mic. Unfortunately, in rt2x00
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* the MIC seems to be missing completely...
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*/
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rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
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if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
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rxdesc->flags |= RX_FLAG_DECRYPTED;
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else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
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rxdesc->flags |= RX_FLAG_MMIC_ERROR;
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}
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/*
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* Obtain the status about this packet.
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* When frame was received with an OFDM bitrate,
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@ -1735,7 +1975,7 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
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* a CCK bitrate the signal is the rate in 100kbit/s.
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*/
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rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
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rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
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rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
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rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
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if (rt2x00_get_field32(word0, RXD_W0_OFDM))
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@ -2355,6 +2595,7 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
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*/
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__set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
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__set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
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__set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
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/*
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* Set the rssi offset.
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@ -2404,6 +2645,7 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
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.config = rt2x00mac_config,
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.config_interface = rt2x00mac_config_interface,
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.configure_filter = rt2x00mac_configure_filter,
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.set_key = rt2x00mac_set_key,
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.get_stats = rt2x00mac_get_stats,
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.set_retry_limit = rt61pci_set_retry_limit,
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.bss_info_changed = rt2x00mac_bss_info_changed,
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@ -2432,6 +2674,8 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
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.write_beacon = rt61pci_write_beacon,
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.kick_tx_queue = rt61pci_kick_tx_queue,
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.fill_rxdone = rt61pci_fill_rxdone,
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.config_shared_key = rt61pci_config_shared_key,
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.config_pairwise_key = rt61pci_config_pairwise_key,
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.config_filter = rt61pci_config_filter,
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.config_intf = rt61pci_config_intf,
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.config_erp = rt61pci_config_erp,
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@ -134,6 +134,16 @@
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#define PAIRWISE_KEY_TABLE_BASE 0x1200
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#define PAIRWISE_TA_TABLE_BASE 0x1a00
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#define SHARED_KEY_ENTRY(__idx) \
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( SHARED_KEY_TABLE_BASE + \
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((__idx) * sizeof(struct hw_key_entry)) )
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#define PAIRWISE_KEY_ENTRY(__idx) \
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( PAIRWISE_KEY_TABLE_BASE + \
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((__idx) * sizeof(struct hw_key_entry)) )
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#define PAIRWISE_TA_ENTRY(__idx) \
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( PAIRWISE_TA_TABLE_BASE + \
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((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
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struct hw_key_entry {
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u8 key[16];
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u8 tx_mic[8];
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@ -142,7 +152,8 @@ struct hw_key_entry {
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struct hw_pairwise_ta_entry {
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u8 address[6];
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u8 reserved[2];
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u8 cipher;
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u8 reserved;
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} __attribute__ ((packed));
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/*
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@ -662,6 +673,10 @@ struct hw_pairwise_ta_entry {
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* SEC_CSR4: Pairwise key table lookup control.
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*/
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#define SEC_CSR4 0x30b0
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#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
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#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
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#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
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#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
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/*
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* SEC_CSR5: shared key table security mode register.
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@ -1428,8 +1443,10 @@ struct hw_pairwise_ta_entry {
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/*
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* Word4
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* ICV: Received ICV of originally encrypted.
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||||
* NOTE: This is a guess, the official definition is "reserved"
|
||||
*/
|
||||
#define RXD_W4_RESERVED FIELD32(0xffffffff)
|
||||
#define RXD_W4_ICV FIELD32(0xffffffff)
|
||||
|
||||
/*
|
||||
* the above 20-byte is called RXINFO and will be DMAed to MAC RX block
|
||||
|
|
Loading…
Reference in New Issue