drm/radeon: properly handle mc_stop/mc_resume on evergreen+ (v2)
- Stop the displays from accessing the FB - Block CPU access - Turn off MC client access This should fix issues some users have seen, especially with UEFI, when changing the MC FB location that result in hangs or display corruption. v2: fix crtc enabled check noticed by Luca Tettamanti Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
75104fa4f9
commit
62444b7462
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@ -1241,116 +1241,103 @@ void evergreen_agp_enable(struct radeon_device *rdev)
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void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
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{
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u32 crtc_enabled, tmp, frame_count, blackout;
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int i, j;
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save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
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save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
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/* Stop all video */
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/* disable VGA render */
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WREG32(VGA_RENDER_CONTROL, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
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if (rdev->num_crtc >= 4) {
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
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}
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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if (rdev->num_crtc >= 4) {
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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}
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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if (rdev->num_crtc >= 4) {
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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/* blank the display controllers */
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for (i = 0; i < rdev->num_crtc; i++) {
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crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
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if (crtc_enabled) {
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save->crtc_enabled[i] = true;
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if (ASIC_IS_DCE6(rdev)) {
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tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
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if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
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radeon_wait_for_vblank(rdev, i);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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}
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
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radeon_wait_for_vblank(rdev, i);
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tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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}
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}
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/* wait for the next frame */
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frame_count = radeon_get_vblank_counter(rdev, i);
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for (j = 0; j < rdev->usec_timeout; j++) {
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if (radeon_get_vblank_counter(rdev, i) != frame_count)
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break;
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udelay(1);
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}
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}
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}
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WREG32(D1VGA_CONTROL, 0);
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WREG32(D2VGA_CONTROL, 0);
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if (rdev->num_crtc >= 4) {
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WREG32(EVERGREEN_D3VGA_CONTROL, 0);
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WREG32(EVERGREEN_D4VGA_CONTROL, 0);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(EVERGREEN_D5VGA_CONTROL, 0);
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WREG32(EVERGREEN_D6VGA_CONTROL, 0);
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radeon_mc_wait_for_idle(rdev);
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blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
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if ((blackout & BLACKOUT_MODE_MASK) != 1) {
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/* Block CPU access */
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WREG32(BIF_FB_EN, 0);
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/* blackout the MC */
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blackout &= ~BLACKOUT_MODE_MASK;
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WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
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}
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}
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void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
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{
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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u32 tmp, frame_count;
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int i, j;
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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if (rdev->num_crtc >= 4) {
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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/* update crtc base addresses */
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for (i = 0; i < rdev->num_crtc; i++) {
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
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(u32)rdev->mc.vram_start);
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}
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if (rdev->num_crtc >= 6) {
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
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(u32)rdev->mc.vram_start);
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}
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WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
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WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
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/* Unlock host access */
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/* unblackout the MC */
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tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
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tmp &= ~BLACKOUT_MODE_MASK;
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WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
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/* allow CPU access */
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WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
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for (i = 0; i < rdev->num_crtc; i++) {
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if (save->crtc_enabled) {
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if (ASIC_IS_DCE6(rdev)) {
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tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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}
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/* wait for the next frame */
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frame_count = radeon_get_vblank_counter(rdev, i);
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for (j = 0; j < rdev->usec_timeout; j++) {
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if (radeon_get_vblank_counter(rdev, i) != frame_count)
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break;
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udelay(1);
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}
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}
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}
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/* Unlock vga access */
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WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
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mdelay(1);
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WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
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@ -218,6 +218,8 @@
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#define EVERGREEN_CRTC_CONTROL 0x6e70
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# define EVERGREEN_CRTC_MASTER_EN (1 << 0)
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# define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
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#define EVERGREEN_CRTC_BLANK_CONTROL 0x6e74
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# define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
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#define EVERGREEN_CRTC_STATUS 0x6e8c
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# define EVERGREEN_CRTC_V_BLANK (1 << 0)
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#define EVERGREEN_CRTC_STATUS_POSITION 0x6e90
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@ -87,6 +87,10 @@
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#define CONFIG_MEMSIZE 0x5428
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#define BIF_FB_EN 0x5490
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#define FB_READ_EN (1 << 0)
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#define FB_WRITE_EN (1 << 1)
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#define CP_COHER_BASE 0x85F8
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#define CP_STALLED_STAT1 0x8674
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#define CP_STALLED_STAT2 0x8678
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@ -430,6 +434,9 @@
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#define NOOFCHAN_MASK 0x00003000
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#define MC_SHARED_CHREMAP 0x2008
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#define MC_SHARED_BLACKOUT_CNTL 0x20ac
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#define BLACKOUT_MODE_MASK 0x00000007
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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#define NOOFBANK_MASK 0x00000003
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@ -389,6 +389,7 @@ void r700_cp_fini(struct radeon_device *rdev);
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struct evergreen_mc_save {
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u32 vga_render_control;
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u32 vga_hdp_control;
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bool crtc_enabled[RADEON_MAX_CRTCS];
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};
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void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
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