mtd: spinand: gigadevice: Add QE Bit
[ Upstream commitaea7687e77
] The following GigaDevice chips have the QE BIT in the feature flags, I checked the datasheets, but did not try this. * GD5F1GQ4xExxG * GD5F1GQ4xFxxG * GD5F1GQ4UAYIG * GD5F4GQ4UAYIG The Quad operations like 0xEB mention that the QE bit has to be set. Fixes:c93c613214
("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200820165121.3192-3-hauke@hauke-m.de Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -201,7 +201,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F2GQ4xA", 0xF2,
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@ -210,7 +210,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F4GQ4xA", 0xF4,
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@ -219,7 +219,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
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@ -228,7 +228,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
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@ -237,7 +237,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4ufxxg_ecc_get_status)),
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};
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