[ARM] Convert ARMv6 and ARMv7 to use new memory types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -175,8 +175,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
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/*
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/*
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* These are the memory types, defined to be compatible with
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* These are the memory types, defined to be compatible with
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* pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
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* pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
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* (note: build_mem_type_table modifies these bits
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* to work with our existing proc-*.S setup.)
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*/
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*/
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#define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */
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#define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */
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#define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */
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#define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */
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@ -184,12 +182,10 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
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#define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */
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#define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */
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#define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */
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#define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */
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#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
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#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
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#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 (pre-v6) */
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#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
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#define L_PTE_MT_DEV_SHARED2 (0x05 << 2) /* 0101 (v6) */
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#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
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#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
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#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */
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#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */
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#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 (pre-v6) */
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#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
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#define L_PTE_MT_DEV_WC2 (0x08 << 2) /* 1000 (v6) */
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#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
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#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
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#define L_PTE_MT_MASK (0x0f << 2)
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#define L_PTE_MT_MASK (0x0f << 2)
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@ -194,7 +194,6 @@ static struct mem_type mem_types[] = {
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},
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},
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[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
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[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
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.prot_pte_ext = PTE_EXT_TEX(2),
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
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.domain = DOMAIN_IO,
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.domain = DOMAIN_IO,
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@ -289,8 +288,6 @@ static void __init build_mem_type_table(void)
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* in xsc3 parlance, Uncached Normal in ARMv6 parlance).
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* in xsc3 parlance, Uncached Normal in ARMv6 parlance).
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*/
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*/
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if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
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if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
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mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1);
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mem_types[MT_DEVICE_WC].prot_pte &= ~L_PTE_BUFFERABLE;
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
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mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
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mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
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}
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}
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@ -351,7 +348,6 @@ static void __init build_mem_type_table(void)
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/*
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/*
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* Mark the device area as "shared device"
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* Mark the device area as "shared device"
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*/
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*/
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mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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@ -104,14 +104,38 @@
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* 11x0 0 1 0 r/w r/o
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* 11x0 0 1 0 r/w r/o
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* 1111 0 1 1 r/w r/w
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* 1111 0 1 1 r/w r/w
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*/
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*/
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.macro armv6_set_pte_ext
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.macro armv6_mt_table pfx
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\pfx\()_mt_table:
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.long 0x00 @ L_PTE_MT_UNCACHED
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.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ unused
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.long 0x00 @ L_PTE_MT_MINICACHE (not present)
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ L_PTE_MT_DEV_IXP2000
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.long 0x00 @ unused
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.long 0x00 @ unused
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.endm
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.macro armv6_set_pte_ext pfx
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str r1, [r0], #-2048 @ linux version
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str r1, [r0], #-2048 @ linux version
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bic r3, r1, #0x000003f0
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bic r3, r1, #0x000003fc
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bic r3, r3, #PTE_TYPE_MASK
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bic r3, r3, #PTE_TYPE_MASK
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orr r3, r3, r2
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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orr r3, r3, #PTE_EXT_AP0 | 2
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adr ip, \pfx\()_mt_table
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and r2, r1, #L_PTE_MT_MASK
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ldr r2, [ip, r2]
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tst r1, #L_PTE_WRITE
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tst r1, #L_PTE_WRITE
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tstne r1, #L_PTE_DIRTY
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tstne r1, #L_PTE_DIRTY
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orreq r3, r3, #PTE_EXT_APX
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orreq r3, r3, #PTE_EXT_APX
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@ -124,6 +148,8 @@
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tst r1, #L_PTE_EXEC
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tst r1, #L_PTE_EXEC
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orreq r3, r3, #PTE_EXT_XN
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orreq r3, r3, #PTE_EXT_XN
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orr r3, r3, r2
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tst r1, #L_PTE_YOUNG
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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moveq r3, #0
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@ -115,9 +115,11 @@ ENTRY(cpu_v6_switch_mm)
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* - pte - PTE value to store
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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* - ext - value for extended PTE bits
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*/
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*/
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armv6_mt_table cpu_v6
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ENTRY(cpu_v6_set_pte_ext)
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ENTRY(cpu_v6_set_pte_ext)
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#ifdef CONFIG_MMU
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#ifdef CONFIG_MMU
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armv6_set_pte_ext
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armv6_set_pte_ext cpu_v6
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#endif
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#endif
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mov pc, lr
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mov pc, lr
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@ -100,9 +100,11 @@ ENTRY(cpu_v7_switch_mm)
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* - pte - PTE value to store
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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* - ext - value for extended PTE bits
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*/
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*/
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armv6_mt_table cpu_v7
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ENTRY(cpu_v7_set_pte_ext)
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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#ifdef CONFIG_MMU
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armv6_set_pte_ext
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armv6_set_pte_ext cpu_v7
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#endif
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#endif
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mov pc, lr
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mov pc, lr
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@ -354,10 +354,10 @@ cpu_xsc3_mt_table:
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long 0x00 @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ L_PTE_MT_DEV_SHARED2
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.long 0x00 @ unused
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.long 0x00 @ L_PTE_MT_MINICACHE (not present)
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.long 0x00 @ L_PTE_MT_MINICACHE (not present)
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC2
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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@ -435,10 +435,10 @@ cpu_xscale_mt_table:
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long 0x00 @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ L_PTE_MT_DEV_SHARED2
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
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.long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC2
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.long 0x00 @ unused
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.long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC
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.long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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