perf/x86: Support constraint ranges
Icelake extended the general counters to 8, even when SMT is enabled. However only a (large) subset of the events can be used on all 8 counters. The events that can or cannot be used on all counters are organized in ranges. A lot of scheduler constraints are required to handle all this. To avoid blowing up the tables add event code ranges to the constraint tables, and a new inline function to match them. Originally-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> # developer hat on Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> # maintainer hat on Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: acme@kernel.org Cc: jolsa@kernel.org Link: https://lkml.kernel.org/r/20190402194509.2832-8-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -2693,7 +2693,7 @@ x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
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if (x86_pmu.event_constraints) {
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for_each_event_constraint(c, x86_pmu.event_constraints) {
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if ((event->hw.config & c->cmask) == c->code) {
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if (constraint_match(c, event->hw.config)) {
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event->hw.flags |= c->flags;
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return c;
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}
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@ -858,7 +858,7 @@ struct event_constraint *intel_pebs_constraints(struct perf_event *event)
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if (x86_pmu.pebs_constraints) {
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for_each_event_constraint(c, x86_pmu.pebs_constraints) {
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if ((event->hw.config & c->cmask) == c->code) {
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if (constraint_match(c, event->hw.config)) {
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event->hw.flags |= c->flags;
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return c;
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}
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@ -49,13 +49,19 @@ struct event_constraint {
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unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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u64 idxmsk64;
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};
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u64 code;
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u64 cmask;
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int weight;
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int overlap;
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int flags;
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u64 code;
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u64 cmask;
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int weight;
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int overlap;
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int flags;
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unsigned int size;
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};
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static inline bool constraint_match(struct event_constraint *c, u64 ecode)
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{
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return ((ecode & c->cmask) - c->code) <= (u64)c->size;
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}
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/*
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* struct hw_perf_event.flags flags
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*/
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@ -280,18 +286,29 @@ struct cpu_hw_events {
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void *kfree_on_online[X86_PERF_KFREE_MAX];
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};
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#define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
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#define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
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{ .idxmsk64 = (n) }, \
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.code = (c), \
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.size = (e) - (c), \
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.cmask = (m), \
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.weight = (w), \
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.overlap = (o), \
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.flags = f, \
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}
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#define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
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__EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
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#define EVENT_CONSTRAINT(c, n, m) \
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__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
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/*
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* The constraint_match() function only works for 'simple' event codes
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* and not for extended (AMD64_EVENTSEL_EVENT) events codes.
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*/
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#define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
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__EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
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#define INTEL_EXCLEVT_CONSTRAINT(c, n) \
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__EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
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0, PERF_X86_EVENT_EXCL)
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@ -326,6 +343,12 @@ struct cpu_hw_events {
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#define INTEL_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
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/*
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* Constraint on a range of Event codes
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*/
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#define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
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EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
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/*
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* Constraint on the Event code + UMask + fixed-mask
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*
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@ -373,6 +396,9 @@ struct cpu_hw_events {
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#define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
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#define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
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EVENT_CONSTRAINT_RANGE(c, e, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
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/* Check only flags, but allow all event/umask */
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#define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
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EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
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@ -389,6 +415,11 @@ struct cpu_hw_events {
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
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#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
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__EVENT_CONSTRAINT_RANGE(code, end, n, \
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
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#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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