ARM: Keystone DTS update for 4.8
- Pinmux entries for K2G - PCI DTS entry fixup -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXaW1xAAoJEHJsHOdBp5c/kk8P/RRJZZVoqgxQkun/Un9uCo8k w72o0YNnm/iae/2V2TvBIq+w9u7hvyemAIo4oHgf4RhQDhHLtRW48DefqoZbCxdB 5YokyM6msFaaQGOuGd0206PDQLyWjzcgrhTFap4yKG1qVaZ+AriERJGsfG73AXUa jiUPy3fCDfGdprxjzBMKRyq7LtWBKtUpBaLfc8ZeWwP8Ik5fbPFqe3iwJPcvW2SD cc5kWKUWO6lqvrx11mdEWhy+5u0wUcEDWyYI9mSse9uLMFAJ6ztYrMiDBcp6/lhk EgNIKO7+BFjRd/3cRfSxKazAc2Zgq+y0Y6HCUALapoWr+SPvlvzBrMp+pemgXHge QQbZcdb9GS6vcVMQ1cXJfUx1KqVpGlAR3G66QJMmZ/p3pJebD4dvGpcbBkH5ZFsG Qi61N9UDjgoxbkk83bCDRjr9KjVBhajPpq4KG0Vu3GvlMaFPAGpm29t7juphbZai fq4tuMT9fEUNxQE4kRNOX2iAp4ns5E2QNwWxOoMzpW39Znsc2iFNTH818cQfx+Fh oXSXtlEINgHqD6hRaBGrq2nkFB1ly2FGQJK1n58frTadP+9vVbggVMjT780B8FWV 6yl0c2w1RZcZhmMNhKVbFpqbPWiGCdwChR0RBNrR4uVBknFMOnshQxJnWihcYUk6 ZPZKqt/WzI4noVCqUKkQ =L7oP -----END PGP SIGNATURE----- Merge tag 'keystone_dts_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/dt ARM: Keystone DTS update for 4.8 - Pinmux entries for K2G - PCI DTS entry fixup * tag 'keystone_dts_for_4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: ARM: dts: k2g-evm: Add pinmuxing for UART0 ARM: dts: keystone: Header file for pinctrl constants ARM: dts: k2g: Add pinctrl support ARM: dts: keystone-k2l: Add pinctrl node ARM: dts: keystone: add interrupt property to PCI controller bindings ARM: dts: keystone: remove bogus IO resource entry from PCI binding Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
64f618a7a1
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@ -96,13 +96,16 @@
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
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ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
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0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
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ranges = <0x82000000 0 0x60000000 0x60000000
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0 0x10000000>;
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status = "disabled";
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device_type = "pci";
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num-lanes = <2>;
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bus-range = <0x00 0xff>;
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/* error interrupt */
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interrupts = <GIC_SPI 385 IRQ_TYPE_EDGE_RISING>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
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@ -27,6 +27,17 @@
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};
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&k2g_pinctrl {
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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@ -14,6 +14,7 @@
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/keystone.h>
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#include "skeleton.dtsi"
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/ {
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@ -75,6 +76,13 @@
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ranges = <0x0 0x0 0x0 0xc0000000>;
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dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
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k2g_pinctrl: pinmux@02621000 {
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compatible = "pinctrl-single";
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reg = <0x02621000 0x410>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x001b0007>;
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};
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uart0: serial@02530c00 {
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compatible = "ns16550a";
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current-speed = <115200>;
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@ -54,6 +54,155 @@
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interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
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};
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k2l_pmx: pinmux@02620690 {
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compatible = "pinctrl-single";
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reg = <0x02620690 0xc>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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status = "disabled";
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uart3_emifa_pins: pinmux_uart3_emifa_pins {
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pinctrl-single,bits = <
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/* UART3_EMIFA_SEL */
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0x0 0x0 0xc0
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>;
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};
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uart2_emifa_pins: pinmux_uart2_emifa_pins {
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pinctrl-single,bits = <
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/* UART2_EMIFA_SEL */
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0x0 0x0 0x30
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>;
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};
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uart01_spi2_pins: pinmux_uart01_spi2_pins {
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pinctrl-single,bits = <
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/* UART01_SPI2_SEL */
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0x0 0x0 0x4
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>;
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};
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dfesync_rp1_pins: pinmux_dfesync_rp1_pins{
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pinctrl-single,bits = <
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/* DFESYNC_RP1_SEL */
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0x0 0x0 0x2
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>;
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};
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avsif_pins: pinmux_avsif_pins {
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pinctrl-single,bits = <
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/* AVSIF_SEL */
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0x0 0x0 0x1
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>;
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};
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gpio_emu_pins: pinmux_gpio_emu_pins {
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pinctrl-single,bits = <
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/*
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* GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
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* GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
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* GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
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* GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
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* GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
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* GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
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* GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
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* GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
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* GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
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* GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
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* GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
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* GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
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* GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
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* GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
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* GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
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*/
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0x4 0x0000 0xFFFE0000
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>;
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};
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gpio_timio_pins: pinmux_gpio_timio_pins {
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pinctrl-single,bits = <
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/*
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* GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
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* GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
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* GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
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* GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
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* GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
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* GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
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* GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
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* GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
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* GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
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* GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
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* GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
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* GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
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*/
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0x4 0x0 0xFFF0
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>;
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};
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gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins {
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pinctrl-single,bits = <
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/*
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* GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
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* GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
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* GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
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* GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
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*/
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0x4 0x0 0xF
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>;
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};
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gpio_dfeio_pins: pinmux_gpio_dfeio_pins {
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pinctrl-single,bits = <
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/*
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* GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
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* GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
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* GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
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* GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
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* GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
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* GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
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* GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
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* GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
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* GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
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* GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
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* GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
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* GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
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* GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
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* GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
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* GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
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* GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
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*/
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0x8 0x0 0xFFFF0000
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>;
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};
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gpio_emifa_pins: pinmux_gpio_emifa_pins {
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pinctrl-single,bits = <
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/*
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* GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
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* GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
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* GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
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* GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
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* GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
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* GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
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* GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
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* GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
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* GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
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* GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
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* GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
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* GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
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* GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
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* GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
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* GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
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* GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
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*/
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0x8 0x0 0xFFFF
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>;
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};
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};
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dspgpio0: keystone_dsp_gpio@02620240 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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@ -294,13 +294,16 @@
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
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ranges = <0x81000000 0 0 0x23250000 0 0x4000
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0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
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ranges = <0x82000000 0 0x50000000 0x50000000
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0 0x10000000>;
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status = "disabled";
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device_type = "pci";
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num-lanes = <2>;
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bus-range = <0x00 0xff>;
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/* error interrupt */
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interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
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@ -0,0 +1,39 @@
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/*
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* This header provides constants for Keystone pinctrl bindings.
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*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H
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#define _DT_BINDINGS_PINCTRL_KEYSTONE_H
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#define MUX_MODE0 0
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#define MUX_MODE1 1
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#define MUX_MODE2 2
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#define MUX_MODE3 3
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#define MUX_MODE4 4
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#define MUX_MODE5 5
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#define BUFFER_CLASS_B (0 << 19)
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#define BUFFER_CLASS_C (1 << 19)
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#define BUFFER_CLASS_D (2 << 19)
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#define BUFFER_CLASS_E (3 << 19)
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#define PULL_DISABLE (1 << 16)
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#define PIN_PULLUP (1 << 17)
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#define PIN_PULLDOWN (0 << 17)
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#define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
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#define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000)
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#endif
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