linux-can-next-for-3.19-20141117
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUagcGAAoJECte4hHFiupU2WQP/AnV8JJP1dvfPXCRyZQNevMI s5g4528XBBQoDP63npml0NGK9R1Z0g8jp7fFiQ1Zix+FBEB40oIT17zxwl2TTLGL /p70umuBsO8/VVWfBe1EwG3ZWgzp9B/Ar0/g8D6Iq4Nc0nOa9Zx5b5ZyN65iGyv3 SrA3NRIYxvgte1BV0bL8lJ9azgi0lotCNtN2xPg2FnxHlJu2Kl0TKL9YTQdeZA6m vFSrY+ao6EdQAQx8vh5pezVTyj+lTxw7743AsothFReeYC4F/za+29IYXtPPggZt jgG+qdEpBvTq+MfsUYqz/rjFlNiW/Q6nWDnBzU0XbiquscrZyCvotrBowcNUNEeb OfuQNCFuGeUNoB26K1IU4fmdro+r8/1+FmT7XtMUSPMbyENJRkVYp6OrQfSqf0zA 1+acT8USYSthHNcTJlQuEzIyR/n5B/k3DZsRy+js0IneFx/2OOhk+GmDRdUFI8NY ScUVQDDATo9zYivwtxGpD8ooqOSRRrrRY2lF2F8DHcZZ5X10F/jlzDhkJcWLe0/M sfyr66j0wg1tB01+Pwf7ZplmkZR5+zAI/q4lP6i4xYLBuCaeL0ORwfIB5ca1pgrG RXXYD3yWqwt2d5AvDZ2tI0xPgzmoON3YX79AQytDrS92i0N+FEHkNV2eNihpDUkA ejX5EX5GSSR+8InoTq4a =1dSV -----END PGP SIGNATURE----- Merge tag 'linux-can-next-for-3.19-20141117' of git://gitorious.org/linux-can/linux-can-next Marc Kleine-Budde says: ==================== this is a pull request of 9 patches for net-next/master. All 9 patches are by Roger Quadros and update the c_can platform driver. First by improving the initialization sequence of the message RAM, making use of syscon/regmap. In the later patches support for various TI SoCs is added. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
66425a7f9b
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@ -4,6 +4,8 @@ Bosch C_CAN/D_CAN controller Device Tree Bindings
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Required properties:
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- compatible : Should be "bosch,c_can" for C_CAN controllers and
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"bosch,d_can" for D_CAN controllers.
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Can be "ti,dra7-d_can", "ti,am3352-d_can" or
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"ti,am4372-d_can".
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- reg : physical base address and size of the C_CAN/D_CAN
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registers map
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- interrupts : property with a value describing the interrupt
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@ -12,6 +14,9 @@ Required properties:
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Optional properties:
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- ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the
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instance number
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- syscon-raminit : Handle to system control region that contains the
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RAMINIT register, register offset to the RAMINIT
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register and the CAN instance number (0 offset).
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Note: "ti,hwmods" field is used to fetch the base address and irq
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resources from TI, omap hwmod data base during device registration.
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@ -35,6 +35,7 @@
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/can.h>
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#include <linux/can/dev.h>
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@ -603,6 +604,8 @@ static int c_can_start(struct net_device *dev)
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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/* activate pins */
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pinctrl_pm_select_default_state(dev->dev.parent);
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return 0;
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}
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@ -611,6 +614,9 @@ static void c_can_stop(struct net_device *dev)
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struct c_can_priv *priv = netdev_priv(dev);
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c_can_irq_control(priv, false);
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/* deactivate pins */
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pinctrl_pm_select_sleep_state(dev->dev.parent);
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priv->can.state = CAN_STATE_STOPPED;
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}
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@ -1244,6 +1250,13 @@ int register_c_can_dev(struct net_device *dev)
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struct c_can_priv *priv = netdev_priv(dev);
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int err;
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/* Deactivate pins to prevent DRA7 DCAN IP from being
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* stuck in transition when module is disabled.
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* Pins are activated in c_can_start() and deactivated
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* in c_can_stop()
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*/
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pinctrl_pm_select_sleep_state(dev->dev.parent);
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c_can_pm_runtime_enable(priv);
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dev->flags |= IFF_ECHO; /* we support local echo */
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@ -169,6 +169,28 @@ enum c_can_dev_id {
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BOSCH_D_CAN,
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};
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struct raminit_bits {
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u8 start;
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u8 done;
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};
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struct c_can_driver_data {
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enum c_can_dev_id id;
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/* RAMINIT register description. Optional. */
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const struct raminit_bits *raminit_bits; /* Array of START/DONE bit positions */
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u8 raminit_num; /* Number of CAN instances on the SoC */
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bool raminit_pulse; /* If set, sets and clears START bit (pulse) */
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};
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/* Out of band RAMINIT register access via syscon regmap */
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struct c_can_raminit {
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struct regmap *syscon; /* for raminit ctrl. reg. access */
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unsigned int reg; /* register index within syscon */
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struct raminit_bits bits;
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bool needs_pulse;
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};
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/* c_can private data structure */
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struct c_can_priv {
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struct can_priv can; /* must be the first member */
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@ -186,8 +208,7 @@ struct c_can_priv {
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const u16 *regs;
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void *priv; /* for board-specific data */
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enum c_can_dev_id type;
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u32 __iomem *raminit_ctrlreg;
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int instance;
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struct c_can_raminit raminit_sys; /* RAMINIT via syscon regmap */
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void (*raminit) (const struct c_can_priv *priv, bool enable);
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u32 comm_rcv_high;
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u32 rxmasked;
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@ -32,14 +32,13 @@
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/can/dev.h>
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#include "c_can.h"
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#define CAN_RAMINIT_START_MASK(i) (0x001 << (i))
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#define CAN_RAMINIT_DONE_MASK(i) (0x100 << (i))
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#define CAN_RAMINIT_ALL_MASK(i) (0x101 << (i))
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#define DCAN_RAM_INIT_BIT (1 << 3)
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static DEFINE_SPINLOCK(raminit_lock);
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/*
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@ -72,39 +71,63 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
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writew(val, priv->base + 2 * priv->regs[index]);
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}
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static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
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u32 val)
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static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
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u32 mask, u32 val)
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{
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const struct c_can_raminit *raminit = &priv->raminit_sys;
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int timeout = 0;
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u32 ctrl = 0;
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/* We look only at the bits of our instance. */
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val &= mask;
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while ((readl(priv->raminit_ctrlreg) & mask) != val)
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do {
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udelay(1);
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timeout++;
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regmap_read(raminit->syscon, raminit->reg, &ctrl);
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if (timeout == 1000) {
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dev_err(&priv->dev->dev, "%s: time out\n", __func__);
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break;
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}
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} while ((ctrl & mask) != val);
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}
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static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
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static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
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{
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u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance);
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u32 ctrl;
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const struct c_can_raminit *raminit = &priv->raminit_sys;
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u32 ctrl = 0;
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u32 mask;
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spin_lock(&raminit_lock);
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ctrl = readl(priv->raminit_ctrlreg);
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mask = 1 << raminit->bits.start | 1 << raminit->bits.done;
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regmap_read(raminit->syscon, raminit->reg, &ctrl);
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/* We clear the done and start bit first. The start bit is
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* looking at the 0 -> transition, but is not self clearing;
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* And we clear the init done bit as well.
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* NOTE: DONE must be written with 1 to clear it.
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*/
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ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance);
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ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
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writel(ctrl, priv->raminit_ctrlreg);
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ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
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c_can_hw_raminit_wait_ti(priv, mask, ctrl);
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ctrl &= ~(1 << raminit->bits.start);
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ctrl |= 1 << raminit->bits.done;
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regmap_write(raminit->syscon, raminit->reg, ctrl);
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ctrl &= ~(1 << raminit->bits.done);
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c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
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if (enable) {
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/* Set start bit and wait for the done bit. */
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ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
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writel(ctrl, priv->raminit_ctrlreg);
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ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
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c_can_hw_raminit_wait_ti(priv, mask, ctrl);
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ctrl |= 1 << raminit->bits.start;
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regmap_write(raminit->syscon, raminit->reg, ctrl);
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/* clear START bit if start pulse is needed */
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if (raminit->needs_pulse) {
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ctrl &= ~(1 << raminit->bits.start);
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regmap_write(raminit->syscon, raminit->reg, ctrl);
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}
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ctrl |= 1 << raminit->bits.done;
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c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
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}
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spin_unlock(&raminit_lock);
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}
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@ -159,26 +182,60 @@ static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
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}
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}
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static const struct c_can_driver_data c_can_drvdata = {
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.id = BOSCH_C_CAN,
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};
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static const struct c_can_driver_data d_can_drvdata = {
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.id = BOSCH_D_CAN,
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};
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static const struct raminit_bits dra7_raminit_bits[] = {
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[0] = { .start = 3, .done = 1, },
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[1] = { .start = 5, .done = 2, },
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};
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static const struct c_can_driver_data dra7_dcan_drvdata = {
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.id = BOSCH_D_CAN,
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.raminit_num = ARRAY_SIZE(dra7_raminit_bits),
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.raminit_bits = dra7_raminit_bits,
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.raminit_pulse = true,
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};
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static const struct raminit_bits am3352_raminit_bits[] = {
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[0] = { .start = 0, .done = 8, },
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[1] = { .start = 1, .done = 9, },
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};
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static const struct c_can_driver_data am3352_dcan_drvdata = {
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.id = BOSCH_D_CAN,
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.raminit_num = ARRAY_SIZE(am3352_raminit_bits),
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.raminit_bits = am3352_raminit_bits,
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};
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static struct platform_device_id c_can_id_table[] = {
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[BOSCH_C_CAN_PLATFORM] = {
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{
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.name = KBUILD_MODNAME,
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.driver_data = BOSCH_C_CAN,
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.driver_data = (kernel_ulong_t)&c_can_drvdata,
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},
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[BOSCH_C_CAN] = {
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{
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.name = "c_can",
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.driver_data = BOSCH_C_CAN,
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.driver_data = (kernel_ulong_t)&c_can_drvdata,
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},
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[BOSCH_D_CAN] = {
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{
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.name = "d_can",
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.driver_data = BOSCH_D_CAN,
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}, {
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}
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.driver_data = (kernel_ulong_t)&d_can_drvdata,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(platform, c_can_id_table);
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static const struct of_device_id c_can_of_table[] = {
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{ .compatible = "bosch,c_can", .data = &c_can_id_table[BOSCH_C_CAN] },
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{ .compatible = "bosch,d_can", .data = &c_can_id_table[BOSCH_D_CAN] },
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{ .compatible = "bosch,c_can", .data = &c_can_drvdata },
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{ .compatible = "bosch,d_can", .data = &d_can_drvdata },
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{ .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata },
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{ .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata },
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{ .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, c_can_of_table);
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@ -190,21 +247,20 @@ static int c_can_plat_probe(struct platform_device *pdev)
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struct net_device *dev;
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struct c_can_priv *priv;
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const struct of_device_id *match;
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const struct platform_device_id *id;
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struct resource *mem, *res;
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struct resource *mem;
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int irq;
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struct clk *clk;
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const struct c_can_driver_data *drvdata;
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struct device_node *np = pdev->dev.of_node;
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if (pdev->dev.of_node) {
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match = of_match_device(c_can_of_table, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Failed to find matching dt id\n");
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ret = -EINVAL;
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goto exit;
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}
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id = match->data;
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match = of_match_device(c_can_of_table, &pdev->dev);
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if (match) {
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drvdata = match->data;
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} else if (pdev->id_entry->driver_data) {
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drvdata = (struct c_can_driver_data *)
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platform_get_device_id(pdev)->driver_data;
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} else {
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id = platform_get_device_id(pdev);
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return -ENODEV;
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}
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/* get the appropriate clk */
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@ -236,7 +292,7 @@ static int c_can_plat_probe(struct platform_device *pdev)
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}
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priv = netdev_priv(dev);
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switch (id->driver_data) {
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switch (drvdata->id) {
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case BOSCH_C_CAN:
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priv->regs = reg_map_c_can;
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switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
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@ -263,27 +319,50 @@ static int c_can_plat_probe(struct platform_device *pdev)
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priv->read_reg32 = d_can_plat_read_reg32;
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priv->write_reg32 = d_can_plat_write_reg32;
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if (pdev->dev.of_node)
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priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can");
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else
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priv->instance = pdev->id;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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/* Not all D_CAN modules have a separate register for the D_CAN
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* RAM initialization. Use default RAM init bit in D_CAN module
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* if not specified in DT.
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/* Check if we need custom RAMINIT via syscon. Mostly for TI
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* platforms. Only supported with DT boot.
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*/
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if (!res) {
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priv->raminit = c_can_hw_raminit;
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break;
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}
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if (np && of_property_read_bool(np, "syscon-raminit")) {
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u32 id;
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struct c_can_raminit *raminit = &priv->raminit_sys;
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priv->raminit_ctrlreg = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!priv->raminit_ctrlreg || priv->instance < 0)
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dev_info(&pdev->dev, "control memory is not used for raminit\n");
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else
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priv->raminit = c_can_hw_raminit_ti;
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ret = -EINVAL;
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raminit->syscon = syscon_regmap_lookup_by_phandle(np,
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"syscon-raminit");
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if (IS_ERR(raminit->syscon)) {
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/* can fail with -EPROBE_DEFER */
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ret = PTR_ERR(raminit->syscon);
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free_c_can_dev(dev);
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return ret;
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}
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if (of_property_read_u32_index(np, "syscon-raminit", 1,
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&raminit->reg)) {
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dev_err(&pdev->dev,
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"couldn't get the RAMINIT reg. offset!\n");
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goto exit_free_device;
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}
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if (of_property_read_u32_index(np, "syscon-raminit", 2,
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&id)) {
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dev_err(&pdev->dev,
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"couldn't get the CAN instance ID\n");
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goto exit_free_device;
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}
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if (id >= drvdata->raminit_num) {
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dev_err(&pdev->dev,
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"Invalid CAN instance ID\n");
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goto exit_free_device;
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}
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raminit->bits = drvdata->raminit_bits[id];
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raminit->needs_pulse = drvdata->raminit_pulse;
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priv->raminit = c_can_hw_raminit_syscon;
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} else {
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priv->raminit = c_can_hw_raminit;
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}
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break;
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default:
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ret = -EINVAL;
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@ -295,7 +374,7 @@ static int c_can_plat_probe(struct platform_device *pdev)
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priv->device = &pdev->dev;
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priv->can.clock.freq = clk_get_rate(clk);
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priv->priv = clk;
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priv->type = id->driver_data;
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priv->type = drvdata->id;
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platform_set_drvdata(pdev, dev);
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SET_NETDEV_DEV(dev, &pdev->dev);
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