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arm: Cleanup the irq namespace 

Convert to the new function names. Automated with coccinelle.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner 2011-03-24 13:25:22 +01:00
parent 25a5662a13
commit 6845664a6a
140 changed files with 626 additions and 610 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/common/gic.c
View File

@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct gic_chip_data *chip_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
struct gic_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, gic_irq;
unsigned long status;
@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
{
if (gic_nr >= MAX_GIC_NR)
BUG();
if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
BUG();
set_irq_chained_handler(irq, gic_handle_cascade_irq);
irq_set_chained_handler(irq, gic_handle_cascade_irq);
}
static void __init gic_dist_init(struct gic_chip_data *gic,
@ -319,9 +319,9 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
* Setup the Linux IRQ subsystem.
*/
for (i = irq_start; i < irq_limit; i++) {
set_irq_chip(i, &gic_chip);
set_irq_chip_data(i, gic);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &gic_chip);
irq_set_chip_data(i, gic);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}

4
arch/arm/common/it8152.c
View File

@ -88,8 +88,8 @@ void it8152_init_irq(void)
__raw_writel((0), IT8152_INTC_LDCNIRR);
for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
set_irq_chip(irq, &it8152_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &it8152_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

18
arch/arm/common/locomo.c
View File

@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = {
static void locomo_handler(unsigned int irq, struct irq_desc *desc)
{
struct locomo *lchip = get_irq_chip_data(irq);
struct locomo *lchip = irq_get_chip_data(irq);
int req, i;
/* Acknowledge the parent IRQ */
@ -197,15 +197,15 @@ static void locomo_setup_irq(struct locomo *lchip)
/*
* Install handler for IRQ_LOCOMO_HW.
*/
set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
set_irq_chip_data(lchip->irq, lchip);
set_irq_chained_handler(lchip->irq, locomo_handler);
irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
irq_set_chip_data(lchip->irq, lchip);
irq_set_chained_handler(lchip->irq, locomo_handler);
/* Install handlers for IRQ_LOCOMO_* */
for ( ; irq <= lchip->irq_base + 3; irq++) {
set_irq_chip(irq, &locomo_chip);
set_irq_chip_data(irq, lchip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &locomo_chip);
irq_set_chip_data(irq, lchip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
@ -476,8 +476,8 @@ static void __locomo_remove(struct locomo *lchip)
device_for_each_child(lchip->dev, NULL, locomo_remove_child);
if (lchip->irq != NO_IRQ) {
set_irq_chained_handler(lchip->irq, NULL);
set_irq_data(lchip->irq, NULL);
irq_set_chained_handler(lchip->irq, NULL);
irq_set_handler_data(lchip->irq, NULL);
}
iounmap(lchip->base);

24
arch/arm/common/sa1111.c
View File

@ -202,7 +202,7 @@ static void
sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int stat0, stat1, i;
struct sa1111 *sachip = get_irq_data(irq);
struct sa1111 *sachip = irq_get_handler_data(irq);
void __iomem *mapbase = sachip->base + SA1111_INTC;
stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
set_irq_chip(irq, &sa1111_low_chip);
set_irq_chip_data(irq, sachip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &sa1111_low_chip);
irq_set_chip_data(irq, sachip);
irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
set_irq_chip(irq, &sa1111_high_chip);
set_irq_chip_data(irq, sachip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &sa1111_high_chip);
irq_set_chip_data(irq, sachip);
irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/*
* Register SA1111 interrupt
*/
set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
set_irq_data(sachip->irq, sachip);
set_irq_chained_handler(sachip->irq, sa1111_irq_handler);
irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
irq_set_handler_data(sachip->irq, sachip);
irq_set_chained_handler(sachip->irq, sa1111_irq_handler);
}
/*
@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip)
clk_disable(sachip->clk);
if (sachip->irq != NO_IRQ) {
set_irq_chained_handler(sachip->irq, NULL);
set_irq_data(sachip->irq, NULL);
irq_set_chained_handler(sachip->irq, NULL);
irq_set_handler_data(sachip->irq, NULL);
release_mem_region(sachip->phys + SA1111_INTC, 512);
}

6
arch/arm/common/vic.c
View File

@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base,
if (vic_sources & (1 << i)) {
unsigned int irq = irq_start + i;
set_irq_chip(irq, &vic_chip);
set_irq_chip_data(irq, base);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &vic_chip);
irq_set_chip_data(irq, base);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

6
arch/arm/kernel/ecard.c
View File

@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type)
*/
if (slot < 8) {
ec->irq = 32 + slot;
set_irq_chip(ec->irq, &ecard_chip);
set_irq_handler(ec->irq, handle_level_irq);
irq_set_chip(ec->irq, &ecard_chip);
irq_set_handler(ec->irq, handle_level_irq);
set_irq_flags(ec->irq, IRQF_VALID);
}
@ -1103,7 +1103,7 @@ static int __init ecard_init(void)
irqhw = ecard_probeirqhw();
set_irq_chained_handler(IRQ_EXPANSIONCARD,
irq_set_chained_handler(IRQ_EXPANSIONCARD,
irqhw ? ecard_irqexp_handler : ecard_irq_handler);
ecard_proc_init();

6
arch/arm/mach-at91/at91cap9_devices.c
View File

@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
return;
if (cpu_is_at91cap9_revB())
set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = {
void __init at91_add_device_usba(struct usba_platform_data *data)
{
if (cpu_is_at91cap9_revB()) {
set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
AT91_MATRIX_UDPHS_BYPASS_LOCK);
}
@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
return;
if (cpu_is_at91cap9_revB())
set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */

10
arch/arm/mach-at91/gpio.c
View File

@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
else
wakeups[bank] &= ~mask;
set_irq_wake(gpio_chip[bank].bank->id, state);
irq_set_irq_wake(gpio_chip[bank].bank->id, state);
return 0;
}
@ -511,8 +511,8 @@ void __init at91_gpio_irq_setup(void)
* Can use the "simple" and not "edge" handler since it's
* shorter, and the AIC handles interrupts sanely.
*/
set_irq_chip(pin, &gpio_irqchip);
set_irq_handler(pin, handle_simple_irq);
irq_set_chip(pin, &gpio_irqchip);
irq_set_handler(pin, handle_simple_irq);
set_irq_flags(pin, IRQF_VALID);
}
@ -523,8 +523,8 @@ void __init at91_gpio_irq_setup(void)
if (prev && prev->next == this)
continue;
set_irq_chip_data(id, this);
set_irq_chained_handler(id, gpio_irq_handler);
irq_set_chip_data(id, this);
irq_set_chained_handler(id, gpio_irq_handler);
}
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
}

4
arch/arm/mach-at91/irq.c
View File

@ -143,8 +143,8 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
/* Active Low interrupt, with the specified priority */
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
set_irq_chip(i, &at91_aic_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &at91_aic_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */

10
arch/arm/mach-bcmring/irq.c
View File

@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip,
unsigned int i;
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;
set_irq_chip(irq, chip);
set_irq_chip_data(irq, base);
irq_set_chip(irq, chip);
irq_set_chip_data(irq, base);
if (vic_sources & (1 << i)) {
set_irq_handler(irq, handle_level_irq);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
@ -119,9 +119,9 @@ void __init bcmring_init_irq(void)
/* special cases */
if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
set_irq_handler(IRQ_GPIO0, handle_simple_irq);
irq_set_handler(IRQ_GPIO0, handle_simple_irq);
}
if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
set_irq_handler(IRQ_GPIO1, handle_simple_irq);
irq_set_handler(IRQ_GPIO1, handle_simple_irq);
}
}

8
arch/arm/mach-clps711x/irq.c
View File

@ -112,13 +112,13 @@ void __init clps711x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) {
if (INT1_IRQS & (1 << i)) {
set_irq_handler(i, handle_level_irq);
set_irq_chip(i, &int1_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip(i, &int1_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
if (INT2_IRQS & (1 << i)) {
set_irq_handler(i, handle_level_irq);
set_irq_chip(i, &int2_chip);
irq_set_handler(i, handle_level_irq);
irq_set_chip(i, &int2_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

4
arch/arm/mach-davinci/cp_intc.c
View File

@ -167,9 +167,9 @@ void __init cp_intc_init(void)
/* Set up genirq dispatching for cp_intc */
for (i = 0; i < num_irq; i++) {
set_irq_chip(i, &cp_intc_irq_chip);
irq_set_chip(i, &cp_intc_irq_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
set_irq_handler(i, handle_edge_irq);
irq_set_handler(i, handle_edge_irq);
}
/* Enable global interrupt */

32
arch/arm/mach-davinci/gpio.c
View File

@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{
struct davinci_gpio_regs __iomem *g;
g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
return g;
}
@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(struct irq_data *d)
{
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
u32 mask = (u32) irq_data_get_irq_handler_data(d);
__raw_writel(mask, &g->clr_falling);
__raw_writel(mask, &g->clr_rising);
@ -217,7 +217,7 @@ static void gpio_irq_disable(struct irq_data *d)
static void gpio_irq_enable(struct irq_data *d)
{
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
u32 mask = (u32) irq_data_get_irq_handler_data(d);
unsigned status = irqd_get_trigger_type(d);
status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
@ -233,7 +233,7 @@ static void gpio_irq_enable(struct irq_data *d)
static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
u32 mask = (u32) irq_data_get_irq_handler_data(d);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
@ -276,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
status >>= 16;
/* now demux them to the right lowlevel handler */
n = (int)get_irq_data(irq);
n = (int)irq_get_handler_data(irq);
while (status) {
res = ffs(status);
n += res;
@ -314,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
{
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d);
u32 mask = (u32) irq_data_get_irq_handler_data(d);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
@ -397,9 +397,9 @@ static int __init davinci_gpio_irq_setup(void)
/* set the direct IRQs up to use that irqchip */
for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
set_irq_chip(irq, &gpio_irqchip_unbanked);
set_irq_data(irq, (void *) __gpio_mask(gpio));
set_irq_chip_data(irq, (__force void *) g);
irq_set_chip(irq, &gpio_irqchip_unbanked);
irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
irq_set_chip_data(irq, (__force void *)g);
irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
}
@ -421,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void)
__raw_writel(~0, &g->clr_rising);
/* set up all irqs in this bank */
set_irq_chained_handler(bank_irq, gpio_irq_handler);
set_irq_chip_data(bank_irq, (__force void *) g);
set_irq_data(bank_irq, (void *) irq);
irq_set_chained_handler(bank_irq, gpio_irq_handler);
irq_set_chip_data(bank_irq, (__force void *)g);
irq_set_handler_data(bank_irq, (void *)irq);
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
set_irq_chip(irq, &gpio_irqchip);
set_irq_chip_data(irq, (__force void *) g);
set_irq_data(irq, (void *) __gpio_mask(gpio));
set_irq_handler(irq, handle_simple_irq);
irq_set_chip(irq, &gpio_irqchip);
irq_set_chip_data(irq, (__force void *)g);
irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
irq_set_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
}

6
arch/arm/mach-davinci/irq.c
View File

@ -154,11 +154,11 @@ void __init davinci_irq_init(void)
/* set up genirq dispatch for ARM INTC */
for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
set_irq_chip(i, &davinci_irq_chip_0);
irq_set_chip(i, &davinci_irq_chip_0);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (i != IRQ_TINT1_TINT34)
set_irq_handler(i, handle_edge_irq);
irq_set_handler(i, handle_edge_irq);
else
set_irq_handler(i, handle_level_irq);
irq_set_handler(i, handle_level_irq);
}
}

16
arch/arm/mach-dove/irq.c
View File

@ -102,14 +102,14 @@ void __init dove_init_irq(void)
*/
orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START);
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 32);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64);
@ -121,10 +121,10 @@ void __init dove_init_irq(void)
writel(0, PMU_INTERRUPT_CAUSE);
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
set_irq_chip(i, &pmu_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &pmu_irq_chip);
irq_set_handler(i, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
}

4
arch/arm/mach-ebsa110/core.c
View File

@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void)
local_irq_restore(flags);
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &ebsa110_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ebsa110_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

31
arch/arm/mach-ep93xx/gpio.c
View File

@ -231,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void)
for (gpio_irq = gpio_to_irq(0);
gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
set_irq_handler(gpio_irq, handle_level_irq);
irq_set_chip(gpio_irq, &ep93xx_gpio_irq_chip);
irq_set_handler(gpio_irq, handle_level_irq);
set_irq_flags(gpio_irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
ep93xx_gpio_ab_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
ep93xx_gpio_f_irq_handler);
}

14
arch/arm/mach-exynos4/irq-combiner.c
View File

@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data)
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct combiner_chip_data *chip_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
{
if (combiner_nr >= MAX_COMBINER_NR)
BUG();
if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
BUG();
set_irq_chained_handler(irq, combiner_handle_cascade_irq);
irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}
void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
@ -119,9 +119,9 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) {
set_irq_chip(i, &combiner_chip);
set_irq_chip_data(i, &combiner_data[combiner_nr]);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &combiner_chip);
irq_set_chip_data(i, &combiner_data[combiner_nr]);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

15
arch/arm/mach-exynos4/irq-eint.c
View File

@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
chip->irq_mask(&desc->irq_data);
@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void)
int irq;
for (irq = 0 ; irq <= 31 ; irq++) {
set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
set_irq_handler(IRQ_EINT(irq), handle_level_irq);
irq_set_chip(IRQ_EINT(irq), &exynos4_irq_eint);
irq_set_handler(IRQ_EINT(irq), handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
}
set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq);
set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
set_irq_chained_handler(exynos4_get_irq_nr(irq),
irq_set_handler_data(exynos4_get_irq_nr(irq),
&eint0_15_data[irq]);
irq_set_chained_handler(exynos4_get_irq_nr(irq),
exynos4_irq_eint0_15);
}

4
arch/arm/mach-footbridge/common.c
View File

@ -102,8 +102,8 @@ static void __init __fb_init_irq(void)
*CSR_FIQ_DISABLE = -1;
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
set_irq_chip(irq, &fb_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &fb_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}

10
arch/arm/mach-footbridge/isa-irq.c
View File

@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq)
if (host_irq != (unsigned int)-1) {
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
set_irq_chip(irq, &isa_lo_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &isa_lo_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
set_irq_chip(irq, &isa_hi_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &isa_hi_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq)
request_resource(&ioport_resource, &pic2_resource);
setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
set_irq_chained_handler(host_irq, isa_irq_handler);
irq_set_chained_handler(host_irq, isa_irq_handler);
/*
* On the NetWinder, don't automatically

8
arch/arm/mach-gemini/gpio.c
View File

@ -217,13 +217,13 @@ void __init gemini_gpio_init(void)
for (j = GPIO_IRQ_BASE + i * 32;
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
set_irq_chip(j, &gpio_irq_chip);
set_irq_handler(j, handle_edge_irq);
irq_set_chip(j, &gpio_irq_chip);
irq_set_handler(j, handle_edge_irq);
set_irq_flags(j, IRQF_VALID);
}
set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
set_irq_data(IRQ_GPIO(i), (void *)i);
irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
irq_set_handler_data(IRQ_GPIO(i), (void *)i);
}
BUG_ON(gpiochip_add(&gemini_gpio_chip));

6
arch/arm/mach-gemini/irq.c
View File

@ -81,13 +81,13 @@ void __init gemini_init_irq(void)
request_resource(&iomem_resource, &irq_resource);
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &gemini_irq_chip);
irq_set_chip(i, &gemini_irq_chip);
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
set_irq_handler(i, handle_edge_irq);
irq_set_handler(i, handle_edge_irq);
mode |= 1 << i;
level |= 1 << i;
} else {
set_irq_handler(i, handle_level_irq);
irq_set_handler(i, handle_level_irq);
}
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}

22
arch/arm/mach-h720x/common.c
View File

@ -199,29 +199,29 @@ void __init h720x_init_irq (void)
/* Initialize global IRQ's, fast path */
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
set_irq_chip(irq, &h720x_global_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &h720x_global_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Initialize multiplexed IRQ's, slow path */
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &h720x_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
#ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &h720x_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif
/* Enable multiplexed irq's */

6
arch/arm/mach-h720x/cpu-h7202.c
View File

@ -202,11 +202,11 @@ void __init h7202_init_irq (void)
for (irq = IRQ_TIMER1;
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
__mask_timerx_irq(irq);
set_irq_chip(irq, &h7202_timerx_chip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &h7202_timerx_chip);
irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
h720x_init_irq();
}

10
arch/arm/mach-iop13xx/irq.c
View File

@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void)
for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
if (i < 32)
set_irq_chip(i, &iop13xx_irqchip1);
irq_set_chip(i, &iop13xx_irqchip1);
else if (i < 64)
set_irq_chip(i, &iop13xx_irqchip2);
irq_set_chip(i, &iop13xx_irqchip2);
else if (i < 96)
set_irq_chip(i, &iop13xx_irqchip3);
irq_set_chip(i, &iop13xx_irqchip3);
else
set_irq_chip(i, &iop13xx_irqchip4);
irq_set_chip(i, &iop13xx_irqchip4);
set_irq_handler(i, handle_level_irq);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}

6
arch/arm/mach-iop13xx/msi.c
View File

@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
void __init iop13xx_msi_init(void)
{
set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
}
/*
@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
if (irq < 0)
return irq;
set_irq_msi(irq, desc);
irq_set_msi_desc(irq, desc);
msg.address_hi = 0x0;
msg.address_lo = IOP13XX_MU_MIMR_PCI;
@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
write_msi_msg(irq, &msg);
set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
return 0;
}

4
arch/arm/mach-iop32x/irq.c
View File

@ -68,8 +68,8 @@ void __init iop32x_init_irq(void)
*IOP3XX_PCIIRSR = 0x0f;
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ext_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &ext_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

5
arch/arm/mach-iop33x/irq.c
View File

@ -110,8 +110,9 @@ void __init iop33x_init_irq(void)
*IOP3XX_PCIIRSR = 0x0f;
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i,
(i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}

20
arch/arm/mach-ixp2000/core.c
View File

@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void)
*/
for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
set_irq_chip(irq, &ixp2000_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixp2000_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
} else set_irq_flags(irq, 0);
}
@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void)
for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
IXP2000_VALID_ERR_IRQ_MASK) {
set_irq_chip(irq, &ixp2000_err_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixp2000_err_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
else
set_irq_flags(irq, 0);
}
set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixp2000_GPIO_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
/*
* Enable PCI irqs. The actual PCI[AB] decoding is done in
@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void)
*/
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
set_irq_chip(irq, &ixp2000_pci_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixp2000_pci_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}

6
arch/arm/mach-ixp2000/ixdp2x00.c
View File

@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
*board_irq_mask = 0xffffffff;
for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixdp2x00_cpld_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
/* Hook into PCI interrupt */
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
}
/*************************************************************************

6
arch/arm/mach-ixp2000/ixdp2x01.c
View File

@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void)
for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
if (irq & valid_irq_mask) {
set_irq_chip(irq, &ixdp2x01_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixdp2x01_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
} else {
set_irq_flags(irq, 0);
@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void)
}
/* Hook into PCI interrupts */
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
}

14
arch/arm/mach-ixp23xx/core.c
View File

@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
{
switch (type) {
case IXP23XX_IRQ_LEVEL:
set_irq_chip(irq, &ixp23xx_irq_level_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixp23xx_irq_level_chip);
irq_set_handler(irq, handle_level_irq);
break;
case IXP23XX_IRQ_EDGE:
set_irq_chip(irq, &ixp23xx_irq_edge_chip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &ixp23xx_irq_edge_chip);
irq_set_handler(irq, handle_edge_irq);
break;
}
set_irq_flags(irq, IRQF_VALID);
@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void)
}
for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
set_irq_chip(irq, &ixp23xx_pci_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixp23xx_pci_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
}

12
arch/arm/mach-ixp23xx/ixdp2351.c
View File

@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void)
irq++) {
if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq);
set_irq_chip(irq, &ixdp2351_inta_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixdp2351_inta_chip);
}
}
@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void)
irq++) {
if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq);
set_irq_chip(irq, &ixdp2351_intb_chip);
irq_set_handler(irq, handle_level_irq);
irq_set_chip(irq, &ixdp2351_intb_chip);
}
}
set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
}
/*

4
arch/arm/mach-ixp23xx/roadrunner.c
View File

@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
static void __init roadrunner_pci_preinit(void)
{
set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp23xx_pci_preinit();
}

8
arch/arm/mach-ixp4xx/avila-pci.c
View File

@ -39,10 +39,10 @@
void __init avila_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/common.c
View File

@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void)
/* Default to all level triggered */
for(i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ixp4xx_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &ixp4xx_irq_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}

4
arch/arm/mach-ixp4xx/coyote-pci.c
View File

@ -32,8 +32,8 @@
void __init coyote_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

12
arch/arm/mach-ixp4xx/dsmg600-pci.c
View File

@ -35,12 +35,12 @@
void __init dsmg600_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

6
arch/arm/mach-ixp4xx/fsg-pci.c
View File

@ -32,9 +32,9 @@
void __init fsg_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/gateway7001-pci.c
View File

@ -29,8 +29,8 @@
void __init gateway7001_pci_preinit(void)
{
set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

12
arch/arm/mach-ixp4xx/goramo_mlr.c
View File

@ -420,8 +420,8 @@ static void __init gmlr_init(void)
gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_control(CONTROL_HSS0_DTR_N, 1);
set_control(CONTROL_HSS1_DTR_N, 1);
@ -441,10 +441,10 @@ static void __init gmlr_init(void)
#ifdef CONFIG_PCI
static void __init gmlr_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/gtwx5715-pci.c
View File

@ -43,8 +43,8 @@
*/
void __init gtwx5715_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

8
arch/arm/mach-ixp4xx/ixdp425-pci.c
View File

@ -36,10 +36,10 @@
void __init ixdp425_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/ixdpg425-pci.c
View File

@ -25,8 +25,8 @@
void __init ixdpg425_pci_preinit(void)
{
set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

10
arch/arm/mach-ixp4xx/nas100d-pci.c
View File

@ -33,11 +33,11 @@
void __init nas100d_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

6
arch/arm/mach-ixp4xx/nslu2-pci.c
View File

@ -32,9 +32,9 @@
void __init nslu2_pci_preinit(void)
{
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/vulcan-pci.c
View File

@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void)
pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
(int)(pci_cardbus_mem_size >> 20));
#endif
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

4
arch/arm/mach-ixp4xx/wg302v2-pci.c
View File

@ -29,8 +29,8 @@
void __init wg302v2_pci_preinit(void)
{
set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit();
}

15
arch/arm/mach-kirkwood/irq.c
View File

@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void)
*/
orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START + 32);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23,
gpio_irq_handler);
}

2
arch/arm/mach-ks8695/gpio.c
View File

@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
local_irq_restore(flags);
/* Set IRQ triggering type */
set_irq_type(gpio_irq[pin], type);
irq_set_irq_type(gpio_irq[pin], type);
/* enable interrupt mode */
ks8695_gpio_mode(pin, 0);

16
arch/arm/mach-ks8695/irq.c
View File

@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
}
if (level_triggered) {
set_irq_chip(d->irq, &ks8695_irq_level_chip);
set_irq_handler(d->irq, handle_level_irq);
irq_set_chip(d->irq, &ks8695_irq_level_chip);
irq_set_handler(d->irq, handle_level_irq);
}
else {
set_irq_chip(d->irq, &ks8695_irq_edge_chip);
set_irq_handler(d->irq, handle_edge_irq);
irq_set_chip(d->irq, &ks8695_irq_edge_chip);
irq_set_handler(d->irq, handle_edge_irq);
}
__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
@ -158,16 +158,16 @@ void __init ks8695_init_irq(void)
case KS8695_IRQ_UART_RX:
case KS8695_IRQ_COMM_TX:
case KS8695_IRQ_COMM_RX:
set_irq_chip(irq, &ks8695_irq_level_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &ks8695_irq_level_chip);
irq_set_handler(irq, handle_level_irq);
break;
/* Edge-triggered interrupts */
default:
/* clear pending bit */
ks8695_irq_ack(irq_get_irq_data(irq));
set_irq_chip(irq, &ks8695_irq_edge_chip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &ks8695_irq_edge_chip);
irq_set_handler(irq, handle_edge_irq);
}
set_irq_flags(irq, IRQF_VALID);

10
arch/arm/mach-lpc32xx/irq.c
View File

@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
}
/* Ok to use the level handler for all types */
set_irq_handler(d->irq, handle_level_irq);
irq_set_handler(d->irq, handle_level_irq);
return 0;
}
@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void)
/* Configure supported IRQ's */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &lpc32xx_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &lpc32xx_irq_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void)
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
/* MIC SUBIRQx interrupts will route handling to the chain handlers */
set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
/* Initially disable all wake events */
__raw_writel(0, LPC32XX_CLKPWR_P01_ER);

18
arch/arm/mach-mmp/irq-mmp2.c
View File

@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
if (chip->irq_ack)
chip->irq_ack(d);
set_irq_chip(irq, chip);
irq_set_chip(irq, chip);
set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq);
irq_set_handler(irq, handle_level_irq);
}
}
@ -122,7 +122,7 @@ void __init mmp2_init_icu(void)
for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
icu_mask_irq(irq_get_irq_data(irq));
set_irq_chip(irq, &icu_irq_chip);
irq_set_chip(irq, &icu_irq_chip);
set_irq_flags(irq, IRQF_VALID);
switch (irq) {
@ -133,7 +133,7 @@ void __init mmp2_init_icu(void)
case IRQ_MMP2_SSP_MUX:
break;
default:
set_irq_handler(irq, handle_level_irq);
irq_set_handler(irq, handle_level_irq);
break;
}
}
@ -149,9 +149,9 @@ void __init mmp2_init_icu(void)
init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
}

4
arch/arm/mach-mmp/irq-pxa168.c
View File

@ -48,8 +48,8 @@ void __init icu_init_irq(void)
for (irq = 0; irq < 64; irq++) {
icu_mask_irq(irq_get_irq_data(irq));
set_irq_chip(irq, &icu_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &icu_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}

2
arch/arm/mach-msm/board-msm8960.c
View File

@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void)
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq);
irq_set_handler(i, handle_percpu_irq);
}
}

2
arch/arm/mach-msm/board-msm8x60.c
View File

@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void)
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq);
irq_set_handler(i, handle_percpu_irq);
}
}

10
arch/arm/mach-msm/board-trout-gpio.c
View File

@ -214,17 +214,17 @@ int __init trout_init_gpio(void)
{
int i;
for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
set_irq_chip(i, &trout_gpio_irq_chip);
set_irq_handler(i, handle_edge_irq);
irq_set_chip(i, &trout_gpio_irq_chip);
irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
gpiochip_add(&msm_gpio_banks[i].chip);
set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
set_irq_wake(MSM_GPIO_TO_INT(17), 1);
irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
return 0;
}

2
arch/arm/mach-msm/board-trout-mmc.c
View File

@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev)
if (IS_ERR(vreg_sdslot))
return PTR_ERR(vreg_sdslot);
set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
if (!opt_disable_sdcard)
msm_add_sdcc(2, &trout_sdslot_data,

12
arch/arm/mach-msm/gpio-v2.c
View File

@ -328,12 +328,12 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
if (on) {
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
set_bit(gpio, msm_gpio.wake_irqs);
} else {
clear_bit(gpio, msm_gpio.wake_irqs);
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
}
return 0;
@ -362,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
set_irq_chip(irq, &msm_gpio_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &msm_gpio_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
msm_summary_irq_handler);
return 0;
}
@ -379,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev)
if (ret < 0)
return ret;
set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
return 0;
}

14
arch/arm/mach-msm/gpio.c
View File

@ -354,9 +354,9 @@ static int __init msm_init_gpio(void)
msm_gpio_chips[j].chip.base +
msm_gpio_chips[j].chip.ngpio)
j++;
set_irq_chip_data(i, &msm_gpio_chips[j]);
set_irq_chip(i, &msm_gpio_irq_chip);
set_irq_handler(i, handle_edge_irq);
irq_set_chip_data(i, &msm_gpio_chips[j]);
irq_set_chip(i, &msm_gpio_irq_chip);
irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
@ -366,10 +366,10 @@ static int __init msm_init_gpio(void)
gpiochip_add(&msm_gpio_chips[i].chip);
}
set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
set_irq_wake(INT_GPIO_GROUP1, 1);
set_irq_wake(INT_GPIO_GROUP2, 2);
irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
irq_set_irq_wake(INT_GPIO_GROUP1, 1);
irq_set_irq_wake(INT_GPIO_GROUP2, 2);
return 0;
}

4
arch/arm/mach-msm/irq-vic.c
View File

@ -357,8 +357,8 @@ void __init msm_init_irq(void)
writel(3, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
set_irq_chip(n, &msm_irq_chip);
set_irq_handler(n, handle_level_irq);
irq_set_chip(n, &msm_irq_chip);
irq_set_handler(n, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
}

4
arch/arm/mach-msm/irq.c
View File

@ -145,8 +145,8 @@ void __init msm_init_irq(void)
writel(1, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
set_irq_chip(n, &msm_irq_chip);
set_irq_handler(n, handle_level_irq);
irq_set_chip(n, &msm_irq_chip);
irq_set_handler(n, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
}

8
arch/arm/mach-msm/sirc.c
View File

@ -158,15 +158,15 @@ void __init msm_init_sirc(void)
wake_enable = 0;
for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
set_irq_chip(i, &sirc_irq_chip);
set_irq_handler(i, handle_edge_irq);
irq_set_chip(i, &sirc_irq_chip);
irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
sirc_irq_handler);
set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
}
return;
}

8
arch/arm/mach-mv78xx0/irq.c
View File

@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void)
orion_gpio_init(0, 32, GPIO_VIRT_BASE,
mv78xx0_core_index() ? 0x18 : 0,
IRQ_MV78XX0_GPIO_START);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
}

8
arch/arm/mach-mx3/mach-mx31ads.c
View File

@ -199,12 +199,12 @@ static void __init mx31ads_init_expio(void)
__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
i++) {
set_irq_chip(i, &expio_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &expio_irq_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
}
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1

2
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View File

@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
gpio_direction_input(MBIMX51_TSC2007_GPIO);
set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
i2c_register_board_info(1, mbimx51_i2c_devices,
ARRAY_SIZE(mbimx51_i2c_devices));

10
arch/arm/mach-mxs/gpio.c
View File

@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 irq_stat;
struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
u32 gpio_irq_no_base = port->virtual_irq_start;
desc->irq_data.chip->irq_ack(&desc->irq_data);
@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
for (j = port[i].virtual_irq_start;
j < port[i].virtual_irq_start + 32; j++) {
set_irq_chip(j, &gpio_irq_chip);
set_irq_handler(j, handle_level_irq);
irq_set_chip(j, &gpio_irq_chip);
irq_set_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
/* setup one handler for each entry */
set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler);
set_irq_data(port[i].irq, &port[i]);
irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
irq_set_handler_data(port[i].irq, &port[i]);
/* register gpio chip */
port[i].chip.direction_input = mxs_gpio_direction_input;

4
arch/arm/mach-mxs/icoll.c
View File

@ -74,8 +74,8 @@ void __init icoll_init_irq(void)
mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxs_icoll_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &mxs_icoll_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}

6
arch/arm/mach-netx/generic.c
View File

@ -171,13 +171,13 @@ void __init netx_init_irq(void)
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
set_irq_chip(irq, &netx_hif_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &netx_hif_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
}
static int __init netx_init(void)

8
arch/arm/mach-ns9xxx/board-a9m9750dev.c
View File

@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void)
__func__);
for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
set_irq_chip(i, &a9m9750dev_fpga_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &a9m9750dev_fpga_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void)
REGSET(eic, SYS_EIC, LVEDG, LEVEL);
__raw_writel(eic, SYS_EIC(2));
set_irq_chained_handler(IRQ_NS9XXX_EXT2,
a9m9750dev_fpga_demux_handler);
irq_set_chained_handler(IRQ_NS9XXX_EXT2,
a9m9750dev_fpga_demux_handler);
}
void __init board_a9m9750dev_init_machine(void)

4
arch/arm/mach-ns9xxx/irq.c
View File

@ -67,8 +67,8 @@ void __init ns9xxx_init_irq(void)
__raw_writel(prio2irq(i), SYS_IVA(i));
for (i = 0; i <= 31; ++i) {
set_irq_chip(i, &ns9xxx_chip);
set_irq_handler(i, handle_fasteoi_irq);
irq_set_chip(i, &ns9xxx_chip);
irq_set_handler(i, handle_fasteoi_irq);
set_irq_flags(i, IRQF_VALID);
irq_set_status_flags(i, IRQ_LEVEL);
}

4
arch/arm/mach-nuc93x/irq.c
View File

@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void)
__raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
set_irq_chip(irqno, &nuc93x_irq_chip);
set_irq_handler(irqno, handle_level_irq);
irq_set_chip(irqno, &nuc93x_irq_chip);
irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}

6
arch/arm/mach-omap1/board-osk.c
View File

@ -276,7 +276,7 @@ static void __init osk_init_cf(void)
return;
}
/* the CF I/O IRQ is really active-low */
set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
}
static void __init osk_init_irq(void)
@ -482,7 +482,7 @@ static void __init osk_mistral_init(void)
omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
gpio_request(4, "ts_int");
gpio_direction_input(4);
set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
spi_register_board_info(mistral_boardinfo,
ARRAY_SIZE(mistral_boardinfo));
@ -500,7 +500,7 @@ static void __init osk_mistral_init(void)
int irq = gpio_to_irq(OMAP_MPUIO(2));
gpio_direction_input(OMAP_MPUIO(2));
set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_PM
/* share the IRQ in case someone wants to use the
* button for more than wakeup from system sleep.

8
arch/arm/mach-omap1/board-palmz71.c
View File

@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id)
{
if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) {
printk(KERN_INFO "PM: Power cable connected\n");
set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
IRQ_TYPE_EDGE_FALLING);
irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
IRQ_TYPE_EDGE_FALLING);
} else {
printk(KERN_INFO "PM: Power cable disconnected\n");
set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
IRQ_TYPE_EDGE_RISING);
}
return IRQ_HANDLED;
}

8
arch/arm/mach-omap1/board-voiceblue.c
View File

@ -279,10 +279,10 @@ static void __init voiceblue_init(void)
gpio_request(13, "16C554 irq");
gpio_request(14, "16C554 irq");
gpio_request(15, "16C554 irq");
set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;

10
arch/arm/mach-omap1/fpga.c
View File

@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void)
* The touchscreen interrupt is level-sensitive, so
* we'll use the regular mask_ack routine for it.
*/
set_irq_chip(i, &omap_fpga_irq_ack);
irq_set_chip(i, &omap_fpga_irq_ack);
}
else {
/*
* All FPGA interrupts except the touchscreen are
* edge-sensitive, so we won't mask them.
*/
set_irq_chip(i, &omap_fpga_irq);
irq_set_chip(i, &omap_fpga_irq);
}
set_irq_handler(i, handle_edge_irq);
irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void)
return;
}
gpio_direction_input(13);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
}

4
arch/arm/mach-omap1/irq.c
View File

@ -230,8 +230,8 @@ void __init omap_init_irq(void)
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_chip(j, &omap_irq_chip);
set_irq_handler(j, handle_level_irq);
irq_set_chip(j, &omap_irq_chip);
irq_set_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
}

2
arch/arm/mach-omap2/gpmc.c
View File

@ -743,7 +743,7 @@ static int __init gpmc_init(void)
/* initalize the irq_chained */
irq = OMAP_GPMC_IRQ_BASE;
for (cs = 0; cs < GPMC_CS_NUM; cs++) {
set_irq_chip_and_handler(irq, &dummy_irq_chip,
irq_set_chip_and_handler(irq, &dummy_irq_chip,
handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
irq++;

4
arch/arm/mach-omap2/irq.c
View File

@ -223,8 +223,8 @@ void __init omap_init_irq(void)
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
for (i = 0; i < nr_of_irqs; i++) {
set_irq_chip(i, &omap_irq_chip);
set_irq_handler(i, handle_level_irq);
irq_set_chip(i, &omap_irq_chip);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}

4
arch/arm/mach-orion5x/db88f5281-setup.c
View File

@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void)
pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void)
pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "db88f5281_pci_preinit faield "
"to set_irq_type pin %d\n", pin);

8
arch/arm/mach-orion5x/irq.c
View File

@ -34,8 +34,8 @@ void __init orion5x_init_irq(void)
* Initialize gpiolib for GPIOs 0-31.
*/
orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
}

4
arch/arm/mach-orion5x/rd88f5182-setup.c
View File

@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void)
pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
if (gpio_request(pin, "PCI IntA") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);
@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void)
pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
if (gpio_request(pin, "PCI IntB") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin);

2
arch/arm/mach-orion5x/terastation_pro2-setup.c
View File

@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void)
pin = TSP2_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "tsp2_pci_preinit failed "
"to set_irq_type pin %d\n", pin);

4
arch/arm/mach-orion5x/ts209-setup.c
View File

@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void)
pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
"set_irq_type pin %d\n", pin);
@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void)
pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed "
"to set_irq_type pin %d\n", pin);

10
arch/arm/mach-pnx4008/irq.c
View File

@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
case IRQ_TYPE_EDGE_RISING:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
set_irq_handler(d->irq, handle_edge_irq);
irq_set_handler(d->irq, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
set_irq_handler(d->irq, handle_edge_irq);
irq_set_handler(d->irq, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
set_irq_handler(d->irq, handle_level_irq);
irq_set_handler(d->irq, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
set_irq_handler(d->irq, handle_level_irq);
irq_set_handler(d->irq, handle_level_irq);
break;
/* IRQ_TYPE_EDGE_BOTH is not supported */
@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void)
/* configure IRQ's */
for (i = 0; i < NR_IRQS; i++) {
set_irq_flags(i, IRQF_VALID);
set_irq_chip(i, &pnx4008_irq_chip);
irq_set_chip(i, &pnx4008_irq_chip);
pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
}

8
arch/arm/mach-pxa/balloon3.c
View File

@ -527,13 +527,13 @@ static void __init balloon3_init_irq(void)
pxa27x_init_irq();
/* setup extra Balloon3 irqs */
for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
set_irq_chip(irq, &balloon3_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &balloon3_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
pr_debug("%s: chained handler installed - irq %d automatically "
"enabled\n", __func__, BALLOON3_AUX_NIRQ);

5
arch/arm/mach-pxa/cm-x2xx-pci.c
View File

@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio)
cmx2xx_it8152_irq_gpio = irq_gpio;
set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux);
irq_set_chained_handler(gpio_to_irq(irq_gpio),
cmx2xx_it8152_irq_demux);
}
#ifdef CONFIG_PM

2
arch/arm/mach-pxa/cm-x300.c
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@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void)
{
pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
i2c_register_board_info(1, &cm_x300_pmic_info, 1);
set_irq_wake(IRQ_WAKEUP0, 1);
irq_set_irq_wake(IRQ_WAKEUP0, 1);
}
static void __init cm_x300_init_wi2wi(void)

12
arch/arm/mach-pxa/irq.c
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@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
GEDR0 = 0x3;
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
set_irq_chip(irq, &pxa_low_gpio_chip);
set_irq_chip_data(irq, irq_base(0));
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &pxa_low_gpio_chip);
irq_set_chip_data(irq, irq_base(0));
irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID);
}
@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
irq = PXA_IRQ(i);
set_irq_chip(irq, &pxa_internal_irq_chip);
set_irq_chip_data(irq, base);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &pxa_internal_irq_chip);
irq_set_chip_data(irq, base);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}

8
arch/arm/mach-pxa/lpd270.c
View File

@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void)
/* setup extra LogicPD PXA270 irqs */
for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
set_irq_chip(irq, &lpd270_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &lpd270_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}

8
arch/arm/mach-pxa/lubbock.c
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@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void)
/* setup extra lubbock irqs */
for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
set_irq_chip(irq, &lubbock_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &lubbock_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM

8
arch/arm/mach-pxa/mainstone.c
View File

@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void)
/* setup extra Mainstone irqs */
for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
set_irq_chip(irq, &mainstone_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &mainstone_irq_chip);
irq_set_handler(irq, handle_level_irq);
if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
else
@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void)
MST_INTMSKENA = 0;
MST_INTSETCLR = 0;
set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM

8
arch/arm/mach-pxa/pcm990-baseboard.c
View File

@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void)
/* setup extra PCM990 irqs */
for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
set_irq_chip(irq, &pcm990_irq_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &pcm990_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
PCM990_INTSETCLR = 0xFF;
set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
}
static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,

4
arch/arm/mach-pxa/pxa3xx.c
View File

@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
int irq;
for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
set_irq_chip(irq, &pxa_ext_wakeup_chip);
set_irq_handler(irq, handle_edge_irq);
irq_set_chip(irq, &pxa_ext_wakeup_chip);
irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID);
}

8
arch/arm/mach-pxa/viper.c
View File

@ -310,14 +310,14 @@ static void __init viper_init_irq(void)
/* setup ISA IRQs */
for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
isa_irq = viper_bit_to_irq(level);
set_irq_chip(isa_irq, &viper_irq_chip);
set_irq_handler(isa_irq, handle_edge_irq);
irq_set_chip(isa_irq, &viper_irq_chip);
irq_set_handler(isa_irq, handle_edge_irq);
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
viper_irq_handler);
set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
}
/* Flat Panel */

19
arch/arm/mach-pxa/zeus.c
View File

@ -136,22 +136,23 @@ static void __init zeus_init_irq(void)
/* Peripheral IRQs. It would be nice to move those inside driver
configuration, but it is not supported at the moment. */
set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING);
set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
IRQ_TYPE_EDGE_FALLING);
irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
/* Setup ISA IRQs */
for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
isa_irq = zeus_bit_to_irq(level);
set_irq_chip(isa_irq, &zeus_irq_chip);
set_irq_handler(isa_irq, handle_edge_irq);
irq_set_chip(isa_irq, &zeus_irq_chip);
irq_set_handler(isa_irq, handle_edge_irq);
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
}

14
arch/arm/mach-rpc/irq.c
View File

@ -133,25 +133,25 @@ void __init rpc_init_irq(void)
switch (irq) {
case 0 ... 7:
set_irq_chip(irq, &iomd_a_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &iomd_a_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 8 ... 15:
set_irq_chip(irq, &iomd_b_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &iomd_b_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 16 ... 21:
set_irq_chip(irq, &iomd_dma_chip);
set_irq_handler(irq, handle_level_irq);
irq_set_chip(irq, &iomd_dma_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, flags);
break;
case 64 ... 71:
set_irq_chip(irq, &iomd_fiq_chip);
irq_set_chip(irq, &iomd_fiq_chip);
set_irq_flags(irq, IRQF_VALID);
break;
}

6
arch/arm/mach-s3c2410/bast-irq.c
View File

@ -147,15 +147,15 @@ static __init int bast_irq_init(void)
__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
/* register our IRQs */
for (i = 0; i < 4; i++) {
unsigned int irqno = bast_pc104_irqs[i];
set_irq_chip(irqno, &bast_pc104_chip);
set_irq_handler(irqno, handle_level_irq);
irq_set_chip(irqno, &bast_pc104_chip);
irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}

12
arch/arm/mach-s3c2412/irq.c
View File

@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
unsigned int irqno;
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
set_irq_chip(irqno, &s3c2412_irq_eint0t4);
set_irq_handler(irqno, handle_edge_irq);
irq_set_chip(irqno, &s3c2412_irq_eint0t4);
irq_set_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
/* add demux support for CF/SDI */
set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
set_irq_chip(irqno, &s3c2412_irq_cfsdi);
set_irq_handler(irqno, handle_level_irq);
irq_set_chip(irqno, &s3c2412_irq_cfsdi);
irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
s3c2412_irq_rtc_chip = s3c_irq_chip;
s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
return 0;
}

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