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clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*

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With the new clk parenting code and CLK_HW_INIT_* macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.

Convert existing CLK_HW_INIT_* definitions to describe parents using
either struct clk_hw pointers or clock-names from the device tree
binding.

For the AR100, this also allows us to merge the generic AR100 and the
A83T specific one, which only differed in the global clock names for
their parent clocks. The device tree bindings used the same name
specifiers.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Chen-Yu Tsai 2019-05-03 11:18:24 +08:00
parent 9309448335
commit 6873d20726
1 changed files with 25 additions and 40 deletions
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49
drivers/clk/sunxi-ng/ccu-sun8i-r.c
View File

@ -25,10 +25,13 @@
#include "ccu-sun8i-r.h"
static const char * const ar100_parents[] = { "osc32k", "osc24M",
"pll-periph0", "iosc" };
static const char * const a83t_ar100_parents[] = { "osc16M-d512", "osc24M",
"pll-periph0", "iosc" };
static const struct clk_parent_data ar100_parents[] = {
{ .fw_name = "losc" },
{ .fw_name = "hosc" },
{ .fw_name = "pll-periph" },
{ .fw_name = "iosc" },
};
static const struct ccu_mux_var_prediv ar100_predivs[] = {
{ .index = 2, .shift = 8, .width = 5 },
};
@ -47,34 +50,13 @@ static struct ccu_div ar100_clk = {
.common = {
.reg = 0x00,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ar100",
.hw.init = CLK_HW_INIT_PARENTS_DATA("ar100",
ar100_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div a83t_ar100_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 16,
.width = 2,
.var_predivs = ar100_predivs,
.n_var_predivs = ARRAY_SIZE(ar100_predivs),
},
.common = {
.reg = 0x00,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ar100",
a83t_ar100_parents,
&ccu_div_ops,
0),
},
};
static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
static struct ccu_div apb0_clk = {
@ -82,8 +64,8 @@ static struct ccu_div apb0_clk = {
.common = {
.reg = 0x0c,
.hw.init = CLK_HW_INIT("apb0",
"ahb0",
.hw.init = CLK_HW_INIT_HW("apb0",
&ahb0_clk.hw,
&ccu_div_ops,
0),
},
@ -115,7 +97,10 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
BIT(31), /* gate */
0);
static const char *const a83t_r_mod0_parents[] = { "osc16M", "osc24M" };
static const struct clk_parent_data a83t_r_mod0_parents[] = {
{ .fw_name = "iosc" },
{ .fw_name = "hosc" },
};
static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
{ .index = 0, .div = 16 },
};
@ -135,7 +120,7 @@ static struct ccu_mp a83t_ir_clk = {
.common = {
.reg = 0x54,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ir",
.hw.init = CLK_HW_INIT_PARENTS_DATA("ir",
a83t_r_mod0_parents,
&ccu_mp_ops,
0),
@ -143,7 +128,7 @@ static struct ccu_mp a83t_ir_clk = {
};
static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
&a83t_ar100_clk.common,
&ar100_clk.common,
&a83t_apb0_clk.common,
&apb0_pio_clk.common,
&apb0_ir_clk.common,
@ -182,7 +167,7 @@ static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
.hws = {
[CLK_AR100] = &a83t_ar100_clk.common.hw,
[CLK_AR100] = &ar100_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.hw,
[CLK_APB0] = &a83t_apb0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,