OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts
This patch adds additional register bitshifts for registers added in OMAP4460 platform. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> [tony@atomide.com: updated to apply on cleanup patches] Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -106,6 +106,10 @@
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#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
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#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
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#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
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#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
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/* Used by CM_L4CFG_CLKSTCTRL */
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#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
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#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
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/* Used by CM_CEFUSE_CLKSTCTRL */
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/* Used by CM_CEFUSE_CLKSTCTRL */
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#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
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#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
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#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
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#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
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@ -418,6 +422,10 @@
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#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
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#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
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#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
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#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
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#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
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/*
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/*
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* Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
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* Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
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* CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
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* CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
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@ -449,6 +457,10 @@
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#define OMAP4430_CLKSEL_60M_SHIFT 24
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#define OMAP4430_CLKSEL_60M_SHIFT 24
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#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
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#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
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/* Used by CM_MPU_MPU_CLKCTRL */
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#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
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#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
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/* Used by CM1_ABE_AESS_CLKCTRL */
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/* Used by CM1_ABE_AESS_CLKCTRL */
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#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
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#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
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#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
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#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
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@ -468,6 +480,10 @@
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#define OMAP4430_CLKSEL_DIV_SHIFT 24
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#define OMAP4430_CLKSEL_DIV_SHIFT 24
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#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
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#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
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/* Used by CM_MPU_MPU_CLKCTRL */
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#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
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#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
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/* Used by CM_CAM_FDIF_CLKCTRL */
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/* Used by CM_CAM_FDIF_CLKCTRL */
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#define OMAP4430_CLKSEL_FCLK_SHIFT 24
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#define OMAP4430_CLKSEL_FCLK_SHIFT 24
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#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
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#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
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@ -572,6 +588,14 @@
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#define OMAP4430_D2D_STATDEP_SHIFT 18
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#define OMAP4430_D2D_STATDEP_SHIFT 18
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#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
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#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
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/* Used by CM_CLKSEL_DPLL_MPU */
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#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
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#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
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/* Used by CM_CLKSEL_DPLL_MPU */
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#define OMAP4460_DCC_EN_SHIFT 22
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#define OMAP4460_DCC_EN_MASK (1 << 22)
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/*
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/*
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* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
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* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
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* CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
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* CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
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@ -582,6 +606,10 @@
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#define OMAP4430_DELTAMSTEP_SHIFT 0
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#define OMAP4430_DELTAMSTEP_SHIFT 0
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#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
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#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
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/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
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#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
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#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
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/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
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/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
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#define OMAP4430_DLL_OVERRIDE_SHIFT 2
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#define OMAP4430_DLL_OVERRIDE_SHIFT 2
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#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2)
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#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2)
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@ -1204,6 +1232,10 @@
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#define OMAP4430_MODULEMODE_SHIFT 0
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#define OMAP4430_MODULEMODE_SHIFT 0
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#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
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#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
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/* Used by CM_L4CFG_DYNAMICDEP */
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#define OMAP4460_MPU_DYNDEP_SHIFT 19
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#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
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/* Used by CM_DSS_DSS_CLKCTRL */
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/* Used by CM_DSS_DSS_CLKCTRL */
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#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
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#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
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#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
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#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
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@ -1298,6 +1330,10 @@
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#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
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#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
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#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
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#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
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/* Used by CM_WKUP_BANDGAP_CLKCTRL */
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#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
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#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
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/* Used by CM_DSS_DSS_CLKCTRL */
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/* Used by CM_DSS_DSS_CLKCTRL */
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#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
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#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
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#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
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#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
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@ -283,6 +283,14 @@
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#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
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#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
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#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
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#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
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/* Used by PRM_DEVICE_OFF_CTRL */
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#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8
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#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
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/* Used by PRM_DEVICE_OFF_CTRL */
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#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9
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#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
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/* Used by RM_MPU_RSTST */
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/* Used by RM_MPU_RSTST */
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#define OMAP4430_EMULATION_RST_SHIFT 0
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#define OMAP4430_EMULATION_RST_SHIFT 0
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#define OMAP4430_EMULATION_RST_MASK (1 << 0)
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#define OMAP4430_EMULATION_RST_MASK (1 << 0)
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