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pinctrl: sh-pfc: Updates for v5.3 

- Add more checks for pinctrl table validation,
   - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and
     M3-N,
   - Rework description of pins without GPIO functionality,
   - Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.3

  - Add more checks for pinctrl table validation,
  - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and
    M3-N,
  - Rework description of pins without GPIO functionality,
  - Small fixes and cleanups.
This commit is contained in:
Linus Walleij 2019-06-08 01:32:19 +02:00
parent 9d130f91a4 992968d786
commit 6bd1eb6c5d
23 changed files with 1245 additions and 1059 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
drivers/pinctrl/sh-pfc/core.c
View File

@ -717,7 +717,7 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
#ifdef DEBUG
static bool is0s(const u16 *enum_ids, unsigned int n)
static bool __init is0s(const u16 *enum_ids, unsigned int n)
{
unsigned int i;
@ -728,11 +728,11 @@ static bool is0s(const u16 *enum_ids, unsigned int n)
return true;
}
static unsigned int sh_pfc_errors;
static unsigned int sh_pfc_warnings;
static unsigned int sh_pfc_errors __initdata = 0;
static unsigned int sh_pfc_warnings __initdata = 0;
static void sh_pfc_check_cfg_reg(const char *drvname,
const struct pinmux_cfg_reg *cfg_reg)
static void __init sh_pfc_check_cfg_reg(const char *drvname,
const struct pinmux_cfg_reg *cfg_reg)
{
unsigned int i, n, rw, fw;
@ -764,7 +764,7 @@ static void sh_pfc_check_cfg_reg(const char *drvname,
}
}
static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
{
const struct sh_pfc_function *func;
const char *drvname = info->name;
@ -773,6 +773,35 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
pr_info("Checking %s\n", drvname);
/* Check pins */
for (i = 0; i < info->nr_pins; i++) {
for (j = 0; j < i; j++) {
if (!strcmp(info->pins[i].name, info->pins[j].name)) {
pr_err("%s: pin %s/%s: name conflict\n",
drvname, info->pins[i].name,
info->pins[j].name);
sh_pfc_errors++;
}
if (info->pins[i].pin != (u16)-1 &&
info->pins[i].pin == info->pins[j].pin) {
pr_err("%s: pin %s/%s: pin %u conflict\n",
drvname, info->pins[i].name,
info->pins[j].name, info->pins[i].pin);
sh_pfc_errors++;
}
if (info->pins[i].enum_id &&
info->pins[i].enum_id == info->pins[j].enum_id) {
pr_err("%s: pin %s/%s: enum_id %u conflict\n",
drvname, info->pins[i].name,
info->pins[j].name,
info->pins[i].enum_id);
sh_pfc_errors++;
}
}
}
/* Check groups and functions */
refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
if (!refcnts)
@ -780,9 +809,15 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
for (i = 0; i < info->nr_functions; i++) {
func = &info->functions[i];
if (!func->name) {
pr_err("%s: empty function %u\n", drvname, i);
sh_pfc_errors++;
continue;
}
for (j = 0; j < func->nr_groups; j++) {
for (k = 0; k < info->nr_groups; k++) {
if (!strcmp(func->groups[j],
if (info->groups[k].name &&
!strcmp(func->groups[j],
info->groups[k].name)) {
refcnts[k]++;
break;
@ -798,13 +833,18 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
}
for (i = 0; i < info->nr_groups; i++) {
if (!info->groups[i].name) {
pr_err("%s: empty group %u\n", drvname, i);
sh_pfc_errors++;
continue;
}
if (!refcnts[i]) {
pr_err("%s: orphan group %s\n", drvname,
info->groups[i].name);
sh_pfc_errors++;
} else if (refcnts[i] > 1) {
pr_err("%s: group %s referred by %u functions\n",
drvname, info->groups[i].name, refcnts[i]);
pr_warn("%s: group %s referenced by %u functions\n",
drvname, info->groups[i].name, refcnts[i]);
sh_pfc_warnings++;
}
}
@ -816,7 +856,7 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
}
static void sh_pfc_check_driver(const struct platform_driver *pdrv)
static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
{
unsigned int i;

70
drivers/pinctrl/sh-pfc/pfc-emev2.c
View File

@ -19,6 +19,20 @@
PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP(LCD3_B2, "B15", fn), \
PIN_NOGP(LCD3_B3, "C15", fn), \
PIN_NOGP(LCD3_B4, "D15", fn), \
PIN_NOGP(LCD3_B5, "B14", fn), \
PIN_NOGP(LCD3_B6, "C14", fn), \
PIN_NOGP(LCD3_B7, "D14", fn), \
PIN_NOGP(LCD3_G2, "B17", fn), \
PIN_NOGP(LCD3_G3, "C17", fn), \
PIN_NOGP(LCD3_G4, "D17", fn), \
PIN_NOGP(LCD3_G5, "B16", fn), \
PIN_NOGP(LCD3_G6, "C16", fn), \
PIN_NOGP(LCD3_G7, "D16", fn)
enum {
PINMUX_RESERVED = 0,
@ -218,10 +232,13 @@ enum {
PINMUX_MARK_END,
};
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers. */
#define PIN_NUMBER(row, col) (1000+((row)-1)*23+(col)-1)
/*
* Pins not associated with a GPIO port.
*/
enum {
PORT_ASSIGN_LAST(),
NOGP_ALL(),
};
/* Expand to a list of sh_pfc_pin entries (named PORT#).
* NOTE: No config are recorded since the driver do not handle pinconf. */
@ -230,20 +247,7 @@ enum {
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_EMEV_GPIO_ALL(),
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(2, 14, B14),
SH_PFC_PIN_NAMED(2, 15, B15),
SH_PFC_PIN_NAMED(2, 16, B16),
SH_PFC_PIN_NAMED(2, 17, B17),
SH_PFC_PIN_NAMED(3, 14, C14),
SH_PFC_PIN_NAMED(3, 15, C15),
SH_PFC_PIN_NAMED(3, 16, C16),
SH_PFC_PIN_NAMED(3, 17, C17),
SH_PFC_PIN_NAMED(4, 14, D14),
SH_PFC_PIN_NAMED(4, 15, D15),
SH_PFC_PIN_NAMED(4, 16, D16),
SH_PFC_PIN_NAMED(4, 17, D17),
PINMUX_NOGP_ALL(),
};
/* Expand to a list of name_DATA, name_FN marks */
@ -829,12 +833,10 @@ static const unsigned int lcd3_rgb888_pins[] = {
/* R[0:7], G[0:7], B[0:7] */
32, 33, 34, 35,
36, 37, 38, 39,
40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
PIN_NUMBER(4, 16),
42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
PIN_NUMBER(4, 14)
40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7
};
static const unsigned int lcd3_rgb888_mux[] = {
LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
@ -850,12 +852,10 @@ static const unsigned int yuv3_pins[] = {
/* CLK_O, HS, VS, DE */
18, 21, 22, 23,
/* YUV3_D[0:15] */
40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
PIN_NUMBER(4, 16),
42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
PIN_NUMBER(4, 14),
40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
};
static const unsigned int yuv3_mux[] = {
YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
@ -972,12 +972,10 @@ static const unsigned int tp33_pins[] = {
/* CLK, CTRL */
38, 39,
/* TP33_DATA[0:15] */
40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
PIN_NUMBER(4, 16),
42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
PIN_NUMBER(4, 14),
40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
};
static const unsigned int tp33_mux[] = {
TP33_CLK_MARK, TP33_CTRL_MARK,

2
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View File

@ -1252,7 +1252,7 @@ static const u16 pinmux_data[] = {
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)

2
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -1515,7 +1515,7 @@ static const u16 pinmux_data[] = {
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)

2
drivers/pinctrl/sh-pfc/pfc-r8a77470.c
View File

@ -10,7 +10,7 @@
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_4(0, fn, sfx), \
PORT_GP_1(0, 4, fn, sfx), \
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \

125
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View File

@ -22,28 +22,17 @@
#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define PORT_GP_PUP_27(bank, fn, sfx) \
PORT_GP_PUP_1(bank, 0, fn, sfx), PORT_GP_PUP_1(bank, 1, fn, sfx), \
PORT_GP_PUP_1(bank, 2, fn, sfx), PORT_GP_PUP_1(bank, 3, fn, sfx), \
PORT_GP_PUP_1(bank, 4, fn, sfx), PORT_GP_PUP_1(bank, 5, fn, sfx), \
PORT_GP_PUP_1(bank, 6, fn, sfx), PORT_GP_PUP_1(bank, 7, fn, sfx), \
PORT_GP_PUP_1(bank, 8, fn, sfx), PORT_GP_PUP_1(bank, 9, fn, sfx), \
PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx), \
PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx), \
PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx), \
PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx), \
PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx), \
PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx), \
PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx), \
PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx), \
PORT_GP_PUP_1(bank, 26, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_PUP_27(4, fn, sfx)
PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP(CLKOUT, "B25", fn), \
PIN_NOGP(CS0, "A20", fn), \
PIN_NOGP(CS1_A26, "C20", fn)
enum {
PINMUX_RESERVED = 0,
@ -1253,19 +1242,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
};
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
/*
* Pins not associated with a GPIO port.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(3, 20, C20),
SH_PFC_PIN_NAMED(1, 20, A20),
SH_PFC_PIN_NAMED(2, 25, B25),
PINMUX_NOGP_ALL(),
};
/* - macro */
@ -1400,7 +1387,7 @@ HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A,
HSPI_RX1_A, HSPI_TX1_A);
HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26),
PIN_NUMBER(1, 20), PIN_NUMBER(2, 25));
PIN_CS0, PIN_CLKOUT);
HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B,
HSPI_RX1_B, HSPI_TX1_B);
@ -1426,7 +1413,7 @@ I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B);
/* - I2C2 ------------------------------------------------------------------ */
I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
I2C_PFC_PIN(i2c2_a, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A);
I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B);
@ -1516,7 +1503,7 @@ SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E);
SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9));
SCIF_PFC_CLK(scif2_clk_a, SCK2_A);
SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20));
SCIF_PFC_PIN(scif2_clk_b, PIN_CS1_A26);
SCIF_PFC_CLK(scif2_clk_b, SCK2_B);
SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12));
SCIF_PFC_CLK(scif2_clk_c, SCK2_C);
@ -1631,7 +1618,7 @@ SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10));
SSI_PFC_DATA(ssi0_data, SSI_SDATA0);
SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21));
SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A);
SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
SSI_PFC_PINS(ssi1_b_ctrl, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B);
SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9));
SSI_PFC_DATA(ssi1_data, SSI_SDATA1);
@ -2921,8 +2908,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
#define PIN_NONE U16_MAX
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 6), /* A0 */
@ -2969,28 +2954,28 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */
[ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */
[ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
@ -3112,21 +3097,21 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */
[15] = RCAR_GP_PIN(4, 25), /* AVS1 */
[16] = RCAR_GP_PIN(4, 26), /* AVS2 */
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};

2
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View File

@ -11,7 +11,7 @@
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \

36
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

@ -20,7 +20,7 @@
* All pins assigned to GPIO bank 3 can be used for SD interfaces in
* which case they support both 3.3V and 1.8V signalling.
*/
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_30(1, fn, sfx), \
PORT_GP_30(2, fn, sfx), \
@ -28,6 +28,12 @@
PORT_GP_32(4, fn, sfx), \
PORT_GP_32(5, fn, sfx)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP(IIC0_SDA, "AF15", fn), \
PIN_NOGP(IIC0_SCL, "AG15", fn), \
PIN_NOGP(IIC3_SDA, "AH15", fn), \
PIN_NOGP(IIC3_SCL, "AJ15", fn)
enum {
PINMUX_RESERVED = 0,
@ -1727,19 +1733,17 @@ static const u16 pinmux_data[] = {
PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
};
/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
@ -2135,7 +2139,7 @@ static const unsigned int hscif1_ctrl_b_mux[] = {
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
PIN_IIC0_SCL, PIN_IIC0_SDA,
};
static const unsigned int i2c0_mux[] = {
I2C0_SCL_MARK, I2C0_SDA_MARK,
@ -2201,7 +2205,7 @@ static const unsigned int i2c2_e_mux[] = {
/* - I2C3 ------------------------------------------------------------------- */
static const unsigned int i2c3_pins[] = {
/* SCL, SDA */
PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
PIN_IIC3_SCL, PIN_IIC3_SDA,
};
static const unsigned int i2c3_mux[] = {
I2C3_SCL_MARK, I2C3_SDA_MARK,
@ -2209,7 +2213,7 @@ static const unsigned int i2c3_mux[] = {
/* - IIC0 (I2C4) ------------------------------------------------------------ */
static const unsigned int iic0_pins[] = {
/* SCL, SDA */
PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
PIN_IIC0_SCL, PIN_IIC0_SDA,
};
static const unsigned int iic0_mux[] = {
IIC0_SCL_MARK, IIC0_SDA_MARK,
@ -2274,8 +2278,8 @@ static const unsigned int iic2_e_mux[] = {
};
/* - IIC3 (I2C7) ------------------------------------------------------------ */
static const unsigned int iic3_pins[] = {
/* SCL, SDA */
PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
/* SCL, SDA */
PIN_IIC3_SCL, PIN_IIC3_SDA,
};
static const unsigned int iic3_mux[] = {
IIC3_SCL_MARK, IIC3_SDA_MARK,

2
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
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@ -15,7 +15,7 @@
* Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
* which case they support both 3.3V and 1.8V signalling.
*/
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \

2
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
View File

@ -11,7 +11,7 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_29(0, fn, sfx), \
PORT_GP_23(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \

2
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
View File

@ -14,7 +14,7 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \

434
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
View File

@ -11,11 +11,9 @@
#include "core.h"
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@ -28,6 +26,53 @@
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@ -1447,69 +1492,16 @@ static const u16 pinmux_data[] = {
};
/*
* R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
* Physical layout rows: A - AW, cols: 1 - 39.
* Pins not associated with a GPIO port.
*/
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
#define PIN_NONE U16_MAX
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/*
* Pins not associated with a GPIO port.
*
* The pin positions are different between different r8a7795
* packages, all that is needed for the pfc driver is a unique
* number for each pin. To this end use the pin layout from
* R-Car H3SiP to calculate a unique number for each pin.
*/
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
@ -1658,7 +1650,7 @@ static const unsigned int avb_phy_int_mux[] = {
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
@ -1671,11 +1663,11 @@ static const unsigned int avb_mii_pins[] = {
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
PIN_NUMBER('A', 12),
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
};
static const unsigned int avb_mii_mux[] = {
@ -3137,22 +3129,21 @@ static const unsigned int pwm6_b_mux[] = {
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* QSPI0_SPCLK, QSPI0_SSL */
PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3),
PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4),
PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6),
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
@ -3161,22 +3152,21 @@ static const unsigned int qspi0_data4_mux[] = {
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* QSPI1_SPCLK, QSPI1_SSL */
PIN_NUMBER('V', 3), PIN_NUMBER('V', 5),
PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5),
PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3),
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
@ -3812,6 +3802,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@ -4165,6 +4185,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@ -4635,6 +4659,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk2_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to1",
"tpu_to2",
"tpu_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -4707,6 +4738,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
@ -5272,44 +5304,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@ -5352,7 +5384,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
{ PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
{ PIN_CLKOUT, 28, 3 }, /* CLKOUT */
{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
@ -5363,7 +5395,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@ -5382,30 +5414,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@ -5474,7 +5506,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@ -5548,35 +5580,35 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@ -5616,7 +5648,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[31] = RCAR_GP_PIN(1, 19), /* A19 */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
[ 0] = PIN_CLKOUT, /* CLKOUT */
[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
@ -5625,7 +5657,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
@ -5646,20 +5678,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
[ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
[ 8] = PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
[ 2] = PIN_FSCLKST_N, /* FSCLKST# */
[ 3] = PIN_EXTALR, /* EXTALR*/
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@ -5724,7 +5756,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
[ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@ -5759,31 +5791,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
[ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
[ 7] = PIN_NONE,
[ 8] = PIN_NONE,
[ 9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};

414
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View File

@ -12,11 +12,9 @@
#include "core.h"
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@ -29,6 +27,52 @@
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@ -1508,68 +1552,16 @@ static const u16 pinmux_data[] = {
};
/*
* R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
* Physical layout rows: A - AW, cols: 1 - 39.
* Pins not associated with a GPIO port.
*/
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
#define PIN_NONE U16_MAX
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/*
* Pins not associated with a GPIO port.
*
* The pin positions are different between different r8a7795
* packages, all that is needed for the pfc driver is a unique
* number for each pin. To this end use the pin layout from
* R-Car H3SiP to calculate a unique number for each pin.
*/
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
@ -1717,7 +1709,7 @@ static const unsigned int avb_phy_int_mux[] = {
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
@ -1730,11 +1722,11 @@ static const unsigned int avb_mii_pins[] = {
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
PIN_NUMBER('A', 12),
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
};
static const unsigned int avb_mii_mux[] = {
@ -3901,6 +3893,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@ -4451,6 +4473,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@ -4946,6 +4972,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk2_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to1",
"tpu_to2",
"tpu_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -5048,6 +5081,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
@ -5623,44 +5657,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@ -5714,7 +5748,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@ -5733,30 +5767,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
{ PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@ -5825,7 +5859,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@ -5898,35 +5932,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@ -5975,7 +6009,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
@ -5996,20 +6030,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
[ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
[ 8] = PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
[ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
[ 2] = PIN_FSCLKST_N, /* FSCLKST# */
[ 3] = PIN_EXTALR, /* EXTALR*/
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@ -6074,7 +6108,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
[ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@ -6109,31 +6143,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
[ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
[ 7] = PIN_NONE,
[ 8] = PIN_NONE,
[ 9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};

414
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View File

@ -17,11 +17,9 @@
#include "core.h"
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@ -34,6 +32,51 @@
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@ -1512,67 +1555,16 @@ static const u16 pinmux_data[] = {
};
/*
* R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
* Physical layout rows: A - AW, cols: 1 - 39.
* Pins not associated with a GPIO port.
*/
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
#define PIN_NONE U16_MAX
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/*
* Pins not associated with a GPIO port.
*
* The pin positions are different between different r8a7796
* packages, all that is needed for the pfc driver is a unique
* number for each pin. To this end use the pin layout from
* R-Car M3SiP to calculate a unique number for each pin.
*/
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
@ -1721,7 +1713,7 @@ static const unsigned int avb_phy_int_mux[] = {
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
@ -1734,11 +1726,11 @@ static const unsigned int avb_mii_pins[] = {
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
PIN_NUMBER('A', 12),
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
};
static const unsigned int avb_mii_mux[] = {
@ -3891,6 +3883,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@ -4110,7 +4132,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[312];
struct sh_pfc_pin_group common[316];
struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
@ -4397,6 +4419,10 @@ static const struct {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
@ -4918,6 +4944,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk2_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to1",
"tpu_to2",
"tpu_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -4963,7 +4996,7 @@ static const char * const vin5_groups[] = {
};
static const struct {
struct sh_pfc_function common[49];
struct sh_pfc_function common[50];
struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
@ -5011,6 +5044,7 @@ static const struct {
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
@ -5590,44 +5624,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@ -5681,7 +5715,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@ -5700,29 +5734,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
{ PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@ -5791,7 +5825,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@ -5864,35 +5898,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@ -5941,7 +5975,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
@ -5962,20 +5996,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
[ 1] = PIN_NONE,
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
[ 8] = PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
[ 1] = SH_PFC_PIN_NONE,
[ 2] = PIN_FSCLKST, /* FSCLKST */
[ 3] = PIN_EXTALR, /* EXTALR*/
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@ -6040,7 +6074,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
[ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@ -6075,31 +6109,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
[ 7] = PIN_NONE,
[ 8] = PIN_NONE,
[ 9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};

410
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
View File

@ -18,11 +18,9 @@
#include "core.h"
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
@ -35,6 +33,51 @@
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@ -1517,67 +1560,16 @@ static const u16 pinmux_data[] = {
};
/*
* R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
* Physical layout rows: A - AW, cols: 1 - 39.
* Pins not associated with a GPIO port.
*/
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
#define PIN_NONE U16_MAX
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/*
* Pins not associated with a GPIO port.
*
* The pin positions are different between different r8a77965
* packages, all that is needed for the pfc driver is a unique
* number for each pin. To this end use the pin layout from
* R-Car M3SiP to calculate a unique number for each pin.
*/
SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
@ -1726,7 +1718,7 @@ static const unsigned int avb_phy_int_mux[] = {
};
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
};
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
@ -1739,11 +1731,11 @@ static const unsigned int avb_mii_pins[] = {
* AVB_RD1, AVB_RD2, AVB_RD3,
* AVB_TXCREFCLK
*/
PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
PIN_NUMBER('A', 12),
PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
PIN_AVB_TXCREFCLK,
};
static const unsigned int avb_mii_mux[] = {
@ -4116,6 +4108,36 @@ static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - TPU ------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
/* TPU0TO0 */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tpu_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
/* TPU0TO1 */
RCAR_GP_PIN(6, 29),
};
static const unsigned int tpu_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
/* TPU0TO2 */
RCAR_GP_PIN(6, 30),
};
static const unsigned int tpu_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
/* TPU0TO3 */
RCAR_GP_PIN(6, 31),
};
static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@ -4672,6 +4694,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
@ -5164,6 +5190,13 @@ static const char * const tmu_groups[] = {
"tmu_tclk2_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to1",
"tpu_to2",
"tpu_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -5258,6 +5291,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
@ -5830,44 +5864,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
{ PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
{ PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
{ PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
{ PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
{ PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
{ PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
{ PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
{ PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
{ PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
{ PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
{ PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
{ PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
{ PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
{ PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
{ PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
{ PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
{ PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
{ PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
{ PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
{ PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
{ PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
{ PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
{ PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
{ PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
{ PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
{ PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
{ PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
{ PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
{ PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
} },
{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
{ PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
{ PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
{ PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
{ PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
{ PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
{ PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
{ PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
{ PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
{ PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
{ PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
{ PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
{ PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
{ PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
{ PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
{ PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
{ PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
{ PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
{ PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
{ PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
{ PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
{ PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
{ PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
{ PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
{ PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
{ PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
{ RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
{ RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
{ RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
} },
{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
{ RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
@ -5921,7 +5955,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
} },
{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
{ RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
{ PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
{ PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
{ RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
{ RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
{ RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
@ -5940,29 +5974,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
{ RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
{ PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
{ PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
{ PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
{ PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */
{ PIN_FSCLKST, 20, 2 }, /* FSCLKST */
{ PIN_TMS, 4, 2 }, /* TMS */
} },
{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
{ PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
{ PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
{ PIN_TDO, 28, 2 }, /* TDO */
{ PIN_ASEBRK, 24, 2 }, /* ASEBRK */
{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
@ -6031,7 +6065,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
{ RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
{ RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
{ PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
{ PIN_MLB_REF, 4, 3 }, /* MLB_REF */
{ RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
@ -6104,35 +6138,35 @@ static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
[ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
[ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
[ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
[ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
[ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
[ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
[ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
[ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
[ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
[10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
[11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
[12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
[13] = PIN_NUMBER('V', 6), /* RPC_WP# */
[14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
[15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
[16] = PIN_NUMBER('B', 19), /* AVB_RXC */
[17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
[18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
[19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
[20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
[21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
[22] = PIN_NUMBER('A', 19), /* AVB_TXC */
[23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
[24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
[25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
[26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
[27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
[28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
[ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
[ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
[ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
[ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
[ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
[ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
[ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
[ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
[ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
[ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
[10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
[11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
[12] = PIN_RPC_INT_N, /* RPC_INT# */
[13] = PIN_RPC_WP_N, /* RPC_WP# */
[14] = PIN_RPC_RESET_N, /* RPC_RESET# */
[15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
[16] = PIN_AVB_RXC, /* AVB_RXC */
[17] = PIN_AVB_RD0, /* AVB_RD0 */
[18] = PIN_AVB_RD1, /* AVB_RD1 */
[19] = PIN_AVB_RD2, /* AVB_RD2 */
[20] = PIN_AVB_RD3, /* AVB_RD3 */
[21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[22] = PIN_AVB_TXC, /* AVB_TXC */
[23] = PIN_AVB_TD0, /* AVB_TD0 */
[24] = PIN_AVB_TD1, /* AVB_TD1 */
[25] = PIN_AVB_TD2, /* AVB_TD2 */
[26] = PIN_AVB_TD3, /* AVB_TD3 */
[27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
[28] = PIN_AVB_MDIO, /* AVB_MDIO */
[29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
[30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
[31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
@ -6181,7 +6215,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
[ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
[ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
[ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
[ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
[10] = RCAR_GP_PIN(0, 0), /* D0 */
[11] = RCAR_GP_PIN(0, 1), /* D1 */
[12] = RCAR_GP_PIN(0, 2), /* D2 */
@ -6202,20 +6236,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
[30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
[31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
[ 1] = PIN_NONE,
[ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
[ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
[ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
[ 5] = PIN_A_NUMBER('T', 27), /* TCK */
[ 6] = PIN_A_NUMBER('R', 30), /* TMS */
[ 7] = PIN_A_NUMBER('R', 29), /* TDI */
[ 8] = PIN_NONE,
[ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
[ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
[ 1] = SH_PFC_PIN_NONE,
[ 2] = PIN_FSCLKST, /* FSCLKST */
[ 3] = PIN_EXTALR, /* EXTALR*/
[ 4] = PIN_TRST_N, /* TRST# */
[ 5] = PIN_TCK, /* TCK */
[ 6] = PIN_TMS, /* TMS */
[ 7] = PIN_TDI, /* TDI */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = PIN_ASEBRK, /* ASEBRK */
[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
@ -6280,7 +6314,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
[ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
[ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
[ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
[ 6] = PIN_MLB_REF, /* MLB_REF */
[ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
@ -6315,31 +6349,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
[ 7] = PIN_NONE,
[ 8] = PIN_NONE,
[ 9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[30] = PIN_NONE,
[31] = PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};

26
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
View File

@ -19,7 +19,7 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_28(1, fn, sfx), \
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
@ -205,8 +205,8 @@
#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -631,14 +631,12 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
PINMUX_IPSR_GPSR(IP6_31_28, D14),
PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
/* IPSR7 */
PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
PINMUX_IPSR_GPSR(IP7_3_0, D15),
PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
@ -1121,20 +1119,6 @@ static const unsigned int mmc_ctrl_pins[] = {
static const unsigned int mmc_ctrl_mux[] = {
MMC_CLK_MARK, MMC_CMD_MARK,
};
static const unsigned int mmc_cd_pins[] = {
/* CD */
RCAR_GP_PIN(3, 16),
};
static const unsigned int mmc_cd_mux[] = {
MMC_CD_MARK,
};
static const unsigned int mmc_wp_pins[] = {
/* WP */
RCAR_GP_PIN(3, 15),
};
static const unsigned int mmc_wp_mux[] = {
MMC_WP_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
@ -1726,8 +1710,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(mmc_cd),
SH_PFC_PIN_GROUP(mmc_wp),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
@ -1897,8 +1879,6 @@ static const char * const mmc_groups[] = {
"mmc_data4",
"mmc_data8",
"mmc_ctrl",
"mmc_cd",
"mmc_wp",
};
static const char * const msiof0_groups[] = {

2
drivers/pinctrl/sh-pfc/pfc-r8a77980.c
View File

@ -19,7 +19,7 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_28(1, fn, sfx), \
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \

181
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
View File

@ -17,10 +17,9 @@
#include "core.h"
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
@ -41,6 +40,25 @@
PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
@ -1277,41 +1295,16 @@ static const u16 pinmux_data[] = {
};
/*
* R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
* Physical layout rows: A - AE, cols: 1 - 25.
* Pins not associated with a GPIO port.
*/
#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
#define PIN_NONE U16_MAX
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/*
* Pins not associated with a GPIO port.
*
* The pin positions are different between different R8A77990
* packages, all that is needed for the pfc driver is a unique
* number for each pin. To this end use the pin layout from
* R8A77990 to calculate a unique number for each pin.
*/
SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------ */
@ -5026,15 +5019,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[0] = RCAR_GP_PIN(2, 23), /* RD# */
[1] = RCAR_GP_PIN(2, 22), /* BS# */
[2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
[3] = PIN_NUMBER('P', 5), /* AVB_MDC */
[4] = PIN_NUMBER('P', 4), /* AVB_MDIO */
[3] = PIN_AVB_MDC, /* AVB_MDC */
[4] = PIN_AVB_MDIO, /* AVB_MDIO */
[5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
[6] = PIN_NUMBER('N', 6), /* AVB_TD3 */
[7] = PIN_NUMBER('N', 5), /* AVB_TD2 */
[8] = PIN_NUMBER('N', 3), /* AVB_TD1 */
[9] = PIN_NUMBER('N', 2), /* AVB_TD0 */
[10] = PIN_NUMBER('N', 1), /* AVB_TXC */
[11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */
[6] = PIN_AVB_TD3, /* AVB_TD3 */
[7] = PIN_AVB_TD2, /* AVB_TD2 */
[8] = PIN_AVB_TD1, /* AVB_TD1 */
[9] = PIN_AVB_TD0, /* AVB_TD0 */
[10] = PIN_AVB_TXC, /* AVB_TXC */
[11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
[12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
[13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
[14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
@ -5085,33 +5078,33 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(1, 2), /* A2 */
[26] = RCAR_GP_PIN(1, 1), /* A1 */
[27] = RCAR_GP_PIN(1, 0), /* A0 */
[28] = PIN_NONE,
[29] = PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
[31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
} },
{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
[0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
[1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
[2] = PIN_NUMBER('H', 1), /* ASEBRK */
[3] = PIN_NONE,
[4] = PIN_NUMBER('G', 2), /* TDI */
[5] = PIN_NUMBER('F', 3), /* TMS */
[6] = PIN_NUMBER('F', 4), /* TCK */
[7] = PIN_NUMBER('F', 1), /* TRST# */
[8] = PIN_NONE,
[9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NUMBER('G', 3), /* FSCLKST# */
[2] = PIN_ASEBRK, /* ASEBRK */
[3] = SH_PFC_PIN_NONE,
[4] = PIN_TDI, /* TDI */
[5] = PIN_TMS, /* TMS */
[6] = PIN_TCK, /* TCK */
[7] = PIN_TRST_N, /* TRST# */
[8] = SH_PFC_PIN_NONE,
[9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = PIN_FSCLKST_N, /* FSCLKST# */
[16] = RCAR_GP_PIN(0, 17), /* SDA4 */
[17] = RCAR_GP_PIN(0, 16), /* SCL4 */
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
[21] = RCAR_GP_PIN(0, 15), /* D15 */
[22] = RCAR_GP_PIN(0, 14), /* D14 */
[23] = RCAR_GP_PIN(0, 13), /* D13 */
@ -5130,8 +5123,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */
[5] = PIN_NONE,
[6] = PIN_NONE,
[5] = SH_PFC_PIN_NONE,
[6] = SH_PFC_PIN_NONE,
[7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
[8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
[9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
@ -5175,7 +5168,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
[14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
[15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
[16] = PIN_NUMBER('T', 21), /* MLB_REF */
[16] = PIN_MLB_REF, /* MLB_REF */
[17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
[18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
[19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
@ -5193,36 +5186,36 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[31] = RCAR_GP_PIN(5, 5), /* RX1 */
} },
{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
[0] = PIN_NONE,
[1] = PIN_NONE,
[2] = PIN_NONE,
[3] = PIN_NONE,
[4] = PIN_NONE,
[5] = PIN_NONE,
[6] = PIN_NONE,
[7] = PIN_NONE,
[8] = PIN_NONE,
[9] = PIN_NONE,
[10] = PIN_NONE,
[11] = PIN_NONE,
[12] = PIN_NONE,
[13] = PIN_NONE,
[14] = PIN_NONE,
[15] = PIN_NONE,
[16] = PIN_NONE,
[17] = PIN_NONE,
[18] = PIN_NONE,
[19] = PIN_NONE,
[20] = PIN_NONE,
[21] = PIN_NONE,
[22] = PIN_NONE,
[23] = PIN_NONE,
[24] = PIN_NONE,
[25] = PIN_NONE,
[26] = PIN_NONE,
[27] = PIN_NONE,
[28] = PIN_NONE,
[29] = PIN_NONE,
[0] = SH_PFC_PIN_NONE,
[1] = SH_PFC_PIN_NONE,
[2] = SH_PFC_PIN_NONE,
[3] = SH_PFC_PIN_NONE,
[4] = SH_PFC_PIN_NONE,
[5] = SH_PFC_PIN_NONE,
[6] = SH_PFC_PIN_NONE,
[7] = SH_PFC_PIN_NONE,
[8] = SH_PFC_PIN_NONE,
[9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = SH_PFC_PIN_NONE,
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
[31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
} },

2
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
View File

@ -17,7 +17,7 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_9(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \

21
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@ -43,6 +43,9 @@
PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP(A11, "F26", fn)
enum {
PINMUX_RESERVED = 0,
@ -1147,7 +1150,7 @@ static const u16 pinmux_data[] = {
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
@ -1158,11 +1161,13 @@ static const u16 pinmux_data[] = {
#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
/*
* Pins not associated with a GPIO port.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
enum {
PORT_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
/* Table 25-1 (I/O and Pull U/D) */
@ -1437,7 +1442,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
SH73A0_PIN_O(309),
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(6, 26, F26),
PINMUX_NOGP_ALL(),
};
/* - BSC -------------------------------------------------------------------- */
@ -1863,7 +1868,7 @@ static const unsigned int keysc_out7_2_mux[] = {
};
static const unsigned int keysc_out8_0_pins[] = {
/* KEYOUT8 */
PIN_NUMBER(6, 26),
PIN_A11,
};
static const unsigned int keysc_out8_0_mux[] = {
KEYOUT8_MARK,
@ -3073,7 +3078,7 @@ static const unsigned int tpu4_to2_mux[] = {
};
static const unsigned int tpu4_to3_pins[] = {
/* TO */
PIN_NUMBER(6, 26),
PIN_A11,
};
static const unsigned int tpu4_to3_mux[] = {
TPU4TO3_MARK,

2
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View File

@ -11,7 +11,7 @@
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \

3
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -569,8 +569,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
return pin->configs &
(SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
case PIN_CONFIG_BIAS_PULL_UP:
return pin->configs & SH_PFC_PIN_CFG_PULL_UP;

90
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -21,10 +21,14 @@ enum {
PINMUX_TYPE_INPUT,
};
#define SH_PFC_PIN_NONE U16_MAX
#define SH_PFC_PIN_CFG_INPUT (1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
@ -542,9 +546,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
PORT_GP_CFG_27(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
@ -584,7 +592,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
@ -594,11 +602,29 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
.enum_id = _name##_DATA, \
.configs = cfg, \
}
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
/*
* GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
*
* The largest GP pin index is obtained by taking the size of a union,
* containing one array per GP pin, sized by the corresponding pin index.
* As the fields in the CPU_ALL_GP() macro definition are separated by commas,
* while the members of a union must be terminated by semicolons, the commas
* are absorbed by wrapping them inside dummy attributes.
*/
#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
#define GP_ASSIGN_LAST() \
GP_LAST = sizeof(union { \
char dummy[0] __attribute__((deprecated, \
CPU_ALL_GP(_GP_ENTRY, unused), \
deprecated)); \
})
/*
* PORT style (linear pin space)
@ -641,22 +667,6 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
.configs = cfgs, \
}
/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED(row, col, _name) \
{ \
.pin = PIN_NUMBER(row, col), \
.name = __stringify(PIN_##_name), \
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
}
/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
{ \
.pin = PIN_NUMBER(row, col), \
.name = __stringify(PIN_##_name), \
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
}
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
* PORT_name_OUT, PORT_name_IN marks
*/
@ -665,6 +675,24 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT##pfx##_OUT, PORT##pfx##_IN)
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
/*
* PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
*
* The largest PORT pin index is obtained by taking the size of a union,
* containing one array per PORT pin, sized by the corresponding pin index.
* As the fields in the CPU_ALL_PORT() macro definition are separated by
* commas, while the members of a union must be terminated by semicolons, the
* commas are absorbed by wrapping them inside dummy attributes.
*/
#define _PORT_ENTRY(pn, pfx, sfx) \
deprecated)); char pfx[pn] __attribute__((deprecated
#define PORT_ASSIGN_LAST() \
PORT_LAST = sizeof(union { \
char dummy[0] __attribute__((deprecated, \
CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
deprecated)); \
})
/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
[gpio - (base)] = { \
@ -674,6 +702,26 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
#define GPIO_FN(str) \
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
/*
* Pins not associated with a GPIO port
*/
#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
/* NOGP_ALL - Expand to a list of PIN_id */
#define _NOGP_ALL(pin, name, cfg) PIN_##pin
#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
#define _NOGP_PINMUX(_pin, _name, cfg) \
{ \
.pin = PIN_##_pin, \
.name = "PIN_" _name, \
.configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
}
#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
/*
* PORTnCR helper macro for SH-Mobile/R-Mobile
*/