Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next
Freescale updates from Scott: "Highlights include 8xx breakpoints and perf, t1042rdb display support, and board updates."
This commit is contained in:
Michael Ellerman
commit
6c8f9ad566
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|
@ -115,7 +115,7 @@ config PPC
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select HAVE_PERF_REGS
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select HAVE_PERF_USER_STACK_DUMP
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
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select HAVE_HW_BREAKPOINT if PERF_EVENTS && (PPC_BOOK3S || PPC_8xx)
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select ARCH_WANT_IPC_PARSE_VERSION
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select SPARSE_IRQ
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select IRQ_DOMAIN
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|
|
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|
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@ -0,0 +1,303 @@
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/*
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* Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
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*
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* (C) Copyright 2016
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* Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
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*
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* Copyright 2014 - 2015 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "t104xsi-pre.dtsi"
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/ {
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model = "keymile,kmcent2";
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compatible = "keymile,kmcent2";
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aliases {
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front_phy = &front_phy;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bman_fbpr: bman-fbpr {
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size = <0 0x1000000>;
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alignment = <0 0x1000000>;
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};
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qman_fqd: qman-fqd {
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size = <0 0x400000>;
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alignment = <0 0x400000>;
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};
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qman_pfdr: qman-pfdr {
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size = <0 0x2000000>;
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alignment = <0 0x2000000>;
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};
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};
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ifc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x2000>;
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ranges = <0 0 0xf 0xe8000000 0x04000000
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1 0 0xf 0xfa000000 0x00010000
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2 0 0xf 0xfb000000 0x00010000
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4 0 0xf 0xc0000000 0x08000000
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6 0 0xf 0xd0000000 0x08000000
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7 0 0xf 0xd8000000 0x08000000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x04000000>;
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bank-width = <2>;
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device-width = <2>;
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};
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|
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,ifc-nand";
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reg = <0x1 0x0 0x10000>;
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};
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board-control@2,0 {
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compatible = "keymile,qriox";
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reg = <0x2 0x0 0x80>;
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};
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|
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chassis-mgmt@6,0 {
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compatible = "keymile,bfticu";
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reg = <6 0 0x100>;
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interrupt-controller;
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interrupt-parent = <&mpic>;
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interrupts = <11 1 0 0>;
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#interrupt-cells = <1>;
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};
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|
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};
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memory {
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device_type = "memory";
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01072000>;
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};
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bportals: bman-portals@ff4000000 {
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ranges = <0x0 0xf 0xf4000000 0x2000000>;
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};
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qportals: qman-portals@ff6000000 {
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ranges = <0x0 0xf 0xf6000000 0x2000000>;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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spi@110000 {
|
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network-clock@1 {
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compatible = "zarlink,zl30364";
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reg = <1>;
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spi-max-frequency = <1000000>;
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};
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};
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|
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sdhc@114000 {
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status = "disabled";
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};
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i2c@118000 {
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clock-frequency = <100000>;
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mux@70 {
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compatible = "nxp,pca9547";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-mux-idle-disconnect;
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i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom@54 {
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compatible = "24c02";
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reg = <0x54>;
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pagesize = <2>;
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read-only;
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label = "ddr3-spd";
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};
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||||
};
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i2c@7 {
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reg = <7>;
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#address-cells = <1>;
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#size-cells = <0>;
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||||
|
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temp-sensor@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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label = "SENSOR_0";
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||||
};
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temp-sensor@4a {
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compatible = "national,lm75";
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||||
reg = <0x4a>;
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label = "SENSOR_2";
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};
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temp-sensor@4b {
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compatible = "national,lm75";
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reg = <0x4b>;
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label = "SENSOR_3";
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};
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};
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};
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};
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||||
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i2c@118100 {
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clock-frequency = <100000>;
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||||
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||||
eeprom@50 {
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||||
compatible = "atmel,24c08";
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||||
reg = <0x50>;
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||||
pagesize = <16>;
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||||
};
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||||
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||||
eeprom@54 {
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||||
compatible = "atmel,24c08";
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reg = <0x54>;
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||||
pagesize = <16>;
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||||
};
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};
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||||
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||||
i2c@119000 {
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||||
status = "disabled";
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||||
};
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||||
|
||||
i2c@119100 {
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||||
status = "disabled";
|
||||
};
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||||
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||||
serial2: serial@11d500 {
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||||
status = "disabled";
|
||||
};
|
||||
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||||
serial3: serial@11d600 {
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||||
status = "disabled";
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||||
};
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||||
|
||||
usb0: usb@210000 {
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||||
status = "disabled";
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||||
};
|
||||
usb1: usb@211000 {
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||||
status = "disabled";
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||||
};
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||||
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||||
display@180000 {
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||||
status = "disabled";
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||||
};
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||||
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||||
sata@220000 {
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||||
status = "disabled";
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||||
};
|
||||
sata@221000 {
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||||
status = "disabled";
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||||
};
|
||||
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||||
fman@400000 {
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||||
ethernet@e0000 {
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fixed-link = <0 1 1000 0 0>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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fixed-link = <1 1 1000 0 0>;
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phy-connection-type = "sgmii";
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||||
};
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||||
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||||
ethernet@e4000 {
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||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
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||||
phy-handle = <&front_phy>;
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||||
phy-connection-type = "rgmii";
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||||
};
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||||
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||||
mdio0: mdio@fc000 {
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||||
front_phy: ethernet-phy@11 {
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||||
reg = <0x11>;
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||||
};
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||||
};
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||||
};
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||||
};
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||||
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||||
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pci0: pcie@ffe240000 {
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reg = <0xf 0xfe240000 0 0x10000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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||||
0x02000000 0 0xe0000000
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0 0x20000000
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||||
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||||
0x01000000 0 0x00000000
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||||
0x01000000 0 0x00000000
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||||
0 0x00010000>;
|
||||
};
|
||||
};
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||||
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||||
pci1: pcie@ffe250000 {
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||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci2: pcie@ffe260000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pci3: pcie@ffe270000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qe: qe@ffe140000 {
|
||||
ranges = <0x0 0xf 0xfe140000 0x40000>;
|
||||
reg = <0xf 0xfe140000 0 0x480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
si1: si@700 {
|
||||
compatible = "fsl,t1040-qe-si";
|
||||
reg = <0x700 0x80>;
|
||||
};
|
||||
|
||||
siram1: siram@1000 {
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||||
compatible = "fsl,t1040-qe-siram";
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||||
reg = <0x1000 0x800>;
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||||
};
|
||||
|
||||
ucc_hdlc: ucc@2000 {
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||||
device_type = "hdlc";
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||||
compatible = "fsl,ucc-hdlc";
|
||||
rx-clock-name = "clk9";
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||||
tx-clock-name = "clk9";
|
||||
fsl,tx-timeslot-mask = <0xfffffffe>;
|
||||
fsl,rx-timeslot-mask = <0xfffffffe>;
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||||
fsl,siram-entry-id = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "t1040si-post.dtsi"
|
||||
|
|
@ -83,6 +83,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdhc@114000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@119000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,220 +0,0 @@
|
|||
CONFIG_PPC_85xx=y
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||||
CONFIG_SMP=y
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CONFIG_NR_CPUS=8
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_CORENET_GENERIC=y
|
||||
CONFIG_MPIC_MSGR=y
|
||||
CONFIG_HIGHMEM=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=13
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_ADVANCED_OPTIONS=y
|
||||
CONFIG_LOWMEM_SIZE_BOOL=y
|
||||
CONFIG_LOWMEM_SIZE=0x20000000
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_XFRM_SUB_POLICY=y
|
||||
CONFIG_XFRM_STATISTICS=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_INET_AH=y
|
||||
CONFIG_INET_ESP=y
|
||||
CONFIG_INET_IPCOMP=y
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_TIPC=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_CBQ=y
|
||||
CONFIG_NET_SCH_HTB=y
|
||||
CONFIG_NET_SCH_HFSC=y
|
||||
CONFIG_NET_SCH_PRIO=y
|
||||
CONFIG_NET_SCH_MULTIQ=y
|
||||
CONFIG_NET_SCH_RED=y
|
||||
CONFIG_NET_SCH_SFQ=y
|
||||
CONFIG_NET_SCH_TEQL=y
|
||||
CONFIG_NET_SCH_TBF=y
|
||||
CONFIG_NET_SCH_GRED=y
|
||||
CONFIG_NET_CLS_BASIC=y
|
||||
CONFIG_NET_CLS_TCINDEX=y
|
||||
CONFIG_NET_CLS_U32=y
|
||||
CONFIG_CLS_U32_PERF=y
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_NET_CLS_FLOW=y
|
||||
CONFIG_NET_CLS_CGROUP=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_PHRAM=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ECC_BCH=y
|
||||
CONFIG_MTD_NAND_FSL_ELBC=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_GLUEBI=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=2
|
||||
CONFIG_BLK_DEV_RAM_SIZE=2048
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SYM53C8XX_2=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_3COM is not set
|
||||
# CONFIG_NET_VENDOR_ADAPTEC is not set
|
||||
# CONFIG_NET_VENDOR_ALTEON is not set
|
||||
# CONFIG_NET_VENDOR_AMD is not set
|
||||
# CONFIG_NET_VENDOR_ATHEROS is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_BROCADE is not set
|
||||
# CONFIG_NET_VENDOR_CHELSIO is not set
|
||||
# CONFIG_NET_VENDOR_CISCO is not set
|
||||
# CONFIG_NET_VENDOR_DEC is not set
|
||||
# CONFIG_NET_VENDOR_DLINK is not set
|
||||
# CONFIG_NET_VENDOR_EMULEX is not set
|
||||
# CONFIG_NET_VENDOR_EXAR is not set
|
||||
CONFIG_FSL_PQ_MDIO=y
|
||||
CONFIG_FSL_XGMAC_MDIO=y
|
||||
# CONFIG_NET_VENDOR_HP is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MELLANOX is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_MYRI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NVIDIA is not set
|
||||
# CONFIG_NET_VENDOR_OKI is not set
|
||||
# CONFIG_NET_PACKET_ENGINE is not set
|
||||
# CONFIG_NET_VENDOR_QLOGIC is not set
|
||||
# CONFIG_NET_VENDOR_REALTEK is not set
|
||||
# CONFIG_NET_VENDOR_RDC is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SILAN is not set
|
||||
# CONFIG_NET_VENDOR_SIS is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_SUN is not set
|
||||
# CONFIG_NET_VENDOR_TEHUTI is not set
|
||||
# CONFIG_NET_VENDOR_TI is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_NET_VENDOR_XILINX is not set
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_PPC_EPAPR_HV_BYTECHAN=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_FSL_SPI=y
|
||||
CONFIG_SPI_FSL_ESPI=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_EDAC=y
|
||||
CONFIG_EDAC_MM_EDAC=y
|
||||
CONFIG_EDAC_MPC85XX=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_DS3232=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_UIO=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_CLK_QORIQ=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_SHIRQ=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_SCHEDSTATS=y
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_UPROBE_EVENT=y
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DEV_FSL_CAAM=y
|
||||
|
|
@ -505,7 +505,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
|
|||
#define MTMSRD(r) mtmsrd r
|
||||
#define MTMSR_EERI(reg) mtmsrd reg,1
|
||||
#else
|
||||
#define FIX_SRR1(ra, rb)
|
||||
#ifndef CONFIG_40x
|
||||
#define RFI rfi
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -225,6 +225,7 @@ struct thread_struct {
|
|||
#ifdef CONFIG_PPC64
|
||||
unsigned long start_tb; /* Start purr when proc switched in */
|
||||
unsigned long accum_tb; /* Total accumulated purr for process */
|
||||
#endif
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
struct perf_event *ptrace_bps[HBP_NUM];
|
||||
/*
|
||||
|
|
@ -233,7 +234,6 @@ struct thread_struct {
|
|||
*/
|
||||
struct perf_event *last_hit_ubp;
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
#endif
|
||||
struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
|
||||
unsigned long trap_nr; /* last trap # on this thread */
|
||||
u8 load_fp;
|
||||
|
|
|
|||
|
|
@ -552,7 +552,9 @@
|
|||
#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
|
||||
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
|
||||
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
|
||||
#ifndef SPRN_ICTRL
|
||||
#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
|
||||
#endif
|
||||
#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
|
||||
#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
|
||||
#define ICTRL_EICP 0x00000100 /* enable icache par. check */
|
||||
|
|
|
|||
|
|
@ -28,6 +28,17 @@
|
|||
/* Special MSR manipulation registers */
|
||||
#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */
|
||||
#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
|
||||
#define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
|
||||
|
||||
/* Debug registers */
|
||||
#define SPRN_CMPA 144
|
||||
#define SPRN_COUNTA 150
|
||||
#define SPRN_CMPE 152
|
||||
#define SPRN_CMPF 153
|
||||
#define SPRN_LCTRL1 156
|
||||
#define SPRN_LCTRL2 157
|
||||
#define SPRN_ICTRL 158
|
||||
#define SPRN_BAR 159
|
||||
|
||||
/* Commands. Only the first few are available to the instruction cache.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -205,6 +205,9 @@ transfer_to_handler_cont:
|
|||
mflr r9
|
||||
lwz r11,0(r9) /* virtual address of handler */
|
||||
lwz r9,4(r9) /* where to go when done */
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
mtspr SPRN_NRI, r0
|
||||
#endif
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
lis r12,reenable_mmu@h
|
||||
ori r12,r12,reenable_mmu@l
|
||||
|
|
@ -292,7 +295,9 @@ stack_ovf:
|
|||
lis r9,StackOverflow@ha
|
||||
addi r9,r9,StackOverflow@l
|
||||
LOAD_MSR_KERNEL(r10,MSR_KERNEL)
|
||||
FIX_SRR1(r10,r12)
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
mtspr SPRN_NRI, r0
|
||||
#endif
|
||||
mtspr SPRN_SRR0,r9
|
||||
mtspr SPRN_SRR1,r10
|
||||
SYNC
|
||||
|
|
@ -417,9 +422,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
|
|||
mtlr r4
|
||||
mtcr r5
|
||||
lwz r7,_NIP(r1)
|
||||
FIX_SRR1(r8, r0)
|
||||
lwz r2,GPR2(r1)
|
||||
lwz r1,GPR1(r1)
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
mtspr SPRN_NRI, r0
|
||||
#endif
|
||||
mtspr SPRN_SRR0,r7
|
||||
mtspr SPRN_SRR1,r8
|
||||
SYNC
|
||||
|
|
@ -703,6 +710,9 @@ fast_exception_return:
|
|||
lwz r10,_LINK(r11)
|
||||
mtlr r10
|
||||
REST_GPR(10, r11)
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
mtspr SPRN_NRI, r0
|
||||
#endif
|
||||
mtspr SPRN_SRR1,r9
|
||||
mtspr SPRN_SRR0,r12
|
||||
REST_GPR(9, r11)
|
||||
|
|
@ -951,7 +961,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
|
|||
.globl exc_exit_restart
|
||||
exc_exit_restart:
|
||||
lwz r12,_NIP(r1)
|
||||
FIX_SRR1(r9,r10)
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
mtspr SPRN_NRI, r0
|
||||
#endif
|
||||
mtspr SPRN_SRR0,r12
|
||||
mtspr SPRN_SRR1,r9
|
||||
REST_4GPRS(9, r1)
|
||||
|
|
@ -1294,7 +1306,6 @@ _GLOBAL(enter_rtas)
|
|||
1: tophys(r9,r1)
|
||||
lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
|
||||
lwz r9,8(r9) /* original msr value */
|
||||
FIX_SRR1(r9,r0)
|
||||
addi r1,r1,INT_FRAME_SIZE
|
||||
li r0,0
|
||||
mtspr SPRN_SPRG_RTAS,r0
|
||||
|
|
|
|||
|
|
@ -869,7 +869,6 @@ __secondary_start:
|
|||
|
||||
/* enable MMU and jump to start_secondary */
|
||||
li r4,MSR_KERNEL
|
||||
FIX_SRR1(r4,r5)
|
||||
lis r3,start_secondary@h
|
||||
ori r3,r3,start_secondary@l
|
||||
mtspr SPRN_SRR0,r3
|
||||
|
|
@ -977,7 +976,6 @@ start_here:
|
|||
ori r4,r4,2f@l
|
||||
tophys(r4,r4)
|
||||
li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
|
||||
FIX_SRR1(r3,r5)
|
||||
mtspr SPRN_SRR0,r4
|
||||
mtspr SPRN_SRR1,r3
|
||||
SYNC
|
||||
|
|
@ -1001,7 +999,6 @@ start_here:
|
|||
|
||||
/* Now turn on the MMU for real! */
|
||||
li r4,MSR_KERNEL
|
||||
FIX_SRR1(r4,r5)
|
||||
lis r3,start_kernel@h
|
||||
ori r3,r3,start_kernel@l
|
||||
mtspr SPRN_SRR0,r3
|
||||
|
|
|
|||
|
|
@ -329,6 +329,12 @@ InstructionTLBMiss:
|
|||
mtspr SPRN_SPRG_SCRATCH2, r3
|
||||
#endif
|
||||
EXCEPTION_PROLOG_0
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
|
||||
lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
|
||||
addi r11, r11, 1
|
||||
stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
|
||||
#endif
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
* kernel page tables.
|
||||
|
|
@ -429,6 +435,12 @@ InstructionTLBMiss:
|
|||
DataStoreTLBMiss:
|
||||
mtspr SPRN_SPRG_SCRATCH2, r3
|
||||
EXCEPTION_PROLOG_0
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
|
||||
lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
|
||||
addi r11, r11, 1
|
||||
stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
|
||||
#endif
|
||||
mfcr r3
|
||||
|
||||
/* If we are faulting a kernel address, we have to use the
|
||||
|
|
@ -561,6 +573,7 @@ InstructionTLBError:
|
|||
andis. r10,r5,0x4000
|
||||
beq+ 1f
|
||||
tlbie r4
|
||||
itlbie:
|
||||
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
|
||||
1: EXC_XFER_LITE(0x400, handle_page_fault)
|
||||
|
||||
|
|
@ -585,6 +598,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
|
|||
andis. r10,r5,0x4000
|
||||
beq+ 1f
|
||||
tlbie r4
|
||||
dtlbie:
|
||||
1: li r10,RPN_PATTERN
|
||||
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
|
||||
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
|
||||
|
|
@ -602,8 +616,43 @@ DARFixed:/* Return from dcbx instruction bug workaround */
|
|||
* support of breakpoints and such. Someday I will get around to
|
||||
* using them.
|
||||
*/
|
||||
EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
|
||||
. = 0x1c00
|
||||
DataBreakpoint:
|
||||
EXCEPTION_PROLOG_0
|
||||
mfcr r10
|
||||
mfspr r11, SPRN_SRR0
|
||||
cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
|
||||
cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
|
||||
beq- cr0, 11f
|
||||
beq- cr7, 11f
|
||||
EXCEPTION_PROLOG_1
|
||||
EXCEPTION_PROLOG_2
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
mfspr r4,SPRN_BAR
|
||||
stw r4,_DAR(r11)
|
||||
mfspr r5,SPRN_DSISR
|
||||
EXC_XFER_EE(0x1c00, do_break)
|
||||
11:
|
||||
mtcr r10
|
||||
EXCEPTION_EPILOG_0
|
||||
rfi
|
||||
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
. = 0x1d00
|
||||
InstructionBreakpoint:
|
||||
EXCEPTION_PROLOG_0
|
||||
lis r10, (instruction_counter - PAGE_OFFSET)@ha
|
||||
lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
|
||||
addi r11, r11, -1
|
||||
stw r11, (instruction_counter - PAGE_OFFSET)@l(r10)
|
||||
lis r10, 0xffff
|
||||
ori r10, r10, 0x01
|
||||
mtspr SPRN_COUNTA, r10
|
||||
EXCEPTION_EPILOG_0
|
||||
rfi
|
||||
#else
|
||||
EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
|
||||
#endif
|
||||
EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
|
||||
EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
|
||||
|
||||
|
|
@ -977,6 +1026,14 @@ initial_mmu:
|
|||
lis r8, IDC_ENABLE@h
|
||||
mtspr SPRN_DC_CST, r8
|
||||
#endif
|
||||
/* Disable debug mode entry on breakpoints */
|
||||
mfspr r8, SPRN_DER
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
rlwinm r8, r8, 0, ~0xc
|
||||
#else
|
||||
rlwinm r8, r8, 0, ~0x8
|
||||
#endif
|
||||
mtspr SPRN_DER, r8
|
||||
blr
|
||||
|
||||
|
||||
|
|
@ -1010,3 +1067,16 @@ cpu6_errata_word:
|
|||
.space 16
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_8xx_PERF_EVENT
|
||||
.globl itlb_miss_counter
|
||||
itlb_miss_counter:
|
||||
.space 4
|
||||
|
||||
.globl dtlb_miss_counter
|
||||
dtlb_miss_counter:
|
||||
.space 4
|
||||
|
||||
.globl instruction_counter
|
||||
instruction_counter:
|
||||
.space 4
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -211,9 +211,11 @@ int hw_breakpoint_handler(struct die_args *args)
|
|||
int rc = NOTIFY_STOP;
|
||||
struct perf_event *bp;
|
||||
struct pt_regs *regs = args->regs;
|
||||
#ifndef CONFIG_PPC_8xx
|
||||
int stepped = 1;
|
||||
struct arch_hw_breakpoint *info;
|
||||
unsigned int instr;
|
||||
#endif
|
||||
struct arch_hw_breakpoint *info;
|
||||
unsigned long dar = regs->dar;
|
||||
|
||||
/* Disable breakpoints during exception handling */
|
||||
|
|
@ -257,6 +259,7 @@ int hw_breakpoint_handler(struct die_args *args)
|
|||
(dar - bp->attr.bp_addr < bp->attr.bp_len)))
|
||||
info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
|
||||
|
||||
#ifndef CONFIG_PPC_8xx
|
||||
/* Do not emulate user-space instructions, instead single-step them */
|
||||
if (user_mode(regs)) {
|
||||
current->thread.last_hit_ubp = bp;
|
||||
|
|
@ -280,6 +283,7 @@ int hw_breakpoint_handler(struct die_args *args)
|
|||
perf_event_disable_inatomic(bp);
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* As a policy, the callback is invoked in a 'trigger-after-execute'
|
||||
* fashion
|
||||
|
|
|
|||
|
|
@ -736,6 +736,28 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
|
|||
mtspr(SPRN_DABRX, dabrx);
|
||||
return 0;
|
||||
}
|
||||
#elif defined(CONFIG_PPC_8xx)
|
||||
static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
|
||||
{
|
||||
unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
|
||||
unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
|
||||
unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
|
||||
|
||||
if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
|
||||
lctrl1 |= 0xa0000;
|
||||
else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
|
||||
lctrl1 |= 0xf0000;
|
||||
else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
|
||||
lctrl2 = 0;
|
||||
|
||||
mtspr(SPRN_LCTRL2, 0);
|
||||
mtspr(SPRN_CMPE, addr);
|
||||
mtspr(SPRN_CMPF, addr + 4);
|
||||
mtspr(SPRN_LCTRL1, lctrl1);
|
||||
mtspr(SPRN_LCTRL2, lctrl2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* Performance event support - PPC 8xx
|
||||
*
|
||||
* Copyright 2016 Christophe Leroy, CS Systemes d'Information
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/hardirq.h>
|
||||
#include <asm/pmc.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/firmware.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
#define PERF_8xx_ID_CPU_CYCLES 1
|
||||
#define PERF_8xx_ID_HW_INSTRUCTIONS 2
|
||||
#define PERF_8xx_ID_ITLB_LOAD_MISS 3
|
||||
#define PERF_8xx_ID_DTLB_LOAD_MISS 4
|
||||
|
||||
#define C(x) PERF_COUNT_HW_CACHE_##x
|
||||
#define DTLB_LOAD_MISS (C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
|
||||
#define ITLB_LOAD_MISS (C(ITLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
|
||||
|
||||
extern unsigned long itlb_miss_counter, dtlb_miss_counter;
|
||||
extern atomic_t instruction_counter;
|
||||
|
||||
static atomic_t insn_ctr_ref;
|
||||
|
||||
static s64 get_insn_ctr(void)
|
||||
{
|
||||
int ctr;
|
||||
unsigned long counta;
|
||||
|
||||
do {
|
||||
ctr = atomic_read(&instruction_counter);
|
||||
counta = mfspr(SPRN_COUNTA);
|
||||
} while (ctr != atomic_read(&instruction_counter));
|
||||
|
||||
return ((s64)ctr << 16) | (counta >> 16);
|
||||
}
|
||||
|
||||
static int event_type(struct perf_event *event)
|
||||
{
|
||||
switch (event->attr.type) {
|
||||
case PERF_TYPE_HARDWARE:
|
||||
if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES)
|
||||
return PERF_8xx_ID_CPU_CYCLES;
|
||||
if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS)
|
||||
return PERF_8xx_ID_HW_INSTRUCTIONS;
|
||||
break;
|
||||
case PERF_TYPE_HW_CACHE:
|
||||
if (event->attr.config == ITLB_LOAD_MISS)
|
||||
return PERF_8xx_ID_ITLB_LOAD_MISS;
|
||||
if (event->attr.config == DTLB_LOAD_MISS)
|
||||
return PERF_8xx_ID_DTLB_LOAD_MISS;
|
||||
break;
|
||||
case PERF_TYPE_RAW:
|
||||
break;
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static int mpc8xx_pmu_event_init(struct perf_event *event)
|
||||
{
|
||||
int type = event_type(event);
|
||||
|
||||
if (type < 0)
|
||||
return type;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_pmu_add(struct perf_event *event, int flags)
|
||||
{
|
||||
int type = event_type(event);
|
||||
s64 val = 0;
|
||||
|
||||
if (type < 0)
|
||||
return type;
|
||||
|
||||
switch (type) {
|
||||
case PERF_8xx_ID_CPU_CYCLES:
|
||||
val = get_tb();
|
||||
break;
|
||||
case PERF_8xx_ID_HW_INSTRUCTIONS:
|
||||
if (atomic_inc_return(&insn_ctr_ref) == 1)
|
||||
mtspr(SPRN_ICTRL, 0xc0080007);
|
||||
val = get_insn_ctr();
|
||||
break;
|
||||
case PERF_8xx_ID_ITLB_LOAD_MISS:
|
||||
val = itlb_miss_counter;
|
||||
break;
|
||||
case PERF_8xx_ID_DTLB_LOAD_MISS:
|
||||
val = dtlb_miss_counter;
|
||||
break;
|
||||
}
|
||||
local64_set(&event->hw.prev_count, val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mpc8xx_pmu_read(struct perf_event *event)
|
||||
{
|
||||
int type = event_type(event);
|
||||
s64 prev, val = 0, delta = 0;
|
||||
|
||||
if (type < 0)
|
||||
return;
|
||||
|
||||
do {
|
||||
prev = local64_read(&event->hw.prev_count);
|
||||
switch (type) {
|
||||
case PERF_8xx_ID_CPU_CYCLES:
|
||||
val = get_tb();
|
||||
delta = 16 * (val - prev);
|
||||
break;
|
||||
case PERF_8xx_ID_HW_INSTRUCTIONS:
|
||||
val = get_insn_ctr();
|
||||
delta = prev - val;
|
||||
if (delta < 0)
|
||||
delta += 0x1000000000000LL;
|
||||
break;
|
||||
case PERF_8xx_ID_ITLB_LOAD_MISS:
|
||||
val = itlb_miss_counter;
|
||||
delta = (s64)((s32)val - (s32)prev);
|
||||
break;
|
||||
case PERF_8xx_ID_DTLB_LOAD_MISS:
|
||||
val = dtlb_miss_counter;
|
||||
delta = (s64)((s32)val - (s32)prev);
|
||||
break;
|
||||
}
|
||||
} while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
|
||||
|
||||
local64_add(delta, &event->count);
|
||||
}
|
||||
|
||||
static void mpc8xx_pmu_del(struct perf_event *event, int flags)
|
||||
{
|
||||
mpc8xx_pmu_read(event);
|
||||
if (event_type(event) != PERF_8xx_ID_HW_INSTRUCTIONS)
|
||||
return;
|
||||
|
||||
/* If it was the last user, stop counting to avoid useles overhead */
|
||||
if (atomic_dec_return(&insn_ctr_ref) == 0)
|
||||
mtspr(SPRN_ICTRL, 7);
|
||||
}
|
||||
|
||||
static struct pmu mpc8xx_pmu = {
|
||||
.event_init = mpc8xx_pmu_event_init,
|
||||
.add = mpc8xx_pmu_add,
|
||||
.del = mpc8xx_pmu_del,
|
||||
.read = mpc8xx_pmu_read,
|
||||
.capabilities = PERF_PMU_CAP_NO_INTERRUPT |
|
||||
PERF_PMU_CAP_NO_NMI,
|
||||
};
|
||||
|
||||
static int init_mpc8xx_pmu(void)
|
||||
{
|
||||
mtspr(SPRN_ICTRL, 7);
|
||||
mtspr(SPRN_CMPA, 0);
|
||||
mtspr(SPRN_COUNTA, 0xffff);
|
||||
|
||||
return perf_pmu_register(&mpc8xx_pmu, "cpu", PERF_TYPE_RAW);
|
||||
}
|
||||
|
||||
early_initcall(init_mpc8xx_pmu);
|
||||
|
|
@ -13,5 +13,7 @@ obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
|
|||
|
||||
obj-$(CONFIG_HV_PERF_CTRS) += hv-24x7.o hv-gpci.o hv-common.o
|
||||
|
||||
obj-$(CONFIG_PPC_8xx_PERF_EVENT) += 8xx-pmu.o
|
||||
|
||||
obj-$(CONFIG_PPC64) += $(obj64-y)
|
||||
obj-$(CONFIG_PPC32) += $(obj32-y)
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
|
|||
obj-$(CONFIG_P1023_RDB) += p1023_rdb.o
|
||||
obj-$(CONFIG_TWR_P102x) += twr_p102x.o
|
||||
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
|
||||
obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o
|
||||
obj-$(CONFIG_STX_GP3) += stx_gp3.o
|
||||
obj-$(CONFIG_TQM85xx) += tqm85xx.o
|
||||
obj-$(CONFIG_SBC8548) += sbc8548.o
|
||||
|
|
|
|||
|
|
@ -157,6 +157,7 @@ static const char * const boards[] __initconst = {
|
|||
"fsl,T1040RDB",
|
||||
"fsl,T1042RDB",
|
||||
"fsl,T1042RDB_PI",
|
||||
"keymile,kmcent2",
|
||||
"keymile,kmcoge4",
|
||||
"varisys,CYRUS",
|
||||
NULL
|
||||
|
|
|
|||
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* T1042 platform DIU operation
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
|
||||
/*DIU Pixel ClockCR offset in scfg*/
|
||||
#define CCSR_SCFG_PIXCLKCR 0x28
|
||||
|
||||
/* DIU Pixel Clock bits of the PIXCLKCR */
|
||||
#define PIXCLKCR_PXCKEN 0x80000000
|
||||
#define PIXCLKCR_PXCKINV 0x40000000
|
||||
#define PIXCLKCR_PXCKDLY 0x0000FF00
|
||||
#define PIXCLKCR_PXCLK_MASK 0x00FF0000
|
||||
|
||||
/* Some CPLD register definitions */
|
||||
#define CPLD_DIUCSR 0x16
|
||||
#define CPLD_DIUCSR_DVIEN 0x80
|
||||
#define CPLD_DIUCSR_BACKLIGHT 0x0f
|
||||
|
||||
struct device_node *cpld_node;
|
||||
|
||||
/**
|
||||
* t1042rdb_set_monitor_port: switch the output to a different monitor port
|
||||
*/
|
||||
static void t1042rdb_set_monitor_port(enum fsl_diu_monitor_port port)
|
||||
{
|
||||
static void __iomem *cpld_base;
|
||||
|
||||
cpld_base = of_iomap(cpld_node, 0);
|
||||
if (!cpld_base) {
|
||||
pr_err("%s: Could not map cpld registers\n", __func__);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
switch (port) {
|
||||
case FSL_DIU_PORT_DVI:
|
||||
/* Enable the DVI(HDMI) port, disable the DFP and
|
||||
* the backlight
|
||||
*/
|
||||
clrbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_DVIEN);
|
||||
break;
|
||||
case FSL_DIU_PORT_LVDS:
|
||||
/*
|
||||
* LVDS also needs backlight enabled, otherwise the display
|
||||
* will be blank.
|
||||
*/
|
||||
/* Enable the DFP port, disable the DVI*/
|
||||
setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 8);
|
||||
setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4);
|
||||
setbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_BACKLIGHT);
|
||||
break;
|
||||
default:
|
||||
pr_err("%s: Unsupported monitor port %i\n", __func__, port);
|
||||
}
|
||||
|
||||
iounmap(cpld_base);
|
||||
exit:
|
||||
of_node_put(cpld_node);
|
||||
}
|
||||
|
||||
/**
|
||||
* t1042rdb_set_pixel_clock: program the DIU's clock
|
||||
* @pixclock: pixel clock in ps (pico seconds)
|
||||
*/
|
||||
static void t1042rdb_set_pixel_clock(unsigned int pixclock)
|
||||
{
|
||||
struct device_node *scfg_np;
|
||||
void __iomem *scfg;
|
||||
unsigned long freq;
|
||||
u64 temp;
|
||||
u32 pxclk;
|
||||
|
||||
scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg");
|
||||
if (!scfg_np) {
|
||||
pr_err("%s: Missing scfg node. Can not display video.\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
scfg = of_iomap(scfg_np, 0);
|
||||
of_node_put(scfg_np);
|
||||
if (!scfg) {
|
||||
pr_err("%s: Could not map device. Can not display video.\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Convert pixclock into frequency */
|
||||
temp = 1000000000000ULL;
|
||||
do_div(temp, pixclock);
|
||||
freq = temp;
|
||||
|
||||
/*
|
||||
* 'pxclk' is the ratio of the platform clock to the pixel clock.
|
||||
* This number is programmed into the PIXCLKCR register, and the valid
|
||||
* range of values is 2-255.
|
||||
*/
|
||||
pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
|
||||
pxclk = clamp_t(u32, pxclk, 2, 255);
|
||||
|
||||
/* Disable the pixel clock, and set it to non-inverted and no delay */
|
||||
clrbits32(scfg + CCSR_SCFG_PIXCLKCR,
|
||||
PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
|
||||
|
||||
/* Enable the clock and set the pxclk */
|
||||
setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
|
||||
|
||||
iounmap(scfg);
|
||||
}
|
||||
|
||||
/**
|
||||
* t1042rdb_valid_monitor_port: set the monitor port for sysfs
|
||||
*/
|
||||
static enum fsl_diu_monitor_port
|
||||
t1042rdb_valid_monitor_port(enum fsl_diu_monitor_port port)
|
||||
{
|
||||
switch (port) {
|
||||
case FSL_DIU_PORT_DVI:
|
||||
case FSL_DIU_PORT_LVDS:
|
||||
return port;
|
||||
default:
|
||||
return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
|
||||
}
|
||||
}
|
||||
|
||||
static int __init t1042rdb_diu_init(void)
|
||||
{
|
||||
cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld");
|
||||
if (!cpld_node)
|
||||
return 0;
|
||||
|
||||
diu_ops.set_monitor_port = t1042rdb_set_monitor_port;
|
||||
diu_ops.set_pixel_clock = t1042rdb_set_pixel_clock;
|
||||
diu_ops.valid_monitor_port = t1042rdb_valid_monitor_port;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
early_initcall(t1042rdb_diu_init);
|
||||
|
|
@ -172,6 +172,13 @@ config PPC_FPU
|
|||
bool
|
||||
default y if PPC64
|
||||
|
||||
config PPC_8xx_PERF_EVENT
|
||||
bool "PPC 8xx perf events"
|
||||
depends on PPC_8xx && PERF_EVENTS
|
||||
help
|
||||
This is Performance Events support for PPC 8xx. The 8xx doesn't
|
||||
have a PMU but some events are emulated using 8xx features.
|
||||
|
||||
config FSL_EMB_PERFMON
|
||||
bool "Freescale Embedded Perfmon"
|
||||
depends on E500 || PPC_83xx
|
||||
|
|
|
|||
Loading…
Reference in New Issue