Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: pch_irq_handler -> {ibx, cpt}_irq_handler char/agp: add another Ironlake host bridge drm/i915: fix up ivb plane 3 pageflips drm/i915: hold forcewake around ring hw init drm/i915: Mark the ringbuffers as being in the GTT domain drm/i915/crt: Do not rely upon the HPD presence pin drm/i915: Reset last_retired_head when resetting ring
This commit is contained in:
commit
6cf98d6ebb
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@ -898,6 +898,7 @@ static struct pci_device_id agp_intel_pci_table[] = {
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ID(PCI_DEVICE_ID_INTEL_B43_HB),
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ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
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@ -212,6 +212,7 @@
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#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
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#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
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@ -233,6 +233,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_pch_split = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_sandybridge_m_info = {
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@ -243,6 +244,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_pch_split = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_ivybridge_d_info = {
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@ -252,6 +254,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_pch_split = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_ivybridge_m_info = {
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@ -262,6 +265,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_pch_split = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_valleyview_m_info = {
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@ -289,6 +293,7 @@ static const struct intel_device_info intel_haswell_d_info = {
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_pch_split = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_haswell_m_info = {
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@ -298,6 +303,7 @@ static const struct intel_device_info intel_haswell_m_info = {
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_pch_split = 1,
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.has_force_wake = 1,
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};
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static const struct pci_device_id pciidlist[] = { /* aka */
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@ -1139,10 +1145,9 @@ MODULE_LICENSE("GPL and additional rights");
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/* We give fast paths for the really cool registers */
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#define NEEDS_FORCE_WAKE(dev_priv, reg) \
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(((dev_priv)->info->gen >= 6) && \
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((HAS_FORCE_WAKE((dev_priv)->dev)) && \
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((reg) < 0x40000) && \
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((reg) != FORCEWAKE)) && \
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(!IS_VALLEYVIEW((dev_priv)->dev))
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((reg) != FORCEWAKE))
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#define __i915_read(x, y) \
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u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
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@ -285,6 +285,7 @@ struct intel_device_info {
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u8 is_ivybridge:1;
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u8 is_valleyview:1;
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u8 has_pch_split:1;
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u8 has_force_wake:1;
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u8 is_haswell:1;
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u8 has_fbc:1;
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u8 has_pipe_cxsr:1;
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@ -1101,6 +1102,8 @@ struct drm_i915_file_private {
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#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
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#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
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#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
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#include "i915_trace.h"
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/**
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@ -510,7 +510,7 @@ out:
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return ret;
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}
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static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
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static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int pipe;
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@ -550,6 +550,35 @@ static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
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DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
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}
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static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int pipe;
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if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
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DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
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(pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
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SDE_AUDIO_POWER_SHIFT_CPT);
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if (pch_iir & SDE_AUX_MASK_CPT)
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DRM_DEBUG_DRIVER("AUX channel interrupt\n");
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if (pch_iir & SDE_GMBUS_CPT)
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DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
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if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
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DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
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if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
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DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
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if (pch_iir & SDE_FDI_MASK_CPT)
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for_each_pipe(pipe)
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DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
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pipe_name(pipe),
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I915_READ(FDI_RX_IIR(pipe)));
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}
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static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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@ -591,7 +620,7 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
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if (pch_iir & SDE_HOTPLUG_MASK_CPT)
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queue_work(dev_priv->wq, &dev_priv->hotplug_work);
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pch_irq_handler(dev, pch_iir);
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cpt_irq_handler(dev, pch_iir);
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/* clear PCH hotplug event before clear CPU irq */
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I915_WRITE(SDEIIR, pch_iir);
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@ -684,7 +713,10 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
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if (de_iir & DE_PCH_EVENT) {
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if (pch_iir & hotplug_mask)
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queue_work(dev_priv->wq, &dev_priv->hotplug_work);
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pch_irq_handler(dev, pch_iir);
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if (HAS_PCH_CPT(dev))
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cpt_irq_handler(dev, pch_iir);
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else
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ibx_irq_handler(dev, pch_iir);
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}
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if (de_iir & DE_PCU_EVENT) {
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@ -210,6 +210,14 @@
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#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
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#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
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#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
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/* IVB has funny definitions for which plane to flip. */
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#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
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#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
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#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
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#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
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#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
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#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
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#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
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#define MI_MM_SPACE_GTT (1<<8)
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#define MI_MM_SPACE_PHYSICAL (0<<8)
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@ -3313,7 +3321,7 @@
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/* PCH */
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/* south display engine interrupt */
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/* south display engine interrupt: IBX */
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#define SDE_AUDIO_POWER_D (1 << 27)
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#define SDE_AUDIO_POWER_C (1 << 26)
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#define SDE_AUDIO_POWER_B (1 << 25)
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@ -3349,15 +3357,44 @@
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#define SDE_TRANSA_CRC_ERR (1 << 1)
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#define SDE_TRANSA_FIFO_UNDER (1 << 0)
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#define SDE_TRANS_MASK (0x3f)
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/* CPT */
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#define SDE_CRT_HOTPLUG_CPT (1 << 19)
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/* south display engine interrupt: CPT/PPT */
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#define SDE_AUDIO_POWER_D_CPT (1 << 31)
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#define SDE_AUDIO_POWER_C_CPT (1 << 30)
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#define SDE_AUDIO_POWER_B_CPT (1 << 29)
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#define SDE_AUDIO_POWER_SHIFT_CPT 29
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#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
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#define SDE_AUXD_CPT (1 << 27)
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#define SDE_AUXC_CPT (1 << 26)
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#define SDE_AUXB_CPT (1 << 25)
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#define SDE_AUX_MASK_CPT (7 << 25)
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#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
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#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
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#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
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#define SDE_CRT_HOTPLUG_CPT (1 << 19)
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#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
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SDE_PORTD_HOTPLUG_CPT | \
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SDE_PORTC_HOTPLUG_CPT | \
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SDE_PORTB_HOTPLUG_CPT)
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#define SDE_GMBUS_CPT (1 << 17)
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#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
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#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
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#define SDE_FDI_RXC_CPT (1 << 8)
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#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
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#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
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#define SDE_FDI_RXB_CPT (1 << 4)
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#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
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#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
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#define SDE_FDI_RXA_CPT (1 << 0)
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#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
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SDE_AUDIO_CP_REQ_B_CPT | \
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SDE_AUDIO_CP_REQ_A_CPT)
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#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
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SDE_AUDIO_CP_CHG_B_CPT | \
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SDE_AUDIO_CP_CHG_A_CPT)
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#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
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SDE_FDI_RXB_CPT | \
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SDE_FDI_RXA_CPT)
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#define SDEISR 0xc4000
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#define SDEIMR 0xc4004
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@ -453,13 +453,15 @@ intel_crt_detect(struct drm_connector *connector, bool force)
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struct intel_load_detect_pipe tmp;
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if (I915_HAS_HOTPLUG(dev)) {
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/* We can not rely on the HPD pin always being correctly wired
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* up, for example many KVM do not pass it through, and so
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* only trust an assertion that the monitor is connected.
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*/
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if (intel_crt_detect_hotplug(connector)) {
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DRM_DEBUG_KMS("CRT detected via hotplug\n");
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return connector_status_connected;
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} else {
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} else
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DRM_DEBUG_KMS("CRT not detected via hotplug\n");
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return connector_status_disconnected;
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}
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}
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if (intel_crt_detect_ddc(connector))
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@ -6158,17 +6158,34 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
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uint32_t plane_bit = 0;
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int ret;
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ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
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if (ret)
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goto err;
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switch(intel_crtc->plane) {
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case PLANE_A:
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plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
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break;
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case PLANE_B:
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plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
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break;
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case PLANE_C:
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plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
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break;
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default:
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WARN_ONCE(1, "unknown plane in flip command\n");
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ret = -ENODEV;
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goto err;
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}
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ret = intel_ring_begin(ring, 4);
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if (ret)
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goto err_unpin;
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intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
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intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
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intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
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intel_ring_emit(ring, (obj->gtt_offset));
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intel_ring_emit(ring, (MI_NOOP));
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@ -266,10 +266,15 @@ u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
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static int init_ring_common(struct intel_ring_buffer *ring)
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{
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj = ring->obj;
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int ret = 0;
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u32 head;
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if (HAS_FORCE_WAKE(dev))
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gen6_gt_force_wake_get(dev_priv);
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/* Stop the ring if it's running. */
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I915_WRITE_CTL(ring, 0);
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I915_WRITE_HEAD(ring, 0);
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@ -317,7 +322,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
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I915_READ_HEAD(ring),
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I915_READ_TAIL(ring),
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I915_READ_START(ring));
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return -EIO;
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ret = -EIO;
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goto out;
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}
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if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
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@ -326,9 +332,14 @@ static int init_ring_common(struct intel_ring_buffer *ring)
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ring->head = I915_READ_HEAD(ring);
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ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
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ring->space = ring_space(ring);
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ring->last_retired_head = -1;
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}
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return 0;
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out:
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if (HAS_FORCE_WAKE(dev))
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gen6_gt_force_wake_put(dev_priv);
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return ret;
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}
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static int
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|
@ -987,6 +998,10 @@ static int intel_init_ring_buffer(struct drm_device *dev,
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if (ret)
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goto err_unref;
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ret = i915_gem_object_set_to_gtt_domain(obj, true);
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if (ret)
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goto err_unpin;
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ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
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ring->size);
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||||
if (ring->virtual_start == NULL) {
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|
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