powerpc/85xx: add cache-sram support
It adds cache-sram support in P1/P2 QorIQ platforms as under:
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Drivers can do the following in Kconfig to use these APIs
"select FSL_85XX_CACHE_SRAM if MPC85xx"
* Required SRAM size and the offset where SRAM should be mapped must be
provided at kernel command line as :
cache-sram-size=<value>
cache-sram-offset=<offset>
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Harninder Rai
Kumar Gala
parent
6341efe4b9
commit
6db92cc9d0
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@ -0,0 +1,48 @@
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* Cache SRAM handling for QorIQ platform
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*
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* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
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* This file is derived from the original work done
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* by Sylvain Munaut for the Bestcomm SRAM allocator.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
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#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
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#include <asm/rheap.h>
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#include <linux/spinlock.h>
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/*
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* Cache-SRAM
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*/
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struct mpc85xx_cache_sram {
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phys_addr_t base_phys;
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void *base_virt;
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unsigned int size;
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rh_info_t *rh;
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spinlock_t lock;
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};
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extern void mpc85xx_cache_sram_free(void *ptr);
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extern void *mpc85xx_cache_sram_alloc(unsigned int size,
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phys_addr_t *phys, unsigned int align);
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#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
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@ -18,6 +18,7 @@ obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
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obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
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obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
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obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
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obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
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obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
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obj-$(CONFIG_RAPIDIO) += fsl_rio.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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@ -0,0 +1,101 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc
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*
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* QorIQ based Cache Controller Memory Mapped Registers
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*
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* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __FSL_85XX_CACHE_CTLR_H__
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#define __FSL_85XX_CACHE_CTLR_H__
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#define L2CR_L2FI 0x40000000 /* L2 flash invalidate */
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#define L2CR_L2IO 0x00200000 /* L2 instruction only */
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#define L2CR_SRAM_ZERO 0x00000000 /* L2SRAM zero size */
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#define L2CR_SRAM_FULL 0x00010000 /* L2SRAM full size */
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#define L2CR_SRAM_HALF 0x00020000 /* L2SRAM half size */
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#define L2CR_SRAM_TWO_HALFS 0x00030000 /* L2SRAM two half sizes */
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#define L2CR_SRAM_QUART 0x00040000 /* L2SRAM one quarter size */
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#define L2CR_SRAM_TWO_QUARTS 0x00050000 /* L2SRAM two quarter size */
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#define L2CR_SRAM_EIGHTH 0x00060000 /* L2SRAM one eighth size */
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#define L2CR_SRAM_TWO_EIGHTH 0x00070000 /* L2SRAM two eighth size */
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#define L2SRAM_OPTIMAL_SZ_SHIFT 0x00000003 /* Optimum size for L2SRAM */
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#define L2SRAM_BAR_MSK_LO18 0xFFFFC000 /* Lower 18 bits */
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#define L2SRAM_BARE_MSK_HI4 0x0000000F /* Upper 4 bits */
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enum cache_sram_lock_ways {
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LOCK_WAYS_ZERO,
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LOCK_WAYS_EIGHTH,
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LOCK_WAYS_TWO_EIGHTH,
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LOCK_WAYS_HALF = 4,
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LOCK_WAYS_FULL = 8,
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};
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struct mpc85xx_l2ctlr {
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u32 ctl; /* 0x000 - L2 control */
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u8 res1[0xC];
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u32 ewar0; /* 0x010 - External write address 0 */
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u32 ewarea0; /* 0x014 - External write address extended 0 */
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u32 ewcr0; /* 0x018 - External write ctrl */
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u8 res2[4];
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u32 ewar1; /* 0x020 - External write address 1 */
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u32 ewarea1; /* 0x024 - External write address extended 1 */
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u32 ewcr1; /* 0x028 - External write ctrl 1 */
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u8 res3[4];
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u32 ewar2; /* 0x030 - External write address 2 */
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u32 ewarea2; /* 0x034 - External write address extended 2 */
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u32 ewcr2; /* 0x038 - External write ctrl 2 */
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u8 res4[4];
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u32 ewar3; /* 0x040 - External write address 3 */
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u32 ewarea3; /* 0x044 - External write address extended 3 */
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u32 ewcr3; /* 0x048 - External write ctrl 3 */
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u8 res5[0xB4];
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u32 srbar0; /* 0x100 - SRAM base address 0 */
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u32 srbarea0; /* 0x104 - SRAM base addr reg ext address 0 */
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u32 srbar1; /* 0x108 - SRAM base address 1 */
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u32 srbarea1; /* 0x10C - SRAM base addr reg ext address 1 */
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u8 res6[0xCF0];
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u32 errinjhi; /* 0xE00 - Error injection mask high */
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u32 errinjlo; /* 0xE04 - Error injection mask low */
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u32 errinjctl; /* 0xE08 - Error injection tag/ecc control */
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u8 res7[0x14];
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u32 captdatahi; /* 0xE20 - Error data high capture */
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u32 captdatalo; /* 0xE24 - Error data low capture */
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u32 captecc; /* 0xE28 - Error syndrome */
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u8 res8[0x14];
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u32 errdet; /* 0xE40 - Error detect */
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u32 errdis; /* 0xE44 - Error disable */
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u32 errinten; /* 0xE48 - Error interrupt enable */
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u32 errattr; /* 0xE4c - Error attribute capture */
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u32 erradrrl; /* 0xE50 - Error address capture low */
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u32 erradrrh; /* 0xE54 - Error address capture high */
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u32 errctl; /* 0xE58 - Error control */
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u8 res9[0x1A4];
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};
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struct sram_parameters {
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unsigned int sram_size;
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uint64_t sram_offset;
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};
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extern int instantiate_cache_sram(struct platform_device *dev,
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struct sram_parameters sram_params);
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extern void remove_cache_sram(struct platform_device *dev);
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#endif /* __FSL_85XX_CACHE_CTLR_H__ */
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@ -0,0 +1,159 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* Simple memory allocator abstraction for QorIQ (P1/P2) based Cache-SRAM
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*
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* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
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*
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* This file is derived from the original work done
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* by Sylvain Munaut for the Bestcomm SRAM allocator.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of_platform.h>
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#include <asm/pgtable.h>
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#include <asm/fsl_85xx_cache_sram.h>
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#include "fsl_85xx_cache_ctlr.h"
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struct mpc85xx_cache_sram *cache_sram;
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void *mpc85xx_cache_sram_alloc(unsigned int size,
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phys_addr_t *phys, unsigned int align)
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{
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unsigned long offset;
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unsigned long flags;
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if (unlikely(cache_sram == NULL))
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return NULL;
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if (!size || (size > cache_sram->size) || (align > cache_sram->size)) {
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pr_err("%s(): size(=%x) or align(=%x) zero or too big\n",
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__func__, size, align);
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return NULL;
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}
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if ((align & (align - 1)) || align <= 1) {
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pr_err("%s(): align(=%x) must be power of two and >1\n",
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__func__, align);
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return NULL;
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}
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spin_lock_irqsave(&cache_sram->lock, flags);
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offset = rh_alloc_align(cache_sram->rh, size, align, NULL);
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spin_unlock_irqrestore(&cache_sram->lock, flags);
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if (IS_ERR_VALUE(offset))
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return NULL;
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*phys = cache_sram->base_phys + offset;
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return (unsigned char *)cache_sram->base_virt + offset;
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}
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EXPORT_SYMBOL(mpc85xx_cache_sram_alloc);
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void mpc85xx_cache_sram_free(void *ptr)
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{
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unsigned long flags;
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BUG_ON(!ptr);
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spin_lock_irqsave(&cache_sram->lock, flags);
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rh_free(cache_sram->rh, ptr - cache_sram->base_virt);
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spin_unlock_irqrestore(&cache_sram->lock, flags);
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}
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EXPORT_SYMBOL(mpc85xx_cache_sram_free);
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int __init instantiate_cache_sram(struct platform_device *dev,
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struct sram_parameters sram_params)
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{
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int ret = 0;
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if (cache_sram) {
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dev_err(&dev->dev, "Already initialized cache-sram\n");
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return -EBUSY;
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}
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cache_sram = kzalloc(sizeof(struct mpc85xx_cache_sram), GFP_KERNEL);
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if (!cache_sram) {
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dev_err(&dev->dev, "Out of memory for cache_sram structure\n");
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return -ENOMEM;
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}
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cache_sram->base_phys = sram_params.sram_offset;
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cache_sram->size = sram_params.sram_size;
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if (!request_mem_region(cache_sram->base_phys, cache_sram->size,
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"fsl_85xx_cache_sram")) {
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dev_err(&dev->dev, "%s: request memory failed\n",
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dev->dev.of_node->full_name);
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ret = -ENXIO;
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goto out_free;
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}
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cache_sram->base_virt = ioremap_flags(cache_sram->base_phys,
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cache_sram->size, _PAGE_COHERENT | PAGE_KERNEL);
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if (!cache_sram->base_virt) {
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dev_err(&dev->dev, "%s: ioremap_flags failed\n",
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dev->dev.of_node->full_name);
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ret = -ENOMEM;
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goto out_release;
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}
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cache_sram->rh = rh_create(sizeof(unsigned int));
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if (IS_ERR(cache_sram->rh)) {
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dev_err(&dev->dev, "%s: Unable to create remote heap\n",
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dev->dev.of_node->full_name);
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ret = PTR_ERR(cache_sram->rh);
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goto out_unmap;
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}
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rh_attach_region(cache_sram->rh, 0, cache_sram->size);
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spin_lock_init(&cache_sram->lock);
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dev_info(&dev->dev, "[base:0x%llx, size:0x%x] configured and loaded\n",
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(unsigned long long)cache_sram->base_phys, cache_sram->size);
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return 0;
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out_unmap:
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iounmap(cache_sram->base_virt);
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out_release:
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release_mem_region(cache_sram->base_phys, cache_sram->size);
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out_free:
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kfree(cache_sram);
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return ret;
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}
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void remove_cache_sram(struct platform_device *dev)
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{
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BUG_ON(!cache_sram);
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rh_detach_region(cache_sram->rh, 0, cache_sram->size);
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rh_destroy(cache_sram->rh);
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iounmap(cache_sram->base_virt);
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release_mem_region(cache_sram->base_phys, cache_sram->size);
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kfree(cache_sram);
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cache_sram = NULL;
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dev_info(&dev->dev, "MPC85xx Cache-SRAM driver unloaded\n");
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}
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@ -0,0 +1,231 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
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*
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* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
|
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* under the terms of the GNU General Public License as published by the
|
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* Free Software Foundation; either version 2 of the License, or (at your
|
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* option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
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*/
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include "fsl_85xx_cache_ctlr.h"
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static char *sram_size;
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static char *sram_offset;
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struct mpc85xx_l2ctlr __iomem *l2ctlr;
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static long get_cache_sram_size(void)
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{
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unsigned long val;
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if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))
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return -EINVAL;
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return val;
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}
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static long get_cache_sram_offset(void)
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{
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unsigned long val;
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if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
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return -EINVAL;
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return val;
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}
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static int __init get_size_from_cmdline(char *str)
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{
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if (!str)
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return 0;
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sram_size = str;
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return 1;
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}
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static int __init get_offset_from_cmdline(char *str)
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{
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if (!str)
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return 0;
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sram_offset = str;
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return 1;
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}
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__setup("cache-sram-size=", get_size_from_cmdline);
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__setup("cache-sram-offset=", get_offset_from_cmdline);
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static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev,
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const struct of_device_id *match)
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{
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long rval;
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unsigned int rem;
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unsigned char ways;
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const unsigned int *prop;
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unsigned int l2cache_size;
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struct sram_parameters sram_params;
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if (!dev->dev.of_node) {
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dev_err(&dev->dev, "Device's OF-node is NULL\n");
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return -EINVAL;
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}
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prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
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if (!prop) {
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dev_err(&dev->dev, "Missing L2 cache-size\n");
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return -EINVAL;
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}
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l2cache_size = *prop;
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sram_params.sram_size = get_cache_sram_size();
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if (sram_params.sram_size <= 0) {
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dev_err(&dev->dev,
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"Entire L2 as cache, Aborting Cache-SRAM stuff\n");
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return -EINVAL;
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}
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sram_params.sram_offset = get_cache_sram_offset();
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if (sram_params.sram_offset <= 0) {
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dev_err(&dev->dev,
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"Entire L2 as cache, provide a valid sram offset\n");
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return -EINVAL;
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}
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||||
|
||||
rem = l2cache_size % sram_params.sram_size;
|
||||
ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
|
||||
if (rem || (ways & (ways - 1))) {
|
||||
dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
l2ctlr = of_iomap(dev->dev.of_node, 0);
|
||||
if (!l2ctlr) {
|
||||
dev_err(&dev->dev, "Can't map L2 controller\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write bits[0-17] to srbar0
|
||||
*/
|
||||
out_be32(&l2ctlr->srbar0,
|
||||
sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);
|
||||
|
||||
/*
|
||||
* Write bits[18-21] to srbare0
|
||||
*/
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
out_be32(&l2ctlr->srbarea0,
|
||||
(sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
|
||||
#endif
|
||||
|
||||
clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
|
||||
|
||||
switch (ways) {
|
||||
case LOCK_WAYS_EIGHTH:
|
||||
setbits32(&l2ctlr->ctl,
|
||||
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
|
||||
break;
|
||||
|
||||
case LOCK_WAYS_TWO_EIGHTH:
|
||||
setbits32(&l2ctlr->ctl,
|
||||
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
|
||||
break;
|
||||
|
||||
case LOCK_WAYS_HALF:
|
||||
setbits32(&l2ctlr->ctl,
|
||||
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
|
||||
break;
|
||||
|
||||
case LOCK_WAYS_FULL:
|
||||
default:
|
||||
setbits32(&l2ctlr->ctl,
|
||||
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
|
||||
break;
|
||||
}
|
||||
eieio();
|
||||
|
||||
rval = instantiate_cache_sram(dev, sram_params);
|
||||
if (rval < 0) {
|
||||
dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
|
||||
iounmap(l2ctlr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devexit mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
|
||||
{
|
||||
BUG_ON(!l2ctlr);
|
||||
|
||||
iounmap(l2ctlr);
|
||||
remove_cache_sram(dev);
|
||||
dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
|
||||
{
|
||||
.compatible = "fsl,p2020-l2-cache-controller",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p2010-l2-cache-controller",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p1020-l2-cache-controller",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p1011-l2-cache-controller",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p1013-l2-cache-controller",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,p1022-l2-cache-controller",
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct of_platform_driver mpc85xx_l2ctlr_of_platform_driver = {
|
||||
.driver = {
|
||||
.name = "fsl-l2ctlr",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mpc85xx_l2ctlr_of_match,
|
||||
},
|
||||
.probe = mpc85xx_l2ctlr_of_probe,
|
||||
.remove = __devexit_p(mpc85xx_l2ctlr_of_remove),
|
||||
};
|
||||
|
||||
static __init int mpc85xx_l2ctlr_of_init(void)
|
||||
{
|
||||
return of_register_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
|
||||
}
|
||||
|
||||
static void __exit mpc85xx_l2ctlr_of_exit(void)
|
||||
{
|
||||
of_unregister_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
|
||||
}
|
||||
|
||||
subsys_initcall(mpc85xx_l2ctlr_of_init);
|
||||
module_exit(mpc85xx_l2ctlr_of_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue