drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3075,6 +3075,21 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
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seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
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seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
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if (adev->asic_type > CHIP_VEGA20) {
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/* VCN clocks */
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
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if (!value) {
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seq_printf(m, "VCN: Disabled\n");
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} else {
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seq_printf(m, "VCN: Enabled\n");
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
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seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
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seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
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}
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}
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seq_printf(m, "\n");
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} else {
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/* UVD clocks */
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/* UVD clocks */
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
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if (!value) {
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if (!value) {
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@ -3099,6 +3114,7 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
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seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
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seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
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}
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}
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}
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}
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}
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return 0;
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return 0;
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}
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}
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