pinctrl: samsung: Add support for EXYNOS4X12
This patch extends the driver with any necessary SoC-specific definitions to support EXYNOS4X12 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tomasz Figa
Kukjin Kim
parent
bab797f8e3
commit
6edc794a5f
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@ -8,6 +8,7 @@ on-chip controllers onto these pads.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
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- "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
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- "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
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- reg: Base address of the pin controller hardware module and length of
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@ -566,3 +566,113 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
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.label = "exynos4210-gpio-ctrl2",
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},
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};
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/* pin banks of exynos4x12 pin-controller 0 */
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static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
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EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
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EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
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EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
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EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
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EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
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EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
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EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
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EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
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EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
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EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
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EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
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};
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/* pin banks of exynos4x12 pin-controller 1 */
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static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
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EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
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EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
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EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
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EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
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EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
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EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
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EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
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EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
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EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
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EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
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EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
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EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
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EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
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EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
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EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
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EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
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EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
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EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
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EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
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EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
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};
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/* pin banks of exynos4x12 pin-controller 2 */
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static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
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EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
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};
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/* pin banks of exynos4x12 pin-controller 3 */
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static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
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EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
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EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
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EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
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};
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/*
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* Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
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* four gpio/pin-mux/pinconfig controllers.
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*/
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struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
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{
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/* pin-controller instance 0 data */
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.pin_banks = exynos4x12_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.label = "exynos4x12-gpio-ctrl0",
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}, {
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/* pin-controller instance 1 data */
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.pin_banks = exynos4x12_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.weint_con = EXYNOS_WKUP_ECON_OFFSET,
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.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
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.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.label = "exynos4x12-gpio-ctrl1",
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}, {
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/* pin-controller instance 2 data */
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.pin_banks = exynos4x12_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.label = "exynos4x12-gpio-ctrl2",
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}, {
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/* pin-controller instance 3 data */
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.pin_banks = exynos4x12_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.label = "exynos4x12-gpio-ctrl3",
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},
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};
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@ -947,6 +947,8 @@ static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
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static const struct of_device_id samsung_pinctrl_dt_match[] = {
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{ .compatible = "samsung,pinctrl-exynos4210",
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.data = (void *)exynos4210_pin_ctrl },
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{ .compatible = "samsung,pinctrl-exynos4x12",
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.data = (void *)exynos4x12_pin_ctrl },
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{},
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};
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MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
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@ -236,5 +236,6 @@ struct samsung_pmx_func {
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/* list of all exported SoC specific data */
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extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
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#endif /* __PINCTRL_SAMSUNG_H */
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