drm amdgpu + one i915 fix
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJcbz3fAAoJEAx081l5xIa+8n4P/janbRigmFM+BNhpUD/1uP3P dQl24ABrUB9j5zEepXJMlA6/ynLwbU43TYTK4TTF1qiwp0Hjgxwba64WxDuVk5/k rWvUZ+F7/KCYfB/zi3nWMv7CaPr3GTRscfTdDZqFGY97ZzTf+Ei3/I4MlCum6zJf Q9wdndo6RtamZRazCFVVVIzfNv8pU+mLczFgN0ts84Ve3prumnWxbPok7W13KFat iyZ32QJsay9Il1Tfi5mLchAwV2Td30OuHja2C1k8lLCtiqTf1HBOc+QzPulNdjk9 mkEgyj+2mCETo9nzkx7XR2wqnFgIxsMrCUu3PBOVafFn0C7OYGsu9CxfZBlnWphv 0wqBqA3khcBxDODM2ZzA+yrPpSz+UgDkiGXYREE1xHNGb5i7BxFPS2P2Tr+PvgKz dZE7exuOuS0a+PsVk66K4tkVG7WQdOfu4Nt9yuAbaPXXOFyphc/q99WB8dBcKvfj VyZq+SGJQdgQAloEyQxpHAsoH1++axzcEJeKJhuvD2GAiyOkOpxzBdtClMYg6FUF Wc0OyCdJ99xqM+YI5yhz9oMyoTplFYpvC6L3q7hYdxWcaqeYn92EvEa4siUSOorY mQfJOuuXKt6DQxfc2IOycv7GNUiC6D/L03YMFPWpbeHie/QR5Ro6AUNUcAz67w5O VsYtbJClm1gVtoC/hf7e =taR/ -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2019-02-22' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "This contains a single i915 tiled display fix, and a set of amdgpu/radeon fixes. i915: - tiled display fix amdgpu/radeon: - runtime PM fix - bulk moves disable (fix is too large for 5.0) - a set of display fixes that are all cc'ed stable so we didn't want to leave them until -next" * tag 'drm-fixes-2019-02-22' of git://anongit.freedesktop.org/drm/drm: drm/amdgpu: disable bulk moves for now drm/amd/display: set clocks to 0 on suspend on dce80 drm/amd/display: fix optimize_bandwidth func pointer for dce80 drm/amd/display: Fix negative cursor pos programming drm/i915/fbdev: Actually configure untiled displays drm/amd/display: Raise dispclk value for dce11 drm/amd/display: Fix MST reboot/poweroff sequence drm/amdgpu: Update sdma golden setting for vega20 drm/amdgpu: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime gpu: drm: radeon: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime
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commit
6ee2846cb4
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@ -212,6 +212,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
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}
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if (amdgpu_device_is_px(dev)) {
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dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
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pm_runtime_use_autosuspend(dev->dev);
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pm_runtime_set_autosuspend_delay(dev->dev, 5000);
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pm_runtime_set_active(dev->dev);
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@ -638,12 +638,14 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
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struct ttm_bo_global *glob = adev->mman.bdev.glob;
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struct amdgpu_vm_bo_base *bo_base;
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#if 0
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if (vm->bulk_moveable) {
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spin_lock(&glob->lru_lock);
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ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
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spin_unlock(&glob->lru_lock);
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return;
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}
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#endif
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memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
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@ -128,7 +128,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
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static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
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{
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
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SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
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@ -158,7 +158,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
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};
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static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
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SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
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SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
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SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
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SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
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SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
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@ -786,12 +786,13 @@ static int dm_suspend(void *handle)
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struct amdgpu_display_manager *dm = &adev->dm;
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int ret = 0;
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WARN_ON(adev->dm.cached_state);
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adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
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s3_handle_mst(adev->ddev, true);
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amdgpu_dm_irq_suspend(adev);
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WARN_ON(adev->dm.cached_state);
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adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
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dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
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@ -662,6 +662,11 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr,
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{
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struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
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struct dm_pp_power_level_change_request level_change_req;
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int patched_disp_clk = context->bw.dce.dispclk_khz;
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/*TODO: W/A for dal3 linux, investigate why this works */
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if (!clk_mgr_dce->dfs_bypass_active)
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patched_disp_clk = patched_disp_clk * 115 / 100;
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level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
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/* get max clock state from PPLIB */
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@ -671,9 +676,9 @@ static void dce11_update_clocks(struct clk_mgr *clk_mgr,
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clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
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}
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if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
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context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
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clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
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if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
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context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);
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clk_mgr->clks.dispclk_khz = patched_disp_clk;
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}
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dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
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}
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@ -37,6 +37,10 @@ void dce100_prepare_bandwidth(
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struct dc *dc,
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struct dc_state *context);
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void dce100_optimize_bandwidth(
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struct dc *dc,
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struct dc_state *context);
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bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
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struct dc_bios *dcb,
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enum pipe_gating_control power_gating);
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@ -77,6 +77,6 @@ void dce80_hw_sequencer_construct(struct dc *dc)
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dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
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dc->hwss.pipe_control_lock = dce_pipe_control_lock;
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dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
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dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
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dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
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}
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@ -790,9 +790,22 @@ bool dce80_validate_bandwidth(
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struct dc *dc,
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struct dc_state *context)
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{
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int i;
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bool at_least_one_pipe = false;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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if (context->res_ctx.pipe_ctx[i].stream)
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at_least_one_pipe = true;
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}
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if (at_least_one_pipe) {
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/* TODO implement when needed but for now hardcode max value*/
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context->bw.dce.dispclk_khz = 681000;
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context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
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} else {
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context->bw.dce.dispclk_khz = 0;
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context->bw.dce.yclk_khz = 0;
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}
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return true;
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}
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@ -2658,8 +2658,8 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
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.mirror = pipe_ctx->plane_state->horizontal_mirror
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};
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pos_cpy.x -= pipe_ctx->plane_state->dst_rect.x;
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pos_cpy.y -= pipe_ctx->plane_state->dst_rect.y;
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pos_cpy.x_hotspot += pipe_ctx->plane_state->dst_rect.x;
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pos_cpy.y_hotspot += pipe_ctx->plane_state->dst_rect.y;
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if (pipe_ctx->plane_state->address.type
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== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
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@ -336,8 +336,8 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
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bool *enabled, int width, int height)
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{
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struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
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unsigned long conn_configured, conn_seq, mask;
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unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
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unsigned long conn_configured, conn_seq;
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int i, j;
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bool *save_enabled;
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bool fallback = true, ret = true;
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@ -355,10 +355,9 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
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drm_modeset_backoff(&ctx);
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memcpy(save_enabled, enabled, count);
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mask = GENMASK(count - 1, 0);
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conn_seq = GENMASK(count - 1, 0);
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conn_configured = 0;
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retry:
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conn_seq = conn_configured;
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for (i = 0; i < count; i++) {
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struct drm_fb_helper_connector *fb_conn;
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struct drm_connector *connector;
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if (conn_configured & BIT(i))
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continue;
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if (conn_seq == 0 && !connector->has_tile)
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/* First pass, only consider tiled connectors */
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if (conn_seq == GENMASK(count - 1, 0) && !connector->has_tile)
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continue;
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if (connector->status == connector_status_connected)
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conn_configured |= BIT(i);
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}
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if ((conn_configured & mask) != mask && conn_configured != conn_seq)
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if (conn_configured != conn_seq) { /* repeat until no more are found */
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conn_seq = conn_configured;
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goto retry;
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}
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/*
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* If the BIOS didn't enable everything it could, fall back to have the
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@ -172,6 +172,7 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
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}
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if (radeon_is_px(dev)) {
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dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
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pm_runtime_use_autosuspend(dev->dev);
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pm_runtime_set_autosuspend_delay(dev->dev, 5000);
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pm_runtime_set_active(dev->dev);
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