intel-iommu: Performance improvement for domain_pfn_mapping()
As with dma_pte_clear_range(), don't keep flushing a single PTE at a time. And also micro-optimise the setting of PTE values rather than using the helper functions to do all the masking. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -1639,7 +1639,7 @@ static int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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unsigned long phys_pfn, unsigned long nr_pages,
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int prot)
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{
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struct dma_pte *pte;
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struct dma_pte *first_pte = NULL, *pte = NULL;
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int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
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BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
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@ -1647,19 +1647,27 @@ static int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
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return -EINVAL;
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prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
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while (nr_pages--) {
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pte = pfn_to_dma_pte(domain, iov_pfn);
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if (!pte)
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return -ENOMEM;
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if (!pte) {
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first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
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if (!pte)
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return -ENOMEM;
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}
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/* We don't need lock here, nobody else
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* touches the iova range
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*/
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BUG_ON(dma_pte_addr(pte));
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dma_set_pte_pfn(pte, phys_pfn);
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dma_set_pte_prot(pte, prot);
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if (prot & DMA_PTE_SNP)
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dma_set_pte_snp(pte);
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domain_flush_cache(domain, pte, sizeof(*pte));
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pte->val = (phys_pfn << VTD_PAGE_SHIFT) | prot;
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pte++;
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if (!nr_pages ||
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(unsigned long)pte >> VTD_PAGE_SHIFT !=
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(unsigned long)first_pte >> VTD_PAGE_SHIFT) {
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domain_flush_cache(domain, first_pte,
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(void *)pte - (void *)first_pte);
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pte = NULL;
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}
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iov_pfn++;
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phys_pfn++;
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}
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