hpt366: fix PCI clock detection for HPT374 (take 4)
HPT374 BIOS seems to only save f_CNT register value for the function #0 before re-tuning DPLL (that causes the driver to report obviously distorted f_CNT for the function #1) -- fix this by always reading the saved f_CNT register value from the function #0 in the driver's init_chipset() method. While at it, introduce 'chip_type' for holding the 'struct hpt_info' field of the same name and replace the structure assignment with memcpy()... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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7293136810
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@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/hpt366.c Version 1.10 Jun 29, 2007
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* linux/drivers/ide/pci/hpt366.c Version 1.11 Aug 11, 2007
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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@ -68,7 +68,8 @@
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* HPT37x chip family; save space by introducing the separate transfer mode
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* table in which the mode lookup is done
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* - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
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* the wrong PCI frequency since DPLL has already been calibrated by BIOS
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* the wrong PCI frequency since DPLL has already been calibrated by BIOS;
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* read it only from the function 0 of HPT374 chips
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* - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
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* and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
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* - pass to init_chipset() handlers a copy of the IDE PCI device structure as
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@ -981,6 +982,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
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unsigned long io_base = pci_resource_start(dev, 4);
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u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
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u8 chip_type;
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enum ata_clock clock;
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if (info == NULL) {
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@ -992,7 +994,8 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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* Copy everything from a static "template" structure
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* to just allocated per-chip hpt_info structure.
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*/
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*info = *(struct hpt_info *)pci_get_drvdata(dev);
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memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
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chip_type = info->chip_type;
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
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@ -1002,7 +1005,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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/*
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* First, try to estimate the PCI clock frequency...
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*/
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if (info->chip_type >= HPT370) {
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if (chip_type >= HPT370) {
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u8 scr1 = 0;
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u16 f_cnt = 0;
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u32 temp = 0;
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@ -1016,7 +1019,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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* HighPoint does this for HPT372A.
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* NOTE: This register is only writeable via I/O space.
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*/
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if (info->chip_type == HPT372A)
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if (chip_type == HPT372A)
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outb(0x0e, io_base + 0x9c);
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/*
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@ -1034,13 +1037,28 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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* First try reading the register in which the HighPoint BIOS
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* saves f_CNT value before reprogramming the DPLL from its
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* default setting (which differs for the various chips).
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* NOTE: This register is only accessible via I/O space.
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*
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* In case the signature check fails, we'll have to resort to
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* reading the f_CNT register itself in hopes that nobody has
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* touched the DPLL yet...
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* NOTE: This register is only accessible via I/O space;
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* HPT374 BIOS only saves it for the function 0, so we have to
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* always read it from there -- no need to check the result of
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* pci_get_slot() for the function 0 as the whole device has
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* been already "pinned" (via function 1) in init_setup_hpt374()
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*/
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if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
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struct pci_dev *dev1 = pci_get_slot(dev->bus,
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dev->devfn - 1);
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unsigned long io_base = pci_resource_start(dev1, 4);
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temp = inl(io_base + 0x90);
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pci_dev_put(dev1);
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} else
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temp = inl(io_base + 0x90);
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/*
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* In case the signature check fails, we'll have to
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* resort to reading the f_CNT register itself in hopes
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* that nobody has touched the DPLL yet...
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*/
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temp = inl(io_base + 0x90);
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if ((temp & 0xFFFFF000) != 0xABCDE000) {
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int i;
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@ -1120,7 +1138,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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* We also don't like using the DPLL because this causes glitches
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* on PRST-/SRST- when the state engine gets reset...
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*/
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if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
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if (chip_type >= HPT374 || info->settings[clock] == NULL) {
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u16 f_low, delta = pci_clk < 50 ? 2 : 4;
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int adjust;
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@ -1190,7 +1208,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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/* Point to this chip's own instance of the hpt_info structure. */
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pci_set_drvdata(dev, info);
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if (info->chip_type >= HPT370) {
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if (chip_type >= HPT370) {
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u8 mcr1, mcr4;
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/*
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@ -1209,7 +1227,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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* the MISC. register to stretch the UltraDMA Tss timing.
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* NOTE: This register is only writeable via I/O space.
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*/
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if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
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if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
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outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
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