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RISC-V: properly determine hardware caps 

On the Hifive-U platform, cpu 0 is a masked cpu with less capabilities
than the other cpus.  Ignore it for the purpose of determining the
hardware capabilities of the system.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Andreas Schwab 2018-10-23 09:33:47 +02:00 committed by Palmer Dabbelt
parent d26c4bbf99
commit 732e8e4130
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GPG Key ID: EF4CA1502CCBAB41
1 changed files with 5 additions and 3 deletions
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8
arch/riscv/kernel/cpufeature.c
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@ -28,7 +28,7 @@ bool has_fpu __read_mostly;
void riscv_fill_hwcap(void)
{
struct device_node *node;
struct device_node *node = NULL;
const char *isa;
size_t i;
static unsigned long isa2hwcap[256] = {0};
@ -44,9 +44,11 @@ void riscv_fill_hwcap(void)
/*
* We don't support running Linux on hertergenous ISA systems. For
* now, we just check the ISA of the first processor.
* now, we just check the ISA of the first "okay" processor.
*/
node = of_find_node_by_type(NULL, "cpu");
while ((node = of_find_node_by_type(node, "cpu")))
if (riscv_of_processor_hartid(node) >= 0)
break;
if (!node) {
pr_warning("Unable to find \"cpu\" devicetree entry");
return;