From 635f56c342cd195a8059f24296fe7fd795aaa33d Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 14 Jul 2017 18:12:41 +0300 Subject: [PATCH 001/179] drm/i915: Fix error checking/locking in perf/lookup_context() 1acfc104cdf8 missed to convert this one caller to be lockless. The side effect of that was that the error check in lookup_context() became incorrect. Convert now this caller too. Fixes: 1acfc104cdf ("drm/i915: Enable rcu-only context lookups") Cc: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Chris Wilson Reviewed-by: Lionel Landwerlin Signed-off-by: Imre Deak Link: http://patchwork.freedesktop.org/patch/msgid/20170714151242.517-1-imre.deak@intel.com --- drivers/gpu/drm/i915/i915_perf.c | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index d9f77a4d85db..96682fd86f82 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2483,27 +2483,6 @@ static const struct file_operations fops = { }; -static struct i915_gem_context * -lookup_context(struct drm_i915_private *dev_priv, - struct drm_i915_file_private *file_priv, - u32 ctx_user_handle) -{ - struct i915_gem_context *ctx; - int ret; - - ret = i915_mutex_lock_interruptible(&dev_priv->drm); - if (ret) - return ERR_PTR(ret); - - ctx = i915_gem_context_lookup(file_priv, ctx_user_handle); - if (!IS_ERR(ctx)) - i915_gem_context_get(ctx); - - mutex_unlock(&dev_priv->drm.struct_mutex); - - return ctx; -} - /** * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD * @dev_priv: i915 device instance @@ -2545,12 +2524,11 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, u32 ctx_handle = props->ctx_handle; struct drm_i915_file_private *file_priv = file->driver_priv; - specific_ctx = lookup_context(dev_priv, file_priv, ctx_handle); - if (IS_ERR(specific_ctx)) { - ret = PTR_ERR(specific_ctx); - if (ret != -EINTR) - DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n", - ctx_handle); + specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle); + if (!specific_ctx) { + DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n", + ctx_handle); + ret = -ENOENT; goto err; } } From edd9003f7f9dddd28fdd768e6e7569d996c769cb Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 14 Jul 2017 18:12:42 +0300 Subject: [PATCH 002/179] drm/i915: Fix user ptr check size in eb_relocate_vma() Fix the sizeof(ptr) vs. sizeof(*ptr) typo. Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the execobjects array") Cc: Chris Wilson Cc: Joonas Lahtinen Signed-off-by: Imre Deak Reviewed-by: Chris Wilson Link: http://patchwork.freedesktop.org/patch/msgid/20170714151242.517-2-imre.deak@intel.com --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 929f275e67aa..fe3e0d40034c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1459,7 +1459,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma) * to read. However, if the array is not writable the user loses * the updated relocation values. */ - if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(urelocs)))) + if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs)))) return -EFAULT; do { From a21960339c8c107eae99d68c85e6355189b22192 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 17 Jul 2017 11:14:03 -0700 Subject: [PATCH 003/179] drm/i915: Consistently use enum pipe for PCH transcoders The current code uses in some instances enum transcoder for PCH transcoders and enum pipe in others. This is error prone and clang raises warnings like this: drivers/gpu/drm/i915/intel_dp.c:3546:51: warning: implicit conversion from enumeration type 'enum pipe' to different enumeration type 'enum transcoder' [-Wenum-conversion] intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); Consistently use the type enum pipe for PCH transcoders. Signed-off-by: Matthias Kaehlcke Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170717181403.57324-1-mka@chromium.org --- drivers/gpu/drm/i915/i915_irq.c | 10 +++++----- drivers/gpu/drm/i915/intel_display.c | 12 ++++++------ drivers/gpu/drm/i915/intel_drv.h | 6 +++--- drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +++--- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 1d33cea01a1b..0b6f310101ee 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2086,10 +2086,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); if (pch_iir & SDE_TRANSA_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); if (pch_iir & SDE_TRANSB_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); } static void ivb_err_int_handler(struct drm_i915_private *dev_priv) @@ -2123,13 +2123,13 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) DRM_ERROR("PCH poison interrupt\n"); if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C); I915_WRITE(SERR_INT, serr_int); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bb9c9c3c391f..a89d0fd1c2e1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1777,7 +1777,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); - assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); + assert_fdi_rx_enabled(dev_priv, PIPE_A); /* Workaround: set timing override bit. */ val = I915_READ(TRANS_CHICKEN2(PIPE_A)); @@ -1853,16 +1853,16 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); } -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); WARN_ON(!crtc->config->has_pch_encoder); if (HAS_PCH_LPT(dev_priv)) - return TRANSCODER_A; + return PIPE_A; else - return (enum transcoder) crtc->pipe; + return crtc->pipe; } /** @@ -1901,7 +1901,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) if (crtc->config->has_pch_encoder) { /* if driving the PCH, we need FDI enabled */ assert_fdi_rx_pll_enabled(dev_priv, - (enum pipe) intel_crtc_pch_transcoder(crtc)); + intel_crtc_pch_transcoder(crtc)); assert_fdi_tx_pll_enabled(dev_priv, (enum pipe) cpu_transcoder); } @@ -4579,7 +4579,7 @@ static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); + assert_pch_transcoder_disabled(dev_priv, PIPE_A); lpt_program_iclkip(crtc); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d17a32437f07..0902d7cb48d9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1211,12 +1211,12 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable); bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable); void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe); void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder); + enum pipe pch_transcoder); void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); @@ -1326,7 +1326,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, /* intel_display.c */ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc); +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); void intel_update_rawclk(struct drm_i915_private *dev_priv); int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); int vlv_get_cck_clock(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index d484862cc7df..5a7cca32c0fa 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -313,11 +313,11 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, * Returns the previous state of underrun reporting. */ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable) { struct intel_crtc *crtc = - intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder); + intel_get_crtc_for_pipe(dev_priv, pch_transcoder); unsigned long flags; bool old; @@ -390,7 +390,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, * interrupt to avoid an irq storm. */ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder) + enum pipe pch_transcoder) { if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, false)) { From 8753d2bc5e49daad301ce65f5dada57ed924fad6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 14 Jul 2017 18:52:27 +0300 Subject: [PATCH 004/179] drm/i915: Fix cursor updates on some platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Turns out that just writing CURPOS isn't sufficient to move the cursor on some platforms. My 830 works just fine, but eg. 945 and PNV don't. On those platforms we need to arm even the CURPOS update with a CURBASE write. Even worse, a write to any of the cursor register apart from CURBASE will cancel an already pending cursor update. So if we have armed a CURCNTR/CURBASE update, a subsequent CURPOS write prior to vblank would cancel that armed update. Thus we're left with a cursor that doesn't appear to move, or even change shape. Fix the problem by always performing the CURBASE write after a CURPOS write. Bspec is somewhat unclear which platforms actually require this CURBASE write and which don't. So to keep it simple and to make sure we really fix the problem across all supported devices, let's just perform the CURBASE write unconditionally. Cc: Paul Menzel Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101790 Fixes: 75343a44c901 ("drm/i915: Drop useless posting reads from cursor commit") Signed-off-by: Ville Syrjälä Tested-by: Paul Menzel Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170714155227.6089-1-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a89d0fd1c2e1..cbdebb022273 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9555,7 +9555,16 @@ static void i9xx_update_cursor(struct intel_plane *plane, * On some platforms writing CURCNTR first will also * cause CURPOS to be armed by the CURBASE write. * Without the CURCNTR write the CURPOS write would - * arm itself. + * arm itself. Thus we always start the full update + * with a CURCNTR write. + * + * On other platforms CURPOS always requires the + * CURBASE write to arm the update. Additonally + * a write to any of the cursor register will cancel + * an already armed cursor update. Thus leaving out + * the CURBASE write after CURPOS could lead to a + * cursor that doesn't appear to move, or even change + * shape. Thus we always write CURBASE. * * CURCNTR and CUR_FBC_CTL are always * armed by the CURBASE write only. @@ -9574,6 +9583,7 @@ static void i9xx_update_cursor(struct intel_plane *plane, plane->cursor.cntl = cntl; } else { I915_WRITE_FW(CURPOS(pipe), pos); + I915_WRITE_FW(CURBASE(pipe), base); } POSTING_READ_FW(CURBASE(pipe)); From 99a59512a6fd7241f244fa162789e2f80ec91a5d Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Tue, 18 Jul 2017 17:25:36 +0300 Subject: [PATCH 005/179] drm/i915: Explicit the connector name for DP link training result This adds the connector name when printing a debug message about the DP link training result. It is useful to figure out what connector is failing when multiple DP connectors are used. Signed-off-by: Paul Kocialkowski Reviewed-by: Dhinakaran Pandiyan Reviewed-by: Manasi Navare Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170718142536.2306-1-paul.kocialkowski@linux.intel.com --- drivers/gpu/drm/i915/intel_dp_link_training.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index b79c1c0e404c..05907fa8a553 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -321,12 +321,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) if (!intel_dp_link_training_channel_equalization(intel_dp)) goto failure_handling; - DRM_DEBUG_KMS("Link Training Passed at Link Rate = %d, Lane count = %d", + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, intel_dp->link_rate, intel_dp->lane_count); return; failure_handling: - DRM_DEBUG_KMS("Link Training failed at link rate = %d, lane count = %d", + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, intel_dp->link_rate, intel_dp->lane_count); if (!intel_dp_get_link_train_fallback_values(intel_dp, intel_dp->link_rate, From 54d20ed1fff23c7d2633f01fc788111bf9c51c5d Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Mon, 17 Jul 2017 14:02:30 +0200 Subject: [PATCH 006/179] drm/i915: Fix bad comparison in skl_compute_plane_wm, v2. ddb_allocation && ddb_allocation / blocks_per_line >= 1 is the same as ddb_allocation >= blocks_per_line, so use the latter to simplify this. This fixes the following compiler warning: drivers/gpu/drm/i915/intel_pm.c:4467]: (warning) Comparison of a boolean expression with an integer other than 0 or 1. Changes since v1: - Rebase, was missing the changes to the macro names. Signed-off-by: Maarten Lankhorst Fixes: d555cb5827d6 ("drm/i915/skl+: use linetime latency if ddb size is not available") Cc: "Mahesh Kumar" Reported-by: David Binderman Cc: David Binderman Cc: # v4.13-rc1+ Link: http://patchwork.freedesktop.org/patch/msgid/20170717120230.2023-1-maarten.lankhorst@linux.intel.com Reviewed-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ee2a349cfe68..48785ef75d33 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4459,8 +4459,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) && (plane_bytes_per_line / 512 < 1)) selected_result = method2; - else if ((ddb_allocation && ddb_allocation / - fixed16_to_u32_round_up(plane_blocks_per_line)) >= 1) + else if (ddb_allocation >= + fixed16_to_u32_round_up(plane_blocks_per_line)) selected_result = min_fixed16(method1, method2); else if (latency >= linetime_us) selected_result = min_fixed16(method1, method2); From 023f807989f4d6a076258f4efe6d1da0d7aaeb29 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 19 Jul 2017 12:00:43 +0200 Subject: [PATCH 007/179] drm/i915: More stolen quirking I've found a bios with an off-by-one at the other end. There's a pnp reservation for 0xc5400000-0xc7fffffe and we want stolen in 0xc6000000 through 0xc8000000. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99872 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98683 Cc: Martin Peres Reviewed-by: Martin Peres Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170719100043.30851-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/i915_gem_stolen.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index a817b3e0b17e..c11c915382e7 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -254,9 +254,10 @@ static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv) * This is a BIOS w/a: Some BIOS wrap stolen in the root * PCI bus, but have an off-by-one error. Hence retry the * reservation starting from 1 instead of 0. + * There's also BIOS with off-by-one on the other end. */ r = devm_request_mem_region(dev_priv->drm.dev, base + 1, - ggtt->stolen_size - 1, + ggtt->stolen_size - 2, "Graphics Stolen Memory"); /* * GEN3 firmware likes to smash pci bridges into the stolen From 3b19f16a556446c144a1f921444931b0cf9447ab Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 18 Jul 2017 14:41:24 +0100 Subject: [PATCH 008/179] drm/i915: Drain the device workqueue on unload Workers on the i915->wq may rearm themselves so for completeness we need to replace our flush_workqueue() with a call to drain_workqueue() before unloading the device. v2: Reinforce the drain_workqueue with an preceding rcu_barrier() as a few of the tasks that need to be drained may first be armed by RCU. References: https://bugs.freedesktop.org/show_bug.cgi?id=101627 Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Mika Kuoppala Link: http://patchwork.freedesktop.org/patch/msgid/20170718134124.14832-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.c | 6 ++---- drivers/gpu/drm/i915/i915_drv.h | 20 +++++++++++++++++++ .../gpu/drm/i915/selftests/mock_gem_device.c | 2 +- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6f750efe9c3d..799dd3890cd9 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -596,7 +596,8 @@ static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { static void i915_gem_fini(struct drm_i915_private *dev_priv) { - flush_workqueue(dev_priv->wq); + /* Flush any outstanding unpin_work. */ + i915_gem_drain_workqueue(dev_priv); mutex_lock(&dev_priv->drm.struct_mutex); intel_uc_fini_hw(dev_priv); @@ -1413,9 +1414,6 @@ void i915_driver_unload(struct drm_device *dev) cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); i915_reset_error_state(dev_priv); - /* Flush any outstanding unpin_work. */ - drain_workqueue(dev_priv->wq); - i915_gem_fini(dev_priv); intel_uc_fini_fw(dev_priv); intel_fbc_cleanup_cfb(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 559fdc7bb393..017361833c58 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3300,6 +3300,26 @@ static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) } while (flush_work(&i915->mm.free_work)); } +static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) +{ + /* + * Similar to objects above (see i915_gem_drain_freed-objects), in + * general we have workers that are armed by RCU and then rearm + * themselves in their callbacks. To be paranoid, we need to + * drain the workqueue a second time after waiting for the RCU + * grace period so that we catch work queued via RCU from the first + * pass. As neither drain_workqueue() nor flush_workqueue() report + * a result, we make an assumption that we only don't require more + * than 2 passes to catch all recursive RCU delayed work. + * + */ + int pass = 2; + do { + rcu_barrier(); + drain_workqueue(i915->wq); + } while (--pass); +} + struct i915_vma * __must_check i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 47613d20bba8..7a468cb30946 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -57,7 +57,7 @@ static void mock_device_release(struct drm_device *dev) cancel_delayed_work_sync(&i915->gt.retire_work); cancel_delayed_work_sync(&i915->gt.idle_work); - flush_workqueue(i915->wq); + i915_gem_drain_workqueue(i915); mutex_lock(&i915->drm.struct_mutex); for_each_engine(engine, i915, id) From 1a0c19248a2f692af352f8b4b3e9b7f8a43bfd52 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 18 Jul 2017 18:30:28 +0100 Subject: [PATCH 009/179] drm/i915/selftests: Attach a stub pm_domain Supply a pm_domain and its ops for our mock GEM device so that device runtime pm doesn't complain even though we only want to mark it permanently active! Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170718173028.31207-1-chris@chris-wilson.co.uk Tested-by: Matthew Auld Reviewed-by: Matthew Auld --- .../gpu/drm/i915/selftests/mock_gem_device.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 7a468cb30946..d451dfbe9bbb 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -22,6 +22,7 @@ * */ +#include #include #include "mock_engine.h" @@ -109,6 +110,23 @@ static void mock_idle_work_handler(struct work_struct *work) { } +static int pm_domain_resume(struct device *dev) +{ + return pm_generic_runtime_resume(dev); +} + +static int pm_domain_suspend(struct device *dev) +{ + return pm_generic_runtime_suspend(dev); +} + +static struct dev_pm_domain pm_domain = { + .ops = { + .runtime_suspend = pm_domain_suspend, + .runtime_resume = pm_domain_resume, + }, +}; + struct drm_i915_private *mock_gem_device(void) { struct drm_i915_private *i915; @@ -127,8 +145,10 @@ struct drm_i915_private *mock_gem_device(void) dev_set_name(&pdev->dev, "mock"); dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + dev_pm_domain_set(&pdev->dev, &pm_domain); + pm_runtime_enable(&pdev->dev); pm_runtime_dont_use_autosuspend(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); + WARN_ON(pm_runtime_get_sync(&pdev->dev)); i915 = (struct drm_i915_private *)(pdev + 1); pci_set_drvdata(pdev, i915); From 49d70aeaeca8f62b72b7712ecd1e29619a445866 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sat, 15 Jul 2017 11:31:06 +0200 Subject: [PATCH 010/179] drm/atomic-helper: Fix leak in disable_all The legacy plane->fb pointer is refcounted by calling drm_atomic_clean_old_fb(). In practice this isn't a real problem because: - The caller in the i915 gpu reset code restores the original state again, which means the plane->fb pointer won't change, hence can't leak. - Drivers using drm_atomic_helper_shutdown call the fbdev cleanup first, and that usually cleans up the fb through drm_remove_framebuffer, which does this correctly. - Without fbdev the only framebuffers are from userspace, and those get cleaned up (again using drm_remove_framebuffer) befor the driver can even be unloaded. But in i915 I've switched the cleanup sequence around so that the _shutdown() calls happens after the drm_remove_framebuffer(), which is how I discovered this issue. v2: My analysis why the current code was ok for gpu reset and suspend/resume was correct, but then I totally failed to realize that we better keep this symmetric. Thanksfully CI noticed that for balance, a refcounting bug must exist at 2 places if previously there was no issue ... v3: Don't be lazy and compute the plane_mask in commit_duplicated_state properly too, instead of just using ~0U. Cc: martin.peres@free.fr Cc: chris@chris-wilson.co.uk Acked-by: Dave Airlie (v1) Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170715093106.19873-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/drm_atomic_helper.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 86d3093c6c9b..99defa068a98 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -2526,6 +2526,7 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, struct drm_plane *plane; struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; + unsigned plane_mask = 0; int ret, i; state = drm_atomic_state_alloc(dev); @@ -2568,10 +2569,14 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, goto free; drm_atomic_set_fb_for_plane(plane_state, NULL); + plane_mask |= BIT(drm_plane_index(plane)); + plane->old_fb = plane->fb; } ret = drm_atomic_commit(state); free: + if (plane_mask) + drm_atomic_clean_old_fb(dev, plane_mask, ret); drm_atomic_state_put(state); return ret; } @@ -2702,11 +2707,16 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, struct drm_connector_state *new_conn_state; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; + unsigned plane_mask = 0; + struct drm_device *dev = state->dev; + int ret; state->acquire_ctx = ctx; - for_each_new_plane_in_state(state, plane, new_plane_state, i) + for_each_new_plane_in_state(state, plane, new_plane_state, i) { + plane_mask |= BIT(drm_plane_index(plane)); state->planes[i].old_state = plane->state; + } for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) state->crtcs[i].old_state = crtc->state; @@ -2714,7 +2724,11 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, for_each_new_connector_in_state(state, connector, new_conn_state, i) state->connectors[i].old_state = connector->state; - return drm_atomic_commit(state); + ret = drm_atomic_commit(state); + if (plane_mask) + drm_atomic_clean_old_fb(dev, plane_mask, ret); + + return ret; } EXPORT_SYMBOL(drm_atomic_helper_commit_duplicated_state); From 4f256d8219f230cb11b49343931dc0b2fa8bd149 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sat, 15 Jul 2017 00:46:55 +0200 Subject: [PATCH 011/179] drm/i915: Fix fbdev unload sequence First thing we need to do is unregister the fbdev instance, but we can't just go ahead and kfree it. That must wait until the hotplug and polling work are stopped, since they can race with the with the teardown. That means we need to split up the fbdev teardown into the unregister part and the cleanup part. I originally suspected that this was broken in one of the unload shuffles, but on closer inspection the oldest sequence I've dug out also gets this wrong. Just not quite so badly. I've run drv_module_reload a few hundred times and it's rock solid compared to insta-death beforehand. This bug seems to have been uncovered by commit 88be58be886f1215cc73dc8c273c985eecd7385c Author: Daniel Vetter Date: Thu Jul 6 15:00:19 2017 +0200 drm/i915/fbdev: Always forward hotplug events But the effect of that seems to only be to increase the race window enough to make it blow up easier. I'm not exactly clear on what's going on there ... v2: Fix whitespace and use fetch_and_zero (Chris). Testcase: igt/drv_module_reload Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101791 Cc: martin.peres@free.fr Cc: chris@chris-wilson.co.uk Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170714224656.6431-2-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/i915_drv.c | 3 +-- drivers/gpu/drm/i915/intel_display.c | 3 +++ drivers/gpu/drm/i915/intel_drv.h | 9 +++++++-- drivers/gpu/drm/i915/intel_fbdev.c | 22 +++++++++++++++------- 4 files changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 799dd3890cd9..ffeb3a3bed58 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1241,6 +1241,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) */ static void i915_driver_unregister(struct drm_i915_private *dev_priv) { + intel_fbdev_unregister(dev_priv); intel_audio_deinit(dev_priv); intel_gpu_ips_teardown(); @@ -1374,8 +1375,6 @@ void i915_driver_unload(struct drm_device *dev) struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; - intel_fbdev_fini(dev); - if (i915_gem_suspend(dev_priv)) DRM_ERROR("failed to idle hardware; continuing to unload!\n"); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cbdebb022273..560be6e09040 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15796,6 +15796,9 @@ void intel_modeset_cleanup(struct drm_device *dev) */ drm_kms_helper_poll_fini(dev); + /* poll work can call into fbdev, hence clean that up afterwards */ + intel_fbdev_fini(dev_priv); + intel_unregister_dsm_handler(); intel_fbc_global_disable(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 0902d7cb48d9..4f9775a05df7 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1597,7 +1597,8 @@ void intel_hpd_poll_init(struct drm_i915_private *dev_priv); #ifdef CONFIG_DRM_FBDEV_EMULATION extern int intel_fbdev_init(struct drm_device *dev); extern void intel_fbdev_initial_config_async(struct drm_device *dev); -extern void intel_fbdev_fini(struct drm_device *dev); +extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv); +extern void intel_fbdev_fini(struct drm_i915_private *dev_priv); extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); extern void intel_fbdev_output_poll_changed(struct drm_device *dev); extern void intel_fbdev_restore_mode(struct drm_device *dev); @@ -1611,7 +1612,11 @@ static inline void intel_fbdev_initial_config_async(struct drm_device *dev) { } -static inline void intel_fbdev_fini(struct drm_device *dev) +static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) +{ +} + +static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) { } diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index ee1a5b937590..2b7a47c9102a 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -531,8 +531,6 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev) * trying to rectify all the possible error paths leading here. */ - drm_fb_helper_unregister_fbi(&ifbdev->helper); - drm_fb_helper_fini(&ifbdev->helper); if (ifbdev->vma) { @@ -720,8 +718,10 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie) /* Due to peculiar init order wrt to hpd handling this is separate. */ if (drm_fb_helper_initial_config(&ifbdev->helper, - ifbdev->preferred_bpp)) - intel_fbdev_fini(ifbdev->helper.dev); + ifbdev->preferred_bpp)) { + intel_fbdev_unregister(to_i915(ifbdev->helper.dev)); + intel_fbdev_fini(to_i915(ifbdev->helper.dev)); + } } void intel_fbdev_initial_config_async(struct drm_device *dev) @@ -744,9 +744,8 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev) ifbdev->cookie = 0; } -void intel_fbdev_fini(struct drm_device *dev) +void intel_fbdev_unregister(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_fbdev *ifbdev = dev_priv->fbdev; if (!ifbdev) @@ -756,8 +755,17 @@ void intel_fbdev_fini(struct drm_device *dev) if (!current_is_async()) intel_fbdev_sync(ifbdev); + drm_fb_helper_unregister_fbi(&ifbdev->helper); +} + +void intel_fbdev_fini(struct drm_i915_private *dev_priv) +{ + struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev); + + if (!ifbdev) + return; + intel_fbdev_destroy(ifbdev); - dev_priv->fbdev = NULL; } void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) From 99c539bef5385099585335897185a014a8dfe1bf Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sat, 15 Jul 2017 00:46:56 +0200 Subject: [PATCH 012/179] drm/i915: unregister interfaces first in unload We first need to make sure no one else can get at us anymore, before we can proceed to tear down all the datastructures. Just a small step towards eventually the perfect unload code ... Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170714224656.6431-3-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ffeb3a3bed58..f406aec8a499 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1375,6 +1375,8 @@ void i915_driver_unload(struct drm_device *dev) struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; + i915_driver_unregister(dev_priv); + if (i915_gem_suspend(dev_priv)) DRM_ERROR("failed to idle hardware; continuing to unload!\n"); @@ -1384,8 +1386,6 @@ void i915_driver_unload(struct drm_device *dev) intel_gvt_cleanup(dev_priv); - i915_driver_unregister(dev_priv); - drm_vblank_cleanup(dev); intel_modeset_cleanup(dev); From 56d27666f8fa21835724217b0c67d42b769b5723 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 19 Jul 2017 14:59:57 +0100 Subject: [PATCH 013/179] drm/i915/selftests: Mark contexts as lost during freeing of mock device We need to unpin the last retired context early in the shutdown sequence so that its RCU free is done before we try to free the context ida. I included this in a later patch ("drm/i915: Keep a recent cache of freed contexts objects for reuse") and so missed that the selftests were broken in the meantime. Reported-by: Matthew Auld Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101627 Fixes: 5f09a9c8ab6b ("drm/i915: Allow contexts to be unreferenced locklessly") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Cc: Mika Kuoppala Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170719135957.14603-1-chris@chris-wilson.co.uk Tested-by: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index d451dfbe9bbb..dda413c95b89 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -54,6 +54,7 @@ static void mock_device_release(struct drm_device *dev) mutex_lock(&i915->drm.struct_mutex); mock_device_flush(i915); + i915_gem_contexts_lost(i915); mutex_unlock(&i915->drm.struct_mutex); cancel_delayed_work_sync(&i915->gt.retire_work); From 2901215920aa7f984a273104d97ac808a8cbc090 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 19 Jul 2017 10:39:28 -0700 Subject: [PATCH 014/179] drm/i915: Pass enum pipe to intel_set_pch_fifo_underrun_reporting() Commit a21960339c8c ("drm/i915: Consistently use enum pipe for PCH transcoders") misses some pieces, due to a problem with the patch format, this patch adds the remaining bits. Fixes: a21960339c8c ("drm/i915: Consistently use enum pipe for PCH transcoders") Signed-off-by: Matthias Kaehlcke Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170719173928.186638-1-mka@chromium.org --- drivers/gpu/drm/i915/intel_display.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 560be6e09040..5979e4469a0a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5347,8 +5347,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, return; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); @@ -5433,8 +5432,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, intel_wait_for_vblank(dev_priv, pipe); intel_wait_for_vblank(dev_priv, pipe); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } /* If we change the relative order between pipe/planes enabling, we need @@ -5531,8 +5529,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_disable(crtc, old_crtc_state, old_state); @@ -5560,8 +5557,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, intel_encoders_post_disable(crtc, old_crtc_state, old_state); if (old_crtc_state->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } static void i9xx_pfit_enable(struct intel_crtc *crtc) From afa8ce5b3080146940f0fbe3363a139e777c46ac Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 19 Jul 2017 14:54:54 +0200 Subject: [PATCH 015/179] drm/i915: Nuke legacy flip queueing code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Just a very minimal patch to nuke that code. Lots of the flip interrupt handling stuff is still around. Cc: Maarten Lankhorst Cc: Ville Syrjälä Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170719125502.25696-2-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/i915_drv.h | 5 - drivers/gpu/drm/i915/intel_display.c | 656 --------------------------- 2 files changed, 661 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 017361833c58..fea04182362d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -715,11 +715,6 @@ struct drm_i915_display_funcs { void (*fdi_link_train)(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); void (*init_clock_gating)(struct drm_i915_private *dev_priv); - int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags); void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); /* clock updates for mode set */ /* cursor updates */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5979e4469a0a..66a1176156e2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2664,20 +2664,6 @@ out_unref_obj: return false; } -/* Update plane->state->fb to match plane->fb after driver-internal updates */ -static void -update_state_fb(struct drm_plane *plane) -{ - if (plane->fb == plane->state->fb) - return; - - if (plane->state->fb) - drm_framebuffer_unreference(plane->state->fb); - plane->state->fb = plane->fb; - if (plane->state->fb) - drm_framebuffer_reference(plane->state->fb); -} - static void intel_set_plane_visible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state, @@ -10159,35 +10145,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) kfree(intel_crtc); } -static void intel_unpin_work_fn(struct work_struct *__work) -{ - struct intel_flip_work *work = - container_of(__work, struct intel_flip_work, unpin_work); - struct intel_crtc *crtc = to_intel_crtc(work->crtc); - struct drm_device *dev = crtc->base.dev; - struct drm_plane *primary = crtc->base.primary; - - if (is_mmio_work(work)) - flush_work(&work->mmio_work); - - mutex_lock(&dev->struct_mutex); - intel_unpin_fb_vma(work->old_vma); - i915_gem_object_put(work->pending_flip_obj); - mutex_unlock(&dev->struct_mutex); - - i915_gem_request_put(work->flip_queued_req); - - intel_frontbuffer_flip_complete(to_i915(dev), - to_intel_plane(primary)->frontbuffer_bit); - intel_fbc_post_update(crtc); - drm_framebuffer_unreference(work->old_fb); - - BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); - atomic_dec(&crtc->unpin_work_count); - - kfree(work); -} - /* Is 'a' after or equal to 'b'? */ static bool g4x_flip_count_after_eq(u32 a, u32 b) { @@ -10332,346 +10289,6 @@ static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, atomic_set(&work->pending, 1); } -static int intel_gen2_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask, *cs; - - cs = intel_ring_begin(req, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Can't queue multiple flips, so wait for the previous - * one to finish before executing the next. - */ - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - *cs++ = MI_WAIT_FOR_EVENT | flip_mask; - *cs++ = MI_NOOP; - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = 0; /* aux display base address, unused */ - - return 0; -} - -static int intel_gen3_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask, *cs; - - cs = intel_ring_begin(req, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - *cs++ = MI_WAIT_FOR_EVENT | flip_mask; - *cs++ = MI_NOOP; - *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = MI_NOOP; - - return 0; -} - -static int intel_gen4_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 pf, pipesrc, *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* i965+ uses the linear or tiled offsets from the - * Display Registers (which do not change across a page-flip) - * so we need only reprogram the base address. - */ - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset | - intel_fb_modifier_to_tiling(fb->modifier); - - /* XXX Enabling the panel-fitter across page-flip is so far - * untested on non-native modes, so ignore it for now. - * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - *cs++ = pf | pipesrc; - - return 0; -} - -static int intel_gen6_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 pf, pipesrc, *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); - *cs++ = intel_crtc->flip_work->gtt_offset; - - /* Contrary to the suggestions in the documentation, - * "Enable Panel Fitter" does not seem to be required when page - * flipping with a non-native mode, and worse causes a normal - * modeset to fail. - * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - *cs++ = pf | pipesrc; - - return 0; -} - -static int intel_gen7_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 *cs, plane_bit = 0; - int len, ret; - - switch (intel_crtc->plane) { - case PLANE_A: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; - break; - case PLANE_B: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; - break; - case PLANE_C: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; - break; - default: - WARN_ONCE(1, "unknown plane in flip command\n"); - return -ENODEV; - } - - len = 4; - if (req->engine->id == RCS) { - len += 6; - /* - * On Gen 8, SRM is now taking an extra dword to accommodate - * 48bits addresses, and we need a NOOP for the batch size to - * stay even. - */ - if (IS_GEN8(dev_priv)) - len += 2; - } - - /* - * BSpec MI_DISPLAY_FLIP for IVB: - * "The full packet must be contained within the same cache line." - * - * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same - * cacheline, if we ever start emitting more commands before - * the MI_DISPLAY_FLIP we may need to first emit everything else, - * then do the cacheline alignment, and finally emit the - * MI_DISPLAY_FLIP. - */ - ret = intel_ring_cacheline_align(req); - if (ret) - return ret; - - cs = intel_ring_begin(req, len); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Unmask the flip-done completion message. Note that the bspec says that - * we should do this for both the BCS and RCS, and that we must not unmask - * more than one flip event at any time (or ensure that one flip message - * can be sent by waiting for flip-done prior to queueing new flips). - * Experimentation says that BCS works despite DERRMR masking all - * flip-done completion events and that unmasking all planes at once - * for the RCS also doesn't appear to drop events. Setting the DERRMR - * to zero does lead to lockups within MI_DISPLAY_FLIP. - */ - if (req->engine->id == RCS) { - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(DERRMR); - *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | - DERRMR_PIPEB_PRI_FLIP_DONE | - DERRMR_PIPEC_PRI_FLIP_DONE); - if (IS_GEN8(dev_priv)) - *cs++ = MI_STORE_REGISTER_MEM_GEN8 | - MI_SRM_LRM_GLOBAL_GTT; - else - *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; - *cs++ = i915_mmio_reg_offset(DERRMR); - *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; - if (IS_GEN8(dev_priv)) { - *cs++ = 0; - *cs++ = MI_NOOP; - } - } - - *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; - *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = MI_NOOP; - - return 0; -} - -static bool use_mmio_flip(struct intel_engine_cs *engine, - struct drm_i915_gem_object *obj) -{ - /* - * This is not being used for older platforms, because - * non-availability of flip done interrupt forces us to use - * CS flips. Older platforms derive flip done using some clever - * tricks involving the flip_pending status bits and vblank irqs. - * So using MMIO flips there would disrupt this mechanism. - */ - - if (engine == NULL) - return true; - - if (INTEL_GEN(engine->i915) < 5) - return false; - - if (i915.use_mmio_flip < 0) - return false; - else if (i915.use_mmio_flip > 0) - return true; - else if (i915.enable_execlists) - return true; - - return engine != i915_gem_object_last_write_engine(obj); -} - -static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, - unsigned int rotation, - struct intel_flip_work *work) -{ - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - const enum pipe pipe = intel_crtc->pipe; - u32 ctl, stride = skl_plane_stride(fb, 0, rotation); - - ctl = I915_READ(PLANE_CTL(pipe, 0)); - ctl &= ~PLANE_CTL_TILED_MASK; - switch (fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - break; - case I915_FORMAT_MOD_X_TILED: - ctl |= PLANE_CTL_TILED_X; - break; - case I915_FORMAT_MOD_Y_TILED: - ctl |= PLANE_CTL_TILED_Y; - break; - case I915_FORMAT_MOD_Yf_TILED: - ctl |= PLANE_CTL_TILED_YF; - break; - default: - MISSING_CASE(fb->modifier); - } - - /* - * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on - * PLANE_SURF updates, the update is then guaranteed to be atomic. - */ - I915_WRITE(PLANE_CTL(pipe, 0), ctl); - I915_WRITE(PLANE_STRIDE(pipe, 0), stride); - - I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); - POSTING_READ(PLANE_SURF(pipe, 0)); -} - -static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, - struct intel_flip_work *work) -{ - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - i915_reg_t reg = DSPCNTR(intel_crtc->plane); - u32 dspcntr; - - dspcntr = I915_READ(reg); - - if (fb->modifier == I915_FORMAT_MOD_X_TILED) - dspcntr |= DISPPLANE_TILED; - else - dspcntr &= ~DISPPLANE_TILED; - - I915_WRITE(reg, dspcntr); - - I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); - POSTING_READ(DSPSURF(intel_crtc->plane)); -} - -static void intel_mmio_flip_work_func(struct work_struct *w) -{ - struct intel_flip_work *work = - container_of(w, struct intel_flip_work, mmio_work); - struct intel_crtc *crtc = to_intel_crtc(work->crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_framebuffer *intel_fb = - to_intel_framebuffer(crtc->base.primary->fb); - struct drm_i915_gem_object *obj = intel_fb->obj; - - WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); - - intel_pipe_update_start(crtc); - - if (INTEL_GEN(dev_priv) >= 9) - skl_do_mmio_flip(crtc, work->rotation, work); - else - /* use_mmio_flip() retricts MMIO flips to ilk+ */ - ilk_do_mmio_flip(crtc, work); - - intel_pipe_update_end(crtc, work); -} - -static int intel_default_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - return -ENODEV; -} - static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, struct intel_crtc *intel_crtc, struct intel_flip_work *work) @@ -10738,251 +10355,6 @@ void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) spin_unlock(&dev->event_lock); } -__maybe_unused -static int intel_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *old_fb = crtc->primary->fb; - struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_plane *primary = crtc->primary; - enum pipe pipe = intel_crtc->pipe; - struct intel_flip_work *work; - struct intel_engine_cs *engine; - bool mmio_flip; - struct drm_i915_gem_request *request; - struct i915_vma *vma; - int ret; - - /* - * drm_mode_page_flip_ioctl() should already catch this, but double - * check to be safe. In the future we may enable pageflipping from - * a disabled primary plane. - */ - if (WARN_ON(intel_fb_obj(old_fb) == NULL)) - return -EBUSY; - - /* Can't change pixel format via MI display flips. */ - if (fb->format != crtc->primary->fb->format) - return -EINVAL; - - /* - * TILEOFF/LINOFF registers can't be changed via MI display flips. - * Note that pitch changes could also affect these register. - */ - if (INTEL_GEN(dev_priv) > 3 && - (fb->offsets[0] != crtc->primary->fb->offsets[0] || - fb->pitches[0] != crtc->primary->fb->pitches[0])) - return -EINVAL; - - if (i915_terminally_wedged(&dev_priv->gpu_error)) - goto out_hang; - - work = kzalloc(sizeof(*work), GFP_KERNEL); - if (work == NULL) - return -ENOMEM; - - work->event = event; - work->crtc = crtc; - work->old_fb = old_fb; - INIT_WORK(&work->unpin_work, intel_unpin_work_fn); - - ret = drm_crtc_vblank_get(crtc); - if (ret) - goto free_work; - - /* We borrow the event spin lock for protecting flip_work */ - spin_lock_irq(&dev->event_lock); - if (intel_crtc->flip_work) { - /* Before declaring the flip queue wedged, check if - * the hardware completed the operation behind our backs. - */ - if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { - DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); - page_flip_completed(intel_crtc); - } else { - DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); - spin_unlock_irq(&dev->event_lock); - - drm_crtc_vblank_put(crtc); - kfree(work); - return -EBUSY; - } - } - intel_crtc->flip_work = work; - spin_unlock_irq(&dev->event_lock); - - if (atomic_read(&intel_crtc->unpin_work_count) >= 2) - flush_workqueue(dev_priv->wq); - - /* Reference the objects for the scheduled work. */ - drm_framebuffer_reference(work->old_fb); - - crtc->primary->fb = fb; - update_state_fb(crtc->primary); - - work->pending_flip_obj = i915_gem_object_get(obj); - - ret = i915_mutex_lock_interruptible(dev); - if (ret) - goto cleanup; - - intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); - if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) { - ret = -EIO; - goto unlock; - } - - atomic_inc(&intel_crtc->unpin_work_count); - - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) - work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; - - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - engine = dev_priv->engine[BCS]; - if (fb->modifier != old_fb->modifier) - /* vlv: DISPLAY_FLIP fails to change tiling */ - engine = NULL; - } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { - engine = dev_priv->engine[BCS]; - } else if (INTEL_GEN(dev_priv) >= 7) { - engine = i915_gem_object_last_write_engine(obj); - if (engine == NULL || engine->id != RCS) - engine = dev_priv->engine[BCS]; - } else { - engine = dev_priv->engine[RCS]; - } - - mmio_flip = use_mmio_flip(engine, obj); - - vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto cleanup_pending; - } - - work->old_vma = to_intel_plane_state(primary->state)->vma; - to_intel_plane_state(primary->state)->vma = vma; - - work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; - work->rotation = crtc->primary->state->rotation; - - /* - * There's the potential that the next frame will not be compatible with - * FBC, so we want to call pre_update() before the actual page flip. - * The problem is that pre_update() caches some information about the fb - * object, so we want to do this only after the object is pinned. Let's - * be on the safe side and do this immediately before scheduling the - * flip. - */ - intel_fbc_pre_update(intel_crtc, intel_crtc->config, - to_intel_plane_state(primary->state)); - - if (mmio_flip) { - INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); - queue_work(system_unbound_wq, &work->mmio_work); - } else { - request = i915_gem_request_alloc(engine, - dev_priv->kernel_context); - if (IS_ERR(request)) { - ret = PTR_ERR(request); - goto cleanup_unpin; - } - - ret = i915_gem_request_await_object(request, obj, false); - if (ret) - goto cleanup_request; - - ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, - page_flip_flags); - if (ret) - goto cleanup_request; - - intel_mark_page_flip_active(intel_crtc, work); - - work->flip_queued_req = i915_gem_request_get(request); - i915_add_request(request); - } - - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); - i915_gem_track_fb(intel_fb_obj(old_fb), obj, - to_intel_plane(primary)->frontbuffer_bit); - mutex_unlock(&dev->struct_mutex); - - intel_frontbuffer_flip_prepare(to_i915(dev), - to_intel_plane(primary)->frontbuffer_bit); - - trace_i915_flip_request(intel_crtc->plane, obj); - - return 0; - -cleanup_request: - i915_add_request(request); -cleanup_unpin: - to_intel_plane_state(primary->state)->vma = work->old_vma; - intel_unpin_fb_vma(vma); -cleanup_pending: - atomic_dec(&intel_crtc->unpin_work_count); -unlock: - mutex_unlock(&dev->struct_mutex); -cleanup: - crtc->primary->fb = old_fb; - update_state_fb(crtc->primary); - - i915_gem_object_put(obj); - drm_framebuffer_unreference(work->old_fb); - - spin_lock_irq(&dev->event_lock); - intel_crtc->flip_work = NULL; - spin_unlock_irq(&dev->event_lock); - - drm_crtc_vblank_put(crtc); -free_work: - kfree(work); - - if (ret == -EIO) { - struct drm_atomic_state *state; - struct drm_plane_state *plane_state; - -out_hang: - state = drm_atomic_state_alloc(dev); - if (!state) - return -ENOMEM; - state->acquire_ctx = dev->mode_config.acquire_ctx; - -retry: - plane_state = drm_atomic_get_plane_state(state, primary); - ret = PTR_ERR_OR_ZERO(plane_state); - if (!ret) { - drm_atomic_set_fb_for_plane(plane_state, fb); - - ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); - if (!ret) - ret = drm_atomic_commit(state); - } - - if (ret == -EDEADLK) { - drm_modeset_backoff(state->acquire_ctx); - drm_atomic_state_clear(state); - goto retry; - } - - drm_atomic_state_put(state); - - if (ret == 0 && event) { - spin_lock_irq(&dev->event_lock); - drm_crtc_send_vblank_event(crtc, event); - spin_unlock_irq(&dev->event_lock); - } - } - return ret; -} - - /** * intel_wm_need_update - Check whether watermarks need updating * @plane: drm plane @@ -14727,34 +14099,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.update_crtcs = skl_update_crtcs; else dev_priv->display.update_crtcs = intel_update_crtcs; - - switch (INTEL_INFO(dev_priv)->gen) { - case 2: - dev_priv->display.queue_flip = intel_gen2_queue_flip; - break; - - case 3: - dev_priv->display.queue_flip = intel_gen3_queue_flip; - break; - - case 4: - case 5: - dev_priv->display.queue_flip = intel_gen4_queue_flip; - break; - - case 6: - dev_priv->display.queue_flip = intel_gen6_queue_flip; - break; - case 7: - case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ - dev_priv->display.queue_flip = intel_gen7_queue_flip; - break; - case 9: - /* Drop through - unsupported since execlist only. */ - default: - /* Default just returns -ENODEV to indicate unsupported */ - dev_priv->display.queue_flip = intel_default_queue_flip; - } } /* From ce87ea15ebc60a9f8f156b2549f7b2cf7fe48d04 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 19 Jul 2017 14:54:55 +0200 Subject: [PATCH 016/179] drm/i915: Unbreak gpu reset vs. modeset locking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Taking the modeset locks unconditionally isn't the greatest idea, because atm that part is still broken and times out (and then atomic keels over). And there's really no reason to do so, the old code didn't do that either. To make the patch a bit simpler let's also nuke 2 cases that are only around for the old mmioflip paths. Atomic nonblocking workers will not die (minus bugs) when a gpu reset happens. And of course this doesn't fix any of the gpu reset vs. modeset deadlock fun, but it at least stop modern CI machines from keeling over all over the place for no reason at all. And we still have the explicit testcases to run the fake gpu reset, so coverage isn't that much worse. v2: Split out additional changes on top, restrict this to purely reducing the critical section of modeset locks. v2: Review from Maarten - update comments - don't oops when state is NULL in intel_finish_reset, but try to at least still drop locks properly. The hw is going to be toast anyway. Fixes: 739748939974 ("drm/i915: Fix modeset handling during gpu reset, v5.") Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst Cc: Ville Syrjälä Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170719125502.25696-3-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_display.c | 60 +++++++++------------------- 1 file changed, 18 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 66a1176156e2..928af814e151 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3413,26 +3413,6 @@ static void intel_complete_page_flips(struct drm_i915_private *dev_priv) intel_finish_page_flip_cs(dev_priv, crtc->pipe); } -static void intel_update_primary_planes(struct drm_device *dev) -{ - struct drm_crtc *crtc; - - for_each_crtc(dev, crtc) { - struct intel_plane *plane = to_intel_plane(crtc->primary); - struct intel_plane_state *plane_state = - to_intel_plane_state(plane->base.state); - - if (plane_state->base.visible) { - trace_intel_update_plane(&plane->base, - to_intel_crtc(crtc)); - - plane->update_plane(plane, - to_intel_crtc_state(crtc->state), - plane_state); - } - } -} - static int __intel_display_resume(struct drm_device *dev, struct drm_atomic_state *state, @@ -3485,6 +3465,12 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) struct drm_atomic_state *state; int ret; + + /* reset doesn't touch the display */ + if (!i915.force_reset_modeset_test && + !gpu_reset_clobbers_display(dev_priv)) + return; + /* * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. @@ -3498,12 +3484,6 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) drm_modeset_backoff(ctx); } - - /* reset doesn't touch the display, but flips might get nuked anyway, */ - if (!i915.force_reset_modeset_test && - !gpu_reset_clobbers_display(dev_priv)) - return; - /* * Disabling the crtcs gracefully seems nicer. Also the * g33 docs say we should at least disable all the planes. @@ -3533,6 +3513,14 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) struct drm_atomic_state *state = dev_priv->modeset_restore_state; int ret; + /* reset doesn't touch the display */ + if (!i915.force_reset_modeset_test && + !gpu_reset_clobbers_display(dev_priv)) + return; + + if (!state) + goto unlock; + /* * Flips in the rings will be nuked by the reset, * so complete all pending flips so that user space @@ -3544,22 +3532,10 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) /* reset doesn't touch the display */ if (!gpu_reset_clobbers_display(dev_priv)) { - if (!state) { - /* - * Flips in the rings have been nuked by the reset, - * so update the base address of all primary - * planes to the the last fb to make sure we're - * showing the correct fb after a reset. - * - * FIXME: Atomic will make this obsolete since we won't schedule - * CS-based flips (which might get lost in gpu resets) any more. - */ - intel_update_primary_planes(dev); - } else { - ret = __intel_display_resume(dev, state, ctx); + /* for testing only restore the display */ + ret = __intel_display_resume(dev, state, ctx); if (ret) DRM_ERROR("Restoring old state failed with %i\n", ret); - } } else { /* * The display has been reset as well, @@ -3583,8 +3559,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) intel_hpd_init(dev_priv); } - if (state) - drm_atomic_state_put(state); + drm_atomic_state_put(state); +unlock: drm_modeset_drop_locks(ctx); drm_modeset_acquire_fini(ctx); mutex_unlock(&dev->mode_config.mutex); From bca2bf2a8f1dc32050fab1934d6490106e498dd6 Mon Sep 17 00:00:00 2001 From: "Pandiyan, Dhinakaran" Date: Tue, 18 Jul 2017 11:28:00 -0700 Subject: [PATCH 017/179] drm/i915: s/INTEL_INFO(dev_priv)->gen/INTEL_GEN(dev_priv) in i915_irq INTEL_GEN() appears to be the new way of doing these platform checks, so convert this i915_irq.c too. Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Chris Wilson Signed-off-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/1500402480-30741-1-git-send-email-dhinakaran.pandiyan@intel.com --- drivers/gpu/drm/i915/i915_irq.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0b6f310101ee..d228857ccb19 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -275,17 +275,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; } static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; } static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; } /** @@ -1661,7 +1661,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) spin_unlock(&dev_priv->irq_lock); } - if (INTEL_INFO(dev_priv)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) return; if (HAS_VEBOX(dev_priv)) { @@ -2440,7 +2440,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; tmp_mask = GEN8_AUX_CHANNEL_A; - if (INTEL_INFO(dev_priv)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) tmp_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; @@ -2498,7 +2498,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) intel_check_page_flip(dev_priv, pipe); flip_done = iir; - if (INTEL_INFO(dev_priv)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; else flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; @@ -2513,7 +2513,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); fault_errors = iir; - if (INTEL_INFO(dev_priv)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; else fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; @@ -3492,7 +3492,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_misc_masked = GEN8_DE_MISC_GSE; enum pipe pipe; - if (INTEL_INFO(dev_priv)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | @@ -4290,16 +4290,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv) * * TODO: verify if this can be reproduced on VLV,CHV. */ - if (INTEL_INFO(dev_priv)->gen <= 7) + if (INTEL_GEN(dev_priv) <= 7) dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; - if (INTEL_INFO(dev_priv)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; if (IS_GEN2(dev_priv)) { /* Gen2 doesn't have a hardware frame counter */ dev->max_vblank_count = 0; - } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { + } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ dev->driver->get_vblank_counter = g4x_get_vblank_counter; } else { @@ -4346,7 +4346,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->enable_vblank = i965_enable_vblank; dev->driver->disable_vblank = i965_disable_vblank; dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; - } else if (INTEL_INFO(dev_priv)->gen >= 8) { + } else if (INTEL_GEN(dev_priv) >= 8) { dev->driver->irq_handler = gen8_irq_handler; dev->driver->irq_preinstall = gen8_irq_reset; dev->driver->irq_postinstall = gen8_irq_postinstall; From a5ec7fe81a6ec38cb8b8a798d0552cbcadce7aa9 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Thu, 20 Jul 2017 00:35:03 +0200 Subject: [PATCH 018/179] drm/i915/selftests: Fix an error handling path in 'mock_gem_device()' Goto the right label in case of error, otherwise there is a leak. This has been introduced by c5cf9a9147ff. In this patch a goto has not been updated. Fixes: c5cf9a9147ff ("drm/i915: Create a kmem_cache to allocate struct i915_priolist from") Signed-off-by: Christophe JAILLET Link: https://patchwork.freedesktop.org/patch/msgid/20170719223503.30580-1-christophe.jaillet@wanadoo.fr Reviewed-by: Tvrtko Ursulin Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index dda413c95b89..ec92b6569b50 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -228,7 +228,7 @@ struct drm_i915_private *mock_gem_device(void) mkwrite_device_info(i915)->ring_mask = BIT(0); i915->engine[RCS] = mock_engine(i915, "mock"); if (!i915->engine[RCS]) - goto err_dependencies; + goto err_priorities; i915->kernel_context = mock_context(i915, NULL); if (!i915->kernel_context) From fd3a40242e8766ae342fa9fe77d44ae7c8139b45 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 20 Jul 2017 19:57:51 +0200 Subject: [PATCH 019/179] drm/i915: Rip out legacy page_flip completion/irq handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All these races and things are now solved through the vblank evasion trick, plus event handling is done using normal vblank even processing and drm_crtc_arm_vblank_event. We can get rid of all this complexity. Cc: Maarten Lankhorst Cc: Ville Syrjälä Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170720175754.30751-5-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/i915_irq.c | 151 +++---------------- drivers/gpu/drm/i915/intel_display.c | 215 --------------------------- drivers/gpu/drm/i915/intel_drv.h | 3 - 3 files changed, 22 insertions(+), 347 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d228857ccb19..fed2894eeaf0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1708,18 +1708,6 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) } } -static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, - enum pipe pipe) -{ - bool ret; - - ret = drm_handle_vblank(&dev_priv->drm, pipe); - if (ret) - intel_finish_page_flip_mmio(dev_priv, pipe); - - return ret; -} - static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, u32 iir, u32 pipe_stats[I915_MAX_PIPES]) { @@ -1784,12 +1772,8 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe; for_each_pipe(dev_priv, pipe) { - if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) - intel_finish_page_flip_cs(dev_priv, pipe); + if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -2241,19 +2225,14 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, DRM_ERROR("Poison interrupt\n"); for_each_pipe(dev_priv, pipe) { - if (de_iir & DE_PIPE_VBLANK(pipe) && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); + if (de_iir & DE_PIPE_VBLANK(pipe)) + drm_handle_vblank(&dev_priv->drm, pipe); if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); if (de_iir & DE_PIPE_CRC_DONE(pipe)) i9xx_pipe_crc_irq_handler(dev_priv, pipe); - - /* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE(pipe)) - intel_finish_page_flip_cs(dev_priv, pipe); } /* check event from PCH */ @@ -2292,13 +2271,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, intel_opregion_asle_intr(dev_priv); for_each_pipe(dev_priv, pipe) { - if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - /* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) - intel_finish_page_flip_cs(dev_priv, pipe); + if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) + drm_handle_vblank(&dev_priv->drm, pipe); } /* check event from PCH */ @@ -2479,7 +2453,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } for_each_pipe(dev_priv, pipe) { - u32 flip_done, fault_errors; + u32 fault_errors; if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) continue; @@ -2493,18 +2467,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); - if (iir & GEN8_PIPE_VBLANK && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - flip_done = iir; - if (INTEL_GEN(dev_priv) >= 9) - flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; - else - flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; - - if (flip_done) - intel_finish_page_flip_cs(dev_priv, pipe); + if (iir & GEN8_PIPE_VBLANK) + drm_handle_vblank(&dev_priv->drm, pipe); if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); @@ -3675,34 +3639,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev) /* * Returns true when a page flip has completed. */ -static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, - int plane, int pipe, u32 iir) -{ - u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); - - if (!intel_pipe_handle_vblank(dev_priv, pipe)) - return false; - - if ((iir & flip_pending) == 0) - goto check_page_flip; - - /* We detect FlipDone by looking for the change in PendingFlip from '1' - * to '0' on the following vblank, i.e. IIR has the Pendingflip - * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence - * the flip is completed (no longer pending). Since this doesn't raise - * an interrupt per se, we watch for the change at vblank. - */ - if (I915_READ16(ISR) & flip_pending) - goto check_page_flip; - - intel_finish_page_flip_cs(dev_priv, pipe); - return true; - -check_page_flip: - intel_check_page_flip(dev_priv, pipe); - return false; -} - static irqreturn_t i8xx_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; @@ -3710,9 +3646,6 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) u16 iir, new_iir; u32 pipe_stats[2]; int pipe; - u16 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; irqreturn_t ret; if (!intel_irqs_enabled(dev_priv)) @@ -3726,7 +3659,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) if (iir == 0) goto out; - while (iir & ~flip_mask) { + while (iir) { /* Can't rely on pipestat interrupt bit in iir as it might * have been cleared after the pipestat interrupt was received. * It doesn't set the bit in iir again, but it still produces @@ -3748,7 +3681,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) } spin_unlock(&dev_priv->irq_lock); - I915_WRITE16(IIR, iir & ~flip_mask); + I915_WRITE16(IIR, iir); new_iir = I915_READ16(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -3759,9 +3692,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) if (HAS_FBC(dev_priv)) plane = !plane; - if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && - i8xx_handle_vblank(dev_priv, plane, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); + if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -3861,45 +3793,11 @@ static int i915_irq_postinstall(struct drm_device *dev) return 0; } -/* - * Returns true when a page flip has completed. - */ -static bool i915_handle_vblank(struct drm_i915_private *dev_priv, - int plane, int pipe, u32 iir) -{ - u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); - - if (!intel_pipe_handle_vblank(dev_priv, pipe)) - return false; - - if ((iir & flip_pending) == 0) - goto check_page_flip; - - /* We detect FlipDone by looking for the change in PendingFlip from '1' - * to '0' on the following vblank, i.e. IIR has the Pendingflip - * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence - * the flip is completed (no longer pending). Since this doesn't raise - * an interrupt per se, we watch for the change at vblank. - */ - if (I915_READ(ISR) & flip_pending) - goto check_page_flip; - - intel_finish_page_flip_cs(dev_priv, pipe); - return true; - -check_page_flip: - intel_check_page_flip(dev_priv, pipe); - return false; -} - static irqreturn_t i915_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; struct drm_i915_private *dev_priv = to_i915(dev); u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; - u32 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; int pipe, ret = IRQ_NONE; if (!intel_irqs_enabled(dev_priv)) @@ -3910,7 +3808,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) iir = I915_READ(IIR); do { - bool irq_received = (iir & ~flip_mask) != 0; + bool irq_received = (iir) != 0; bool blc_event = false; /* Can't rely on pipestat interrupt bit in iir as it might @@ -3945,7 +3843,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) i9xx_hpd_irq_handler(dev_priv, hotplug_status); } - I915_WRITE(IIR, iir & ~flip_mask); + I915_WRITE(IIR, iir); new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -3956,9 +3854,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) if (HAS_FBC(dev_priv)) plane = !plane; - if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && - i915_handle_vblank(dev_priv, plane, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); + if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; @@ -3991,7 +3888,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) */ ret = IRQ_HANDLED; iir = new_iir; - } while (iir & ~flip_mask); + } while (iir); enable_rpm_wakeref_asserts(dev_priv); @@ -4126,9 +4023,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) u32 iir, new_iir; u32 pipe_stats[I915_MAX_PIPES]; int ret = IRQ_NONE, pipe; - u32 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; if (!intel_irqs_enabled(dev_priv)) return IRQ_NONE; @@ -4139,7 +4033,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) iir = I915_READ(IIR); for (;;) { - bool irq_received = (iir & ~flip_mask) != 0; + bool irq_received = (iir) != 0; bool blc_event = false; /* Can't rely on pipestat interrupt bit in iir as it might @@ -4177,7 +4071,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) i9xx_hpd_irq_handler(dev_priv, hotplug_status); } - I915_WRITE(IIR, iir & ~flip_mask); + I915_WRITE(IIR, iir); new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -4186,9 +4080,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) notify_ring(dev_priv->engine[VCS]); for_each_pipe(dev_priv, pipe) { - if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && - i915_handle_vblank(dev_priv, pipe, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); + if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 928af814e151..0d8cf76b5099 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3405,14 +3405,6 @@ static void skylake_disable_primary_plane(struct intel_plane *primary, spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -static void intel_complete_page_flips(struct drm_i915_private *dev_priv) -{ - struct intel_crtc *crtc; - - for_each_intel_crtc(&dev_priv->drm, crtc) - intel_finish_page_flip_cs(dev_priv, crtc->pipe); -} - static int __intel_display_resume(struct drm_device *dev, struct drm_atomic_state *state, @@ -3521,13 +3513,6 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) if (!state) goto unlock; - /* - * Flips in the rings will be nuked by the reset, - * so complete all pending flips so that user space - * will get its events and not get stuck. - */ - intel_complete_page_flips(dev_priv); - dev_priv->modeset_restore_state = NULL; /* reset doesn't touch the display */ @@ -10121,140 +10106,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) kfree(intel_crtc); } -/* Is 'a' after or equal to 'b'? */ -static bool g4x_flip_count_after_eq(u32 a, u32 b) -{ - return !((a - b) & 0x80000000); -} - -static bool __pageflip_finished_cs(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - - if (abort_flip_on_reset(crtc)) - return true; - - /* - * The relevant registers doen't exist on pre-ctg. - * As the flip done interrupt doesn't trigger for mmio - * flips on gmch platforms, a flip count check isn't - * really needed there. But since ctg has the registers, - * include it in the check anyway. - */ - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) - return true; - - /* - * BDW signals flip done immediately if the plane - * is disabled, even if the plane enable is already - * armed to occur at the next vblank :( - */ - - /* - * A DSPSURFLIVE check isn't enough in case the mmio and CS flips - * used the same base address. In that case the mmio flip might - * have completed, but the CS hasn't even executed the flip yet. - * - * A flip count check isn't enough as the CS might have updated - * the base address just after start of vblank, but before we - * managed to process the interrupt. This means we'd complete the - * CS flip too soon. - * - * Combining both checks should get us a good enough result. It may - * still happen that the CS flip has been executed, but has not - * yet actually completed. But in case the base address is the same - * anyway, we don't really care. - */ - return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == - crtc->flip_work->gtt_offset && - g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), - crtc->flip_work->flip_count); -} - -static bool -__pageflip_finished_mmio(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - /* - * MMIO work completes when vblank is different from - * flip_queued_vblank. - * - * Reset counter value doesn't matter, this is handled by - * i915_wait_request finishing early, so no need to handle - * reset here. - */ - return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; -} - - -static bool pageflip_finished(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - if (!atomic_read(&work->pending)) - return false; - - smp_rmb(); - - if (is_mmio_work(work)) - return __pageflip_finished_mmio(crtc, work); - else - return __pageflip_finished_cs(crtc, work); -} - -void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - unsigned long flags; - - /* Ignore early vblank irqs */ - if (!crtc) - return; - - /* - * This is called both by irq handlers and the reset code (to complete - * lost pageflips) so needs the full irqsave spinlocks. - */ - spin_lock_irqsave(&dev->event_lock, flags); - work = crtc->flip_work; - - if (work != NULL && - !is_mmio_work(work) && - pageflip_finished(crtc, work)) - page_flip_completed(crtc); - - spin_unlock_irqrestore(&dev->event_lock, flags); -} - -void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - unsigned long flags; - - /* Ignore early vblank irqs */ - if (!crtc) - return; - - /* - * This is called both by irq handlers and the reset code (to complete - * lost pageflips) so needs the full irqsave spinlocks. - */ - spin_lock_irqsave(&dev->event_lock, flags); - work = crtc->flip_work; - - if (work != NULL && - is_mmio_work(work) && - pageflip_finished(crtc, work)) - page_flip_completed(crtc); - - spin_unlock_irqrestore(&dev->event_lock, flags); -} - static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, struct intel_flip_work *work) { @@ -10265,72 +10116,6 @@ static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, atomic_set(&work->pending, 1); } -static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, - struct intel_crtc *intel_crtc, - struct intel_flip_work *work) -{ - u32 addr, vblank; - - if (!atomic_read(&work->pending)) - return false; - - smp_rmb(); - - vblank = intel_crtc_get_vblank_counter(intel_crtc); - if (work->flip_ready_vblank == 0) { - if (work->flip_queued_req && - !i915_gem_request_completed(work->flip_queued_req)) - return false; - - work->flip_ready_vblank = vblank; - } - - if (vblank - work->flip_ready_vblank < 3) - return false; - - /* Potential stall - if we see that the flip has happened, - * assume a missed interrupt. */ - if (INTEL_GEN(dev_priv) >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); - else - addr = I915_READ(DSPADDR(intel_crtc->plane)); - - /* There is a potential issue here with a false positive after a flip - * to the same address. We could address this by checking for a - * non-incrementing frame counter. - */ - return addr == work->gtt_offset; -} - -void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - - WARN_ON(!in_interrupt()); - - if (crtc == NULL) - return; - - spin_lock(&dev->event_lock); - work = crtc->flip_work; - - if (work != NULL && !is_mmio_work(work) && - __pageflip_stall_check_cs(dev_priv, crtc, work)) { - WARN_ONCE(1, - "Kicking stuck page flip: queued at %d, now %d\n", - work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); - page_flip_completed(crtc); - work = NULL; - } - - if (work != NULL && !is_mmio_work(work) && - intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) - intel_queue_rps_boost_for_request(work->flip_queued_req); - spin_unlock(&dev->event_lock); -} - /** * intel_wm_need_update - Check whether watermarks need updating * @plane: drm plane diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4f9775a05df7..4b7766efae7b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1408,9 +1408,6 @@ void intel_unpin_fb_vma(struct i915_vma *vma); struct drm_framebuffer * intel_framebuffer_create(struct drm_i915_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd); -void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe); -void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe); -void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe); int intel_prepare_plane_fb(struct drm_plane *plane, struct drm_plane_state *new_state); void intel_cleanup_plane_fb(struct drm_plane *plane, From fa05887a8906a674ebd3c10ba22d5328ba6038af Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 20 Jul 2017 19:57:52 +0200 Subject: [PATCH 020/179] drm/i915: adjust has_pending_fb_unpin to atomic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A bit an oversight - the current code did nothing, since only legacy flips used the unpin_work_count and assorted logic. Cc: Maarten Lankhorst Cc: Ville Syrjälä Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170720175754.30751-6-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0d8cf76b5099..e144e6fec76e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4134,21 +4134,22 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) { - struct intel_crtc *crtc; + struct drm_crtc *crtc; + bool cleanup_done; - /* Note that we don't need to be called with mode_config.lock here - * as our list of CRTC objects is static for the lifetime of the - * device and so cannot disappear as we iterate. Similarly, we can - * happily treat the predicates as racy, atomic checks as userspace - * cannot claim and pin a new fb without at least acquring the - * struct_mutex and so serialising with us. - */ - for_each_intel_crtc(&dev_priv->drm, crtc) { - if (atomic_read(&crtc->unpin_work_count) == 0) + drm_for_each_crtc(crtc, &dev_priv->drm) { + struct drm_crtc_commit *commit; + spin_lock(&crtc->commit_lock); + commit = list_first_entry_or_null(&crtc->commit_list, + struct drm_crtc_commit, commit_entry); + cleanup_done = commit ? + try_wait_for_completion(&commit->cleanup_done) : true; + spin_unlock(&crtc->commit_lock); + + if (cleanup_done) continue; - if (crtc->flip_work) - intel_wait_for_vblank(dev_priv, crtc->pipe); + drm_crtc_wait_one_vblank(crtc); return true; } From 8b5d27b911d741054c65fb57f0d794a283308577 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 20 Jul 2017 19:57:53 +0200 Subject: [PATCH 021/179] drm/i915: Remove intel_flip_work infrastructure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This gets rid of all the interactions between the legacy flip code and the modeset code. Yay! This highlights an ommission in the atomic paths, where we fail to apply a boost to the pending rendering when we miss the target vblank. But the existing code is still dead and can be removed. v2: Note that the boosting doesn't work in atomic (Chris). Cc: Maarten Lankhorst Cc: Ville Syrjälä Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170720175754.30751-7-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/i915_debugfs.c | 70 ---------------- drivers/gpu/drm/i915/i915_drv.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 4 - drivers/gpu/drm/i915/i915_gem.c | 2 - drivers/gpu/drm/i915/intel_display.c | 117 +-------------------------- drivers/gpu/drm/i915/intel_drv.h | 21 +---- drivers/gpu/drm/i915/intel_sprite.c | 8 +- 7 files changed, 3 insertions(+), 220 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2ef75c1a6119..c25f42c60d61 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -543,75 +543,6 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data) return 0; } -static int i915_gem_pageflip_info(struct seq_file *m, void *data) -{ - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc; - int ret; - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - for_each_intel_crtc(dev, crtc) { - const char pipe = pipe_name(crtc->pipe); - const char plane = plane_name(crtc->plane); - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = crtc->flip_work; - if (work == NULL) { - seq_printf(m, "No flip due on pipe %c (plane %c)\n", - pipe, plane); - } else { - u32 pending; - u32 addr; - - pending = atomic_read(&work->pending); - if (pending) { - seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", - pipe, plane); - } else { - seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", - pipe, plane); - } - if (work->flip_queued_req) { - struct intel_engine_cs *engine = work->flip_queued_req->engine; - - seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", - engine->name, - work->flip_queued_req->global_seqno, - intel_engine_last_submit(engine), - intel_engine_get_seqno(engine), - i915_gem_request_completed(work->flip_queued_req)); - } else - seq_printf(m, "Flip not associated with any ring\n"); - seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", - work->flip_queued_vblank, - work->flip_ready_vblank, - intel_crtc_get_vblank_counter(crtc)); - seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); - - if (INTEL_GEN(dev_priv) >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); - else - addr = I915_READ(DSPADDR(crtc->plane)); - seq_printf(m, "Current scanout address 0x%08x\n", addr); - - if (work->pending_flip_obj) { - seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); - seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); - } - } - spin_unlock_irq(&dev->event_lock); - } - - mutex_unlock(&dev->struct_mutex); - - return 0; -} - static int i915_gem_batch_pool_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -4854,7 +4785,6 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_gem_gtt", i915_gem_gtt_info, 0}, {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, {"i915_gem_stolen", i915_gem_stolen_list_info }, - {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, {"i915_gem_request", i915_gem_request_info, 0}, {"i915_gem_seqno", i915_gem_seqno_info, 0}, {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index f406aec8a499..5a21a6fcc90d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -876,7 +876,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, spin_lock_init(&dev_priv->uncore.lock); spin_lock_init(&dev_priv->mm.object_stat_lock); - spin_lock_init(&dev_priv->mmio_flip_lock); mutex_init(&dev_priv->sb_lock); mutex_init(&dev_priv->modeset_restore_lock); mutex_init(&dev_priv->av_mutex); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fea04182362d..0e84346115dd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2143,9 +2143,6 @@ struct drm_i915_private { /* protects the irq masks */ spinlock_t irq_lock; - /* protects the mmio flip data */ - spinlock_t mmio_flip_lock; - bool display_irqs_enabled; /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ @@ -2250,7 +2247,6 @@ struct drm_i915_private { struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; - wait_queue_head_t pending_flip_queue; #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1b2dfa8bdeef..59715e9f2cc4 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4935,8 +4935,6 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) init_waitqueue_head(&dev_priv->gpu_error.wait_queue); init_waitqueue_head(&dev_priv->gpu_error.reset_queue); - init_waitqueue_head(&dev_priv->pending_flip_queue); - atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); spin_lock_init(&dev_priv->fb_tracking.lock); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e144e6fec76e..56bf9009ea15 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -49,11 +49,6 @@ #include #include -static bool is_mmio_work(struct intel_flip_work *work) -{ - return work->mmio_work.func; -} - /* Primary plane formats for gen <= 3 */ static const uint32_t i8xx_primary_formats[] = { DRM_FORMAT_C8, @@ -3551,35 +3546,6 @@ unlock: mutex_unlock(&dev->mode_config.mutex); } -static bool abort_flip_on_reset(struct intel_crtc *crtc) -{ - struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; - - if (i915_reset_backoff(error)) - return true; - - if (crtc->reset_count != i915_reset_count(error)) - return true; - - return false; -} - -static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - bool pending; - - if (abort_flip_on_reset(intel_crtc)) - return false; - - spin_lock_irq(&dev->event_lock); - pending = to_intel_crtc(crtc)->flip_work != NULL; - spin_unlock_irq(&dev->event_lock); - - return pending; -} - static void intel_update_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *old_crtc_state) { @@ -4157,57 +4123,6 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) return false; } -static void page_flip_completed(struct intel_crtc *intel_crtc) -{ - struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - struct intel_flip_work *work = intel_crtc->flip_work; - - intel_crtc->flip_work = NULL; - - if (work->event) - drm_crtc_send_vblank_event(&intel_crtc->base, work->event); - - drm_crtc_vblank_put(&intel_crtc->base); - - wake_up_all(&dev_priv->pending_flip_queue); - trace_i915_flip_complete(intel_crtc->plane, - work->pending_flip_obj); - - queue_work(dev_priv->wq, &work->unpin_work); -} - -static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - long ret; - - WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); - - ret = wait_event_interruptible_timeout( - dev_priv->pending_flip_queue, - !intel_crtc_has_pending_flip(crtc), - 60*HZ); - - if (ret < 0) - return ret; - - if (ret == 0) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = intel_crtc->flip_work; - if (work && !is_mmio_work(work)) { - WARN_ONCE(1, "Removing stuck page flip\n"); - page_flip_completed(intel_crtc); - } - spin_unlock_irq(&dev->event_lock); - } - - return 0; -} - void lpt_disable_iclkip(struct drm_i915_private *dev_priv) { u32 temp; @@ -5814,8 +5729,6 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, return; if (crtc->primary->state->visible) { - WARN_ON(intel_crtc->flip_work); - intel_pre_disable_primary_noatomic(crtc); intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); @@ -10088,35 +10001,11 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = intel_crtc->flip_work; - intel_crtc->flip_work = NULL; - spin_unlock_irq(&dev->event_lock); - - if (work) { - cancel_work_sync(&work->mmio_work); - cancel_work_sync(&work->unpin_work); - kfree(work); - } drm_crtc_cleanup(crtc); - kfree(intel_crtc); } -static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); - - /* Ensure that the work item is consistent when activating it ... */ - smp_mb__before_atomic(); - atomic_set(&work->pending, 1); -} - /** * intel_wm_need_update - Check whether watermarks need updating * @plane: drm plane @@ -11935,10 +11824,6 @@ static int intel_atomic_prepare_commit(struct drm_device *dev, if (state->legacy_cursor_update) continue; - ret = intel_crtc_wait_for_pending_flips(crtc); - if (ret) - return ret; - if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) flush_workqueue(dev_priv->wq); } @@ -12712,7 +12597,7 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc, { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - intel_pipe_update_end(intel_crtc, NULL); + intel_pipe_update_end(intel_crtc); } /** diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4b7766efae7b..79009b759056 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -797,7 +797,6 @@ struct intel_crtc { u8 plane_ids_mask; unsigned long long enabled_power_domains; struct intel_overlay *overlay; - struct intel_flip_work *flip_work; atomic_t unpin_work_count; @@ -1132,24 +1131,6 @@ intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane) return dev_priv->plane_to_crtc_mapping[plane]; } -struct intel_flip_work { - struct work_struct unpin_work; - struct work_struct mmio_work; - - struct drm_crtc *crtc; - struct i915_vma *old_vma; - struct drm_framebuffer *old_fb; - struct drm_i915_gem_object *pending_flip_obj; - struct drm_pending_vblank_event *event; - atomic_t pending; - u32 flip_count; - u32 gtt_offset; - struct drm_i915_gem_request *flip_queued_req; - u32 flip_queued_vblank; - u32 flip_ready_vblank; - unsigned int rotation; -}; - struct intel_load_detect_pipe { struct drm_atomic_state *restore_state; }; @@ -1903,7 +1884,7 @@ struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); void intel_pipe_update_start(struct intel_crtc *crtc); -void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work); +void intel_pipe_update_end(struct intel_crtc *crtc); /* intel_tv.c */ void intel_tv_init(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 94f9a1332dbf..8e25694a1508 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -176,7 +176,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc) * re-enables interrupts and verifies the update was actually completed * before a vblank using the value of @start_vbl_count. */ -void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) +void intel_pipe_update_end(struct intel_crtc *crtc) { enum pipe pipe = crtc->pipe; int scanline_end = intel_get_crtc_scanline(crtc); @@ -184,12 +184,6 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work ktime_t end_vbl_time = ktime_get(); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (work) { - work->flip_queued_vblank = end_vbl_count; - smp_mb__before_atomic(); - atomic_set(&work->pending, 1); - } - trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); /* We're still in the vblank-evade critical section, this can't race. From 3118cb0678550e4296a7ae3f5d88ca5a714fd155 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 20 Jul 2017 19:57:54 +0200 Subject: [PATCH 022/179] drm/i915: Drop unpin stall in atomic_prepare_commit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The core already does this in setup_commit(). With this we can also remove the unpin_work_count since it's the last user, and also remove the loop since that was only used for stalling against legacy flips. v2: Amend commit message a bit (Chris). Cc: Maarten Lankhorst Cc: Ville Syrjälä Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170720175754.30751-8-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_display.c | 13 +------------ drivers/gpu/drm/i915/intel_drv.h | 2 -- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 56bf9009ea15..9e899780dd4f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11815,18 +11815,7 @@ static int intel_atomic_check(struct drm_device *dev, static int intel_atomic_prepare_commit(struct drm_device *dev, struct drm_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_crtc_state *crtc_state; - struct drm_crtc *crtc; - int i, ret; - - for_each_new_crtc_in_state(state, crtc, crtc_state, i) { - if (state->legacy_cursor_update) - continue; - - if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) - flush_workqueue(dev_priv->wq); - } + int ret; ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 79009b759056..021cc5487853 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -798,8 +798,6 @@ struct intel_crtc { unsigned long long enabled_power_domains; struct intel_overlay *overlay; - atomic_t unpin_work_count; - /* Display surface base address adjustement for pageflips. Note that on * gen4+ this only adjusts up to a tile, offsets within a tile are * handled in the hw itself (with the TILEOFF register). */ From 7d9a1e418c962c2b25b8835dd3a6c68f81912fcd Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 20 Jul 2017 12:25:16 +0300 Subject: [PATCH 023/179] Revert "drm/i915: Add option to support dynamic backlight via DPCD" This reverts commit ae25eceab616d16a07bcaa434b84463d58a3bdc3. The DPCD backlight commits regress a Thinkpad X1 Carbon 4th Gen and a BXT-P (in CI). Enabling dynamic backlight boots to a black screen, and enabling DPCD backlight leads to a black screen after suspend/resume. References: http://mid.mail-archive.com/20170706135349.6tu3lz7uehazlnnn@boom References: http://mid.mail-archive.com/20170627132326.f2q3yn4bh5flji4q@boom Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101619 Reported-by: David Weinehall Fixes: ae25eceab616 ("drm/i915: Add option to support dynamic backlight via DPCD") Cc: Jenny TC Cc: David Weinehall Cc: Puthikorn Voravootivat Cc: Dhinakaran Pandiyan Cc: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org Reviewed-by: Dhinakaran Pandiyan Acked-by: Daniel Vetter Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/051eeb592361985d2d06333c61c220dd92253b09.1500542254.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_params.c | 5 ---- drivers/gpu/drm/i915/i915_params.h | 3 +-- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 26 ------------------- 3 files changed, 1 insertion(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 88b9d3e6713a..5b5ab15d191f 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -65,7 +65,6 @@ struct i915_params i915 __read_mostly = { .inject_load_failure = 0, .enable_dpcd_backlight = -1, .enable_gvt = false, - .enable_dbc = true, }; module_param_named(modeset, i915.modeset, int, 0400); @@ -255,7 +254,3 @@ MODULE_PARM_DESC(enable_dpcd_backlight, module_param_named(enable_gvt, i915.enable_gvt, bool, 0400); MODULE_PARM_DESC(enable_gvt, "Enable support for Intel GVT-g graphics virtualization host support(default:false)"); - -module_param_named_unsafe(enable_dbc, i915.enable_dbc, bool, 0600); -MODULE_PARM_DESC(enable_dbc, - "Enable support for dynamic backlight control (default:true)"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 057e203e6bda..0d6cf9138dc4 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -67,8 +67,7 @@ func(bool, verbose_state_checks); \ func(bool, nuclear_pageflip); \ func(bool, enable_dp_mst); \ - func(bool, enable_gvt); \ - func(bool, enable_dbc) + func(bool, enable_gvt) #define MEMBER(T, member) T member struct i915_params { diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c index b25cd88fc1c5..fea161727c6e 100644 --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -173,24 +173,6 @@ static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) return true; } -/* -* Set minimum / maximum dynamic brightness percentage. This value is expressed -* as the percentage of normal brightness in 5% increments. -*/ -static bool -intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp, - u32 min, u32 max) -{ - u8 dbc[] = { DIV_ROUND_CLOSEST(min, 5), DIV_ROUND_CLOSEST(max, 5) }; - - if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, - dbc, sizeof(dbc)) < 0) { - DRM_DEBUG_KMS("Failed to write aux DBC brightness level\n"); - return false; - } - return true; -} - static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { @@ -226,14 +208,6 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st if (intel_dp_aux_set_pwm_freq(connector)) new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; - if (i915.enable_dbc && - (intel_dp->edp_dpcd[2] & DP_EDP_DYNAMIC_BACKLIGHT_CAP)) { - if(intel_dp_aux_set_dynamic_backlight_percent(intel_dp, 0, 100)) { - new_dpcd_buf |= DP_EDP_DYNAMIC_BACKLIGHT_ENABLE; - DRM_DEBUG_KMS("Enable dynamic brightness.\n"); - } - } - if (new_dpcd_buf != dpcd_buf) { if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) { From d2939424ff89f1ee3aeefdd030cba6ba163e77ac Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 20 Jul 2017 12:25:17 +0300 Subject: [PATCH 024/179] Revert "drm/i915: Add heuristic to determine better way to adjust brightness" This reverts commit 560a758d39c616f83ac25ff6e0816a49ebe6401c. The DPCD backlight commits regress a Thinkpad X1 Carbon 4th Gen and a BXT-P (in CI). Enabling dynamic backlight boots to a black screen, and enabling DPCD backlight leads to a black screen after suspend/resume. References: http://mid.mail-archive.com/20170706135349.6tu3lz7uehazlnnn@boom References: http://mid.mail-archive.com/20170627132326.f2q3yn4bh5flji4q@boom Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101619 Reported-by: David Weinehall Fixes: 560a758d39c6 ("drm/i915: Add heuristic to determine better way to adjust brightness") Cc: Jenny TC Cc: David Weinehall Cc: Puthikorn Voravootivat Cc: Dhinakaran Pandiyan Cc: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org Reviewed-by: Dhinakaran Pandiyan Acked-by: Daniel Vetter Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/f49a89a05f18e90871c2eeadcdcd783ac7961cdf.1500542254.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_params.c | 7 +-- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 61 +------------------ 3 files changed, 7 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 5b5ab15d191f..14e2c2e57f96 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -63,7 +63,7 @@ struct i915_params i915 __read_mostly = { .huc_firmware_path = NULL, .enable_dp_mst = true, .inject_load_failure = 0, - .enable_dpcd_backlight = -1, + .enable_dpcd_backlight = false, .enable_gvt = false, }; @@ -246,10 +246,9 @@ MODULE_PARM_DESC(enable_dp_mst, module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400); MODULE_PARM_DESC(inject_load_failure, "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); -module_param_named_unsafe(enable_dpcd_backlight, i915.enable_dpcd_backlight, int, 0600); +module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600); MODULE_PARM_DESC(enable_dpcd_backlight, - "Enable support for DPCD backlight control " - "(-1:auto (default), 0:force disable, 1:force enabled if supported"); + "Enable support for DPCD backlight control (default:false)"); module_param_named(enable_gvt, i915.enable_gvt, bool, 0400); MODULE_PARM_DESC(enable_gvt, diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 0d6cf9138dc4..febbfdbd30bd 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -53,7 +53,6 @@ func(int, edp_vswing); \ func(int, reset); \ func(unsigned int, inject_load_failure); \ - func(int, enable_dpcd_backlight); \ /* leave bools at the end to not create holes */ \ func(bool, alpha_support); \ func(bool, enable_cmd_parser); \ @@ -67,6 +66,7 @@ func(bool, verbose_state_checks); \ func(bool, nuclear_pageflip); \ func(bool, enable_dp_mst); \ + func(bool, enable_dpcd_backlight); \ func(bool, enable_gvt) #define MEMBER(T, member) T member diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c index fea161727c6e..d2830ba3162e 100644 --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -251,66 +251,15 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector) /* Check the eDP Display control capabilities registers to determine if * the panel can support backlight control over the aux channel */ - if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) && - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) { + if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP && + (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) && + !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { DRM_DEBUG_KMS("AUX Backlight Control Supported!\n"); return true; } return false; } -/* - * Heuristic function whether we should use AUX for backlight adjustment or not. - * - * We should use AUX for backlight brightness adjustment if panel doesn't this - * via PWM pin or using AUX is better than using PWM pin. - * - * The heuristic to determine that using AUX pin is better than using PWM pin is - * that the panel support any of the feature list here. - * - Regional backlight brightness adjustment - * - Backlight PWM frequency set - * - More than 8 bits resolution of brightness level - * - Backlight enablement via AUX and not by BL_ENABLE pin - * - * If all above are not true, assume that using PWM pin is better. - */ -static bool -intel_dp_aux_display_control_heuristic(struct intel_connector *connector) -{ - struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); - uint8_t reg_val; - - /* Panel doesn't support adjusting backlight brightness via PWN pin */ - if (!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) - return true; - - /* Panel supports regional backlight brightness adjustment */ - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_GENERAL_CAP_3, - ®_val) != 1) { - DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", - DP_EDP_GENERAL_CAP_3); - return false; - } - if (reg_val > 0) - return true; - - /* Panel supports backlight PWM frequency set */ - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) - return true; - - /* Panel supports more than 8 bits resolution of brightness level */ - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) - return true; - - /* Panel supports enabling backlight via AUX but not by BL_ENABLE pin */ - if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) && - !(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP)) - return true; - - return false; - -} - int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) { struct intel_panel *panel = &intel_connector->panel; @@ -321,10 +270,6 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) if (!intel_dp_aux_display_control_capable(intel_connector)) return -ENODEV; - if (i915.enable_dpcd_backlight == -1 && - !intel_dp_aux_display_control_heuristic(intel_connector)) - return -ENODEV; - panel->backlight.setup = intel_dp_aux_setup_backlight; panel->backlight.enable = intel_dp_aux_enable_backlight; panel->backlight.disable = intel_dp_aux_disable_backlight; From 4d73da937fcf5f1bc0e58f6f34b2c32355e64f74 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:19 +0100 Subject: [PATCH 025/179] drm/i915: Report execlists irq bit in debugfs As part of the knowing whether there is outstanding data in the CSB, also check whether there is an outstanding IRQ notification. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c25f42c60d61..ea50c4a1efae 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3325,8 +3325,10 @@ static int i915_engine_info(struct seq_file *m, void *unused) ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); read = GEN8_CSB_READ_PTR(ptr); write = GEN8_CSB_WRITE_PTR(ptr); - seq_printf(m, "\tExeclist CSB read %d, write %d\n", - read, write); + seq_printf(m, "\tExeclist CSB read %d, write %d, interrupt posted? %s\n", + read, write, + yesno(test_bit(ENGINE_IRQ_EXECLIST, + &engine->irq_posted))); if (read >= GEN8_CSB_ENTRIES) read = 0; if (write >= GEN8_CSB_ENTRIES) From b4f3e1631f5e8fcfb1da84cbd5d3ec581480954a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:20 +0100 Subject: [PATCH 026/179] drm/i915: Reset context image on engines after triggering the reset We try to fixup the context image after the reset to ensure that there are no more pending writes from the hw that may conflict and to fixup any that were in flight. Fixes: a1ef70e14453 ("drm/i915: Add support for per engine reset recovery") Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Tvrtko Ursulin Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-2-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6b583dc2eb1f..853d6741d3a5 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1950,6 +1950,8 @@ int i915_reset_engine(struct intel_engine_cs *engine) goto out; } + ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine)); + /* * The request that caused the hang is stuck on elsp, we know the * active request and can drop it, adjust head to skip the offending @@ -1957,9 +1959,6 @@ int i915_reset_engine(struct intel_engine_cs *engine) */ i915_gem_reset_engine(engine, active_request); - /* Finally, reset just this engine. */ - ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine)); - i915_gem_reset_finish_engine(engine); if (ret) { From 0364cd19d61caad7292cc4e87f5001595b6c7642 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:21 +0100 Subject: [PATCH 027/179] drm/i915: Serialize per-engine resets against new requests We rely on disabling the execlists (by stopping the tasklet) to prevent new requests from submitting to the engine ELSP before we are ready. However, we re-enable the engine before we call init_hw which gives userspace the opportunity to subit a new request which is then overwritten by init_hw -- but not before the HW may have started executing. The subsequent out-of-order CSB is detected by our sanity checks in intel_lrc_irq_handler(). Fixes: a1ef70e14453 ("drm/i915: Add support for per engine reset recovery") Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-3-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 853d6741d3a5..6753fc861dbb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1951,6 +1951,12 @@ int i915_reset_engine(struct intel_engine_cs *engine) } ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine)); + if (ret) { + /* If we fail here, we expect to fallback to a global reset */ + DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n", + engine->name, ret); + goto out; + } /* * The request that caused the hang is stuck on elsp, we know the @@ -1959,15 +1965,6 @@ int i915_reset_engine(struct intel_engine_cs *engine) */ i915_gem_reset_engine(engine, active_request); - i915_gem_reset_finish_engine(engine); - - if (ret) { - /* If we fail here, we expect to fallback to a global reset */ - DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n", - engine->name, ret); - goto out; - } - /* * The engine and its registers (and workarounds in case of render) * have been reset to their default values. Follow the init_ring @@ -1979,6 +1976,7 @@ int i915_reset_engine(struct intel_engine_cs *engine) error->reset_engine_count[engine->id]++; out: + i915_gem_reset_finish_engine(engine); return ret; } From cdb6ded42f735396197906de04316d9b0e10c987 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:22 +0100 Subject: [PATCH 028/179] drm/i915: Flush the execlist ports if idle When doing a GPU reset, the CSB register will be trashed and we will lose any context-switch notifications that happened since the tasklet was disabled. If we find that all requests on this engine were completed, we want to make sure that the ELSP tracker is similarly empty so that we do not feed back in the completed requests upon recovering from the reset. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-4-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 36 +++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 699868d81de8..b0738d2b2a7f 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1306,6 +1306,31 @@ static void reset_common_ring(struct intel_engine_cs *engine, { struct execlist_port *port = engine->execlist_port; struct intel_context *ce; + unsigned int n; + + /* + * Catch up with any missed context-switch interrupts. + * + * Ideally we would just read the remaining CSB entries now that we + * know the gpu is idle. However, the CSB registers are sometimes^W + * often trashed across a GPU reset! Instead we have to rely on + * guessing the missed context-switch events by looking at what + * requests were completed. + */ + if (!request) { + for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) + i915_gem_request_put(port_request(&port[n])); + memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); + return; + } + + if (request->ctx != port_request(port)->ctx) { + i915_gem_request_put(port_request(port)); + port[0] = port[1]; + memset(&port[1], 0, sizeof(port[1])); + } + + GEM_BUG_ON(request->ctx != port_request(port)->ctx); /* If the request was innocent, we leave the request in the ELSP * and will try to replay it on restarting. The context image may @@ -1317,7 +1342,7 @@ static void reset_common_ring(struct intel_engine_cs *engine, * and have to at least restore the RING register in the context * image back to the expected values to skip over the guilty request. */ - if (!request || request->fence.error != -EIO) + if (request->fence.error != -EIO) return; /* We want a simple context + ring to execute the breadcrumb update. @@ -1339,15 +1364,6 @@ static void reset_common_ring(struct intel_engine_cs *engine, request->ring->head = request->postfix; intel_ring_update_space(request->ring); - /* Catch up with any missed context-switch interrupts */ - if (request->ctx != port_request(port)->ctx) { - i915_gem_request_put(port_request(port)); - port[0] = port[1]; - memset(&port[1], 0, sizeof(port[1])); - } - - GEM_BUG_ON(request->ctx != port_request(port)->ctx); - /* Reset WaIdleLiteRestore:bdw,skl as well */ request->tail = intel_ring_wrap(request->ring, From 5cce5e31a7295a3365813bafd59bae7fa049f6c0 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:23 +0100 Subject: [PATCH 029/179] drm/i915: Check execlist/ring status during hangcheck Before we declare an engine as idle, check if there are any pending execlist context-switches and if the ring itself reports as idle. Otherwise, we may be left in a situation where we miss a crucial execlist event (or something more sinister) yet the requests complete. Since the seqno write happens, we believe the engine to be truly idle. Signed-off-by: Chris Wilson Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-5-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index 9b0ece427bdc..d9d87d96fb69 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -324,7 +324,7 @@ hangcheck_get_action(struct intel_engine_cs *engine, if (engine->hangcheck.seqno != hc->seqno) return ENGINE_ACTIVE_SEQNO; - if (i915_seqno_passed(hc->seqno, intel_engine_last_submit(engine))) + if (intel_engine_is_idle(engine)) return ENGINE_IDLE; return engine_stuck(engine, hc->acthd); From d6edb6e3b63faae5cd96993e0977d3807bd87be6 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:24 +0100 Subject: [PATCH 030/179] drm/i915: Check the execlist queue for pending requests before declaring idle Including a check against the execlist queue before calling the engine idle and passing hangcheck. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-6-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 24db316e0fd1..c6ebfe7fb4f1 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1283,6 +1283,10 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) if (port_request(&engine->execlist_port[0])) return false; + /* ELSP is empty, but there are ready requests? */ + if (READ_ONCE(engine->execlist_first)) + return false; + /* Ring stopped? */ if (!ring_is_idle(engine)) return false; From 5e32d7482ee20738d3474151f365b0a522fba463 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:25 +0100 Subject: [PATCH 031/179] drm/i915: Clear execlist port[] before updating seqno on wedging When we wedge the device, we clear out the in-flight requests and advance the breadcrumb to indicate they are complete. However, the breadcrumb advance includes an assert that the engine is idle, so that advancement needs to be the last step to ensure we pass our own sanity checks. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-7-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1a8842f143fc..8da1489913c2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3051,13 +3051,6 @@ static void engine_set_wedged(struct intel_engine_cs *engine) dma_fence_set_error(&request->fence, -EIO); spin_unlock_irqrestore(&engine->timeline->lock, flags); - /* Mark all pending requests as complete so that any concurrent - * (lockless) lookup doesn't try and wait upon the request as we - * reset it. - */ - intel_engine_init_global_seqno(engine, - intel_engine_last_submit(engine)); - /* * Clear the execlists queue up before freeing the requests, as those * are the ones that keep the context and ringbuffer backing objects @@ -3086,6 +3079,13 @@ static void engine_set_wedged(struct intel_engine_cs *engine) */ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); } + + /* Mark all pending requests as complete so that any concurrent + * (lockless) lookup doesn't try and wait upon the request as we + * reset it. + */ + intel_engine_init_global_seqno(engine, + intel_engine_last_submit(engine)); } static int __i915_gem_set_wedged_BKL(void *data) From 4d53568cca96015d7ad44353dfd83c10ef14c6cf Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:26 +0100 Subject: [PATCH 032/179] drm/i915: Move idle checks before intel_engine_init_global_seqno() intel_engine_init_globa_seqno() may be called from an uncontrolled set-wedged path where we have given up waiting for broken hw and declare it defunct. Along that path, any sanity checks that the hw is idle before we adjust its state will expectedly fail, so we simply cannot. Instead of asserting inside init_global_seqno, we move them to the normal caller reset_all_global_seqno() as it handles runtime seqno wraparound. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-8-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_request.c | 4 ++++ drivers/gpu/drm/i915/intel_engine_cs.c | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 483af8921060..d93a185c0f0a 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -213,6 +213,10 @@ static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) cond_resched(); } + /* Check we are idle before we fiddle with hw state! */ + GEM_BUG_ON(!intel_engine_is_idle(engine)); + GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request)); + /* Finally reset hw state */ intel_engine_init_global_seqno(engine, seqno); tl->seqno = seqno; diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index c6ebfe7fb4f1..9ab596941372 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -337,9 +337,6 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) { struct drm_i915_private *dev_priv = engine->i915; - GEM_BUG_ON(!intel_engine_is_idle(engine)); - GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request)); - /* Our semaphore implementation is strictly monotonic (i.e. we proceed * so long as the semaphore value in the register/page is greater * than the sync value), so whenever we reset the seqno, From 3d7adbbf49c31b194958ad381010e86c842e40af Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:27 +0100 Subject: [PATCH 033/179] drm/i915: Wake up waiters after setting the WEDGED bit After setting the WEDGED bit, make sure that we do wake up waiters as they may not be waiting for a request completion yet, just for its execution. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-9-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8da1489913c2..a01176dd4bae 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3094,10 +3094,12 @@ static int __i915_gem_set_wedged_BKL(void *data) struct intel_engine_cs *engine; enum intel_engine_id id; - set_bit(I915_WEDGED, &i915->gpu_error.flags); for_each_engine(engine, i915, id) engine_set_wedged(engine); + set_bit(I915_WEDGED, &i915->gpu_error.flags); + wake_up_all(&i915->gpu_error.reset_queue); + return 0; } From bf2eac3bee51299bd08dcbd25f7bd8dbaaff1b62 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:28 +0100 Subject: [PATCH 034/179] drm/i915: Assert that machine is wedged for nop_submit_request We should only ever do nop_submit_request when the machine is wedged, so assert it is so. Signed-off-by: Chris Wilson Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-10-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a01176dd4bae..2ff5e23406e5 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3026,6 +3026,7 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) static void nop_submit_request(struct drm_i915_gem_request *request) { + GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error)); dma_fence_set_error(&request->fence, -EIO); i915_gem_request_submit(request); intel_engine_init_global_seqno(request->engine, request->global_seqno); From ed454f2cd61a54d00c267e385c0600bae0761833 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:29 +0100 Subject: [PATCH 035/179] drm/i915: Clear engine irq posted following a reset When the GPU is reset, we want to discard all pending notifications as either we have manually completed them, or they are no longer applicable. Make sure we do reset the engine->irq_posted prior to re-enabling the engine (e.g. the interrupt tasklets) in i915_gem_reset_finish_engine(). Signed-off-by: Chris Wilson Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-11-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 2ff5e23406e5..fcf7fee7ca71 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2964,6 +2964,8 @@ static bool i915_gem_reset_request(struct drm_i915_gem_request *request) void i915_gem_reset_engine(struct intel_engine_cs *engine, struct drm_i915_gem_request *request) { + engine->irq_posted = 0; + if (request && i915_gem_reset_request(request)) { DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", engine->name, request->global_seqno); From 77b25a972b5d4ed93b8a86d3e383ec2092fd89b1 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:30 +0100 Subject: [PATCH 036/179] drm/i915: Make i915_gem_context_mark_guilty() safe for unlocked updates Since we make call i915_gem_context_mark_guilty() concurrently when resetting different engines in parallel, we need to make sure that our updates are safe for the unlocked access. Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-12-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gem.c | 32 ++++++++++++++----------- drivers/gpu/drm/i915/i915_gem_context.c | 6 ++--- drivers/gpu/drm/i915/i915_gem_context.h | 6 ++--- drivers/gpu/drm/i915/i915_gem_request.c | 3 +-- drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++---- 6 files changed, 30 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ef089fe0353e..b051122c960b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -602,7 +602,7 @@ struct drm_i915_file_private { * to limit the badly behaving clients access to gpu. */ #define I915_MAX_CLIENT_CONTEXT_BANS 3 - int context_bans; + atomic_t context_bans; }; /* Used by dp and fdi links */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fcf7fee7ca71..a9ea83ea321b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2740,34 +2740,38 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, return 0; } -static bool ban_context(const struct i915_gem_context *ctx) +static bool ban_context(const struct i915_gem_context *ctx, + unsigned int score) { return (i915_gem_context_is_bannable(ctx) && - ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD); + score >= CONTEXT_SCORE_BAN_THRESHOLD); } static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) { - ctx->guilty_count++; - ctx->ban_score += CONTEXT_SCORE_GUILTY; - if (ban_context(ctx)) - i915_gem_context_set_banned(ctx); + unsigned int score; + bool banned; + atomic_inc(&ctx->guilty_count); + + score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score); + banned = ban_context(ctx, score); DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", - ctx->name, ctx->ban_score, - yesno(i915_gem_context_is_banned(ctx))); - - if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv)) + ctx->name, score, yesno(banned)); + if (!banned) return; - ctx->file_priv->context_bans++; - DRM_DEBUG_DRIVER("client %s has had %d context banned\n", - ctx->name, ctx->file_priv->context_bans); + i915_gem_context_set_banned(ctx); + if (!IS_ERR_OR_NULL(ctx->file_priv)) { + atomic_inc(&ctx->file_priv->context_bans); + DRM_DEBUG_DRIVER("client %s has had %d context banned\n", + ctx->name, atomic_read(&ctx->file_priv->context_bans)); + } } static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) { - ctx->active_count++; + atomic_inc(&ctx->active_count); } struct drm_i915_gem_request * diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 1a87d04e7937..ed91ac8ca832 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -977,7 +977,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) static bool client_is_banned(struct drm_i915_file_private *file_priv) { - return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS; + return atomic_read(&file_priv->context_bans) > I915_MAX_CLIENT_CONTEXT_BANS; } int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, @@ -1179,8 +1179,8 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, else args->reset_count = 0; - args->batch_active = READ_ONCE(ctx->guilty_count); - args->batch_pending = READ_ONCE(ctx->active_count); + args->batch_active = atomic_read(&ctx->guilty_count); + args->batch_pending = atomic_read(&ctx->active_count); ret = 0; out: diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 04320f80f9f4..2d02918a449e 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -191,17 +191,17 @@ struct i915_gem_context { u32 desc_template; /** guilty_count: How many times this context has caused a GPU hang. */ - unsigned int guilty_count; + atomic_t guilty_count; /** * @active_count: How many times this context was active during a GPU * hang, but did not cause it. */ - unsigned int active_count; + atomic_t active_count; #define CONTEXT_SCORE_GUILTY 10 #define CONTEXT_SCORE_BAN_THRESHOLD 40 /** ban_score: Accumulated score of all hangs caused by this context. */ - int ban_score; + atomic_t ban_score; /** remap_slice: Bitmask of cache lines that need remapping */ u8 remap_slice; diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index d93a185c0f0a..68e406a53c04 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -374,8 +374,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) i915_gem_request_remove_from_client(request); /* Retirement decays the ban score as it is a sign of ctx progress */ - if (request->ctx->ban_score > 0) - request->ctx->ban_score--; + atomic_dec_if_positive(&request->ctx->ban_score); /* The backing object for the context is done after switching to the * *next* context. Therefore we cannot retire the previous context until diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index ae70283470a6..ed5a1eb839ad 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1266,7 +1266,7 @@ static void record_request(struct drm_i915_gem_request *request, struct drm_i915_error_request *erq) { erq->context = request->ctx->hw_id; - erq->ban_score = request->ctx->ban_score; + erq->ban_score = atomic_read(&request->ctx->ban_score); erq->seqno = request->global_seqno; erq->jiffies = request->emitted_jiffies; erq->head = request->head; @@ -1357,9 +1357,9 @@ static void record_context(struct drm_i915_error_context *e, e->handle = ctx->user_handle; e->hw_id = ctx->hw_id; - e->ban_score = ctx->ban_score; - e->guilty = ctx->guilty_count; - e->active = ctx->active_count; + e->ban_score = atomic_read(&ctx->ban_score); + e->guilty = atomic_read(&ctx->guilty_count); + e->active = atomic_read(&ctx->active_count); } static void request_record_user_bo(struct drm_i915_gem_request *request, From 7367612fe1eae573d86fc273a29af0797bfb918f Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:31 +0100 Subject: [PATCH 037/179] drm/i915: Emit a user level message when resetting the GPU (or engine) Although a banned context will be told to -EIO off if they try to submit more requests, we have a discrepancy between whole device resets and per-engine resets where we report the GPU reset but not the engine resets. This leaves a bit of mystery as to why the context was banned, and also reduces awareness overall of when a GPU (engine) reset occurs with its possible side-effects. Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-13-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6753fc861dbb..3ac8215c0e36 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1861,9 +1861,10 @@ void i915_reset(struct drm_i915_private *dev_priv) if (!i915_gem_unset_wedged(dev_priv)) goto wakeup; + dev_notice(dev_priv->drm.dev, + "Resetting chip after gpu hang\n"); error->reset_count++; - pr_notice("drm/i915: Resetting chip after gpu hang\n"); disable_irq(dev_priv->drm.irq); ret = i915_gem_reset_prepare(dev_priv); if (ret) { @@ -1941,7 +1942,9 @@ int i915_reset_engine(struct intel_engine_cs *engine) GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); - DRM_DEBUG_DRIVER("resetting %s\n", engine->name); + dev_notice(engine->i915->drm.dev, + "Resetting %s after gpu hang\n", engine->name); + error->reset_engine_count[engine->id]++; active_request = i915_gem_reset_prepare_engine(engine); if (IS_ERR(active_request)) { @@ -1974,7 +1977,6 @@ int i915_reset_engine(struct intel_engine_cs *engine) if (ret) goto out; - error->reset_engine_count[engine->id]++; out: i915_gem_reset_finish_engine(engine); return ret; From 2b49e7210efcb5b977cffafa5e651e1b5c8555a3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 4 Jul 2017 16:56:09 +0100 Subject: [PATCH 038/179] drm/i915: Disable per-engine reset for Broxton Triggering a GPU reset for one engine affects another, notably corrupting the context status buffer (CSB) effectively losing track of inflight requests. Adding a few printks: diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ad41836fa5e5..a969456bc0fa 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1953,6 +1953,7 @@ int i915_reset_engine(struct intel_engine_cs *engine) goto out; } + pr_err("Resetting %s\n", engine->name); ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine)); if (ret) { /* If we fail here, we expect to fallback to a global reset */ diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 716e5c9ea222..a72bc35d0870 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -355,6 +355,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); port_set(&port[n], port_pack(rq, count)); desc = execlists_update_context(rq); + pr_err("%s: in (rq=%x) ctx=%d\n", engine->name, rq->global_seqno, upper_32_bits(desc)); GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); } else { GEM_BUG_ON(!n); @@ -594,9 +595,23 @@ static void intel_lrc_irq_handler(unsigned long data) if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) continue; + pr_err("%s: out CSB (%x head=%d, tail=%d), ctx=%d, rq=%d\n", + engine->name, + readl(csb_mmio), + head, tail, + readl(buf+2*head+1), + port->context_id); + /* Check the context/desc id for this event matches */ - GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) != - port->context_id); + if (readl(buf + 2 * head + 1) != port->context_id) { + pr_err("%s: BUG CSB (%x head=%d, tail=%d), ctx=%d, rq=%d\n", + engine->name, + readl(csb_mmio), + head, tail, + readl(buf+2*head+1), + port->context_id); + BUG(); + } rq = port_unpack(port, &count); GEM_BUG_ON(count == 0); Results in: [ 6423.006602] Resetting rcs0 [ 6423.009080] rcs0: in (rq=fffffe70) ctx=1 [ 6423.009216] rcs0: in (rq=fffffe6f) ctx=3 [ 6423.009542] rcs0: out CSB (2 head=1, tail=2), ctx=3, rq=3 [ 6423.009619] Resetting bcs0 [ 6423.009980] rcs0: BUG CSB (0 head=1, tail=2), ctx=0, rq=3 Note that this bug may be affect all machines and not just Broxton, Broxton is just the first machine on which I have confirmed this bug. Fixes: 142bc7d99bcf ("drm/i915: Modify error handler for per engine hang recovery") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Michel Thierry Acked-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-13-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a1e6b696bcfa..09d97e0990b7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -398,6 +398,7 @@ static const struct intel_device_info intel_broxton_info = { GEN9_LP_FEATURES, .platform = INTEL_BROXTON, .ddb_size = 512, + .has_reset_engine = false, }; static const struct intel_device_info intel_geminilake_info = { From 79f0f4724d9c502d65d08917709a60e4a8cb4972 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:34 +0100 Subject: [PATCH 039/179] drm/i915/selftests: Exercise independence of per-engine resets If all goes well, resetting one engine should not affect the operation of any others. So to test this, we setup a continuous stream of requests onto to each of the "innocent" engines whilst constantly resetting our target engine. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Michel Thierry Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-16-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- .../gpu/drm/i915/selftests/intel_hangcheck.c | 164 ++++++++++++++++++ drivers/gpu/drm/i915/selftests/mock_context.c | 8 + drivers/gpu/drm/i915/selftests/mock_context.h | 3 + 3 files changed, 175 insertions(+) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 7096c3911cd3..cf589e3c7106 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -22,8 +22,13 @@ * */ +#include + #include "../i915_selftest.h" +#include "mock_context.h" +#include "mock_drm.h" + struct hang { struct drm_i915_private *i915; struct drm_i915_gem_object *hws; @@ -372,6 +377,164 @@ static int igt_reset_engine(void *arg) return err; } +static int active_engine(void *data) +{ + struct intel_engine_cs *engine = data; + struct drm_i915_gem_request *rq[2] = {}; + struct i915_gem_context *ctx[2]; + struct drm_file *file; + unsigned long count = 0; + int err = 0; + + file = mock_file(engine->i915); + if (IS_ERR(file)) + return PTR_ERR(file); + + mutex_lock(&engine->i915->drm.struct_mutex); + ctx[0] = live_context(engine->i915, file); + mutex_unlock(&engine->i915->drm.struct_mutex); + if (IS_ERR(ctx[0])) { + err = PTR_ERR(ctx[0]); + goto err_file; + } + + mutex_lock(&engine->i915->drm.struct_mutex); + ctx[1] = live_context(engine->i915, file); + mutex_unlock(&engine->i915->drm.struct_mutex); + if (IS_ERR(ctx[1])) { + err = PTR_ERR(ctx[1]); + i915_gem_context_put(ctx[0]); + goto err_file; + } + + while (!kthread_should_stop()) { + unsigned int idx = count++ & 1; + struct drm_i915_gem_request *old = rq[idx]; + struct drm_i915_gem_request *new; + + mutex_lock(&engine->i915->drm.struct_mutex); + new = i915_gem_request_alloc(engine, ctx[idx]); + if (IS_ERR(new)) { + mutex_unlock(&engine->i915->drm.struct_mutex); + err = PTR_ERR(new); + break; + } + + rq[idx] = i915_gem_request_get(new); + i915_add_request(new); + mutex_unlock(&engine->i915->drm.struct_mutex); + + if (old) { + i915_wait_request(old, 0, MAX_SCHEDULE_TIMEOUT); + i915_gem_request_put(old); + } + } + + for (count = 0; count < ARRAY_SIZE(rq); count++) + i915_gem_request_put(rq[count]); + +err_file: + mock_file_free(engine->i915, file); + return err; +} + +static int igt_reset_active_engines(void *arg) +{ + struct drm_i915_private *i915 = arg; + struct intel_engine_cs *engine, *active; + enum intel_engine_id id, tmp; + int err = 0; + + /* Check that issuing a reset on one engine does not interfere + * with any other engine. + */ + + if (!intel_has_reset_engine(i915)) + return 0; + + for_each_engine(engine, i915, id) { + struct task_struct *threads[I915_NUM_ENGINES]; + unsigned long resets[I915_NUM_ENGINES]; + unsigned long global = i915_reset_count(&i915->gpu_error); + IGT_TIMEOUT(end_time); + + memset(threads, 0, sizeof(threads)); + for_each_engine(active, i915, tmp) { + struct task_struct *tsk; + + if (active == engine) + continue; + + resets[tmp] = i915_reset_engine_count(&i915->gpu_error, + active); + + tsk = kthread_run(active_engine, active, + "igt/%s", active->name); + if (IS_ERR(tsk)) { + err = PTR_ERR(tsk); + goto unwind; + } + + threads[tmp] = tsk; + get_task_struct(tsk); + } + + set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags); + do { + err = i915_reset_engine(engine); + if (err) { + pr_err("i915_reset_engine(%s) failed, err=%d\n", + engine->name, err); + break; + } + } while (time_before(jiffies, end_time)); + clear_bit(I915_RESET_ENGINE + engine->id, + &i915->gpu_error.flags); + +unwind: + for_each_engine(active, i915, tmp) { + int ret; + + if (!threads[tmp]) + continue; + + ret = kthread_stop(threads[tmp]); + if (ret) { + pr_err("kthread for active engine %s failed, err=%d\n", + active->name, ret); + if (!err) + err = ret; + } + put_task_struct(threads[tmp]); + + if (resets[tmp] != i915_reset_engine_count(&i915->gpu_error, + active)) { + pr_err("Innocent engine %s was reset (count=%ld)\n", + active->name, + i915_reset_engine_count(&i915->gpu_error, + active) - resets[tmp]); + err = -EIO; + } + } + + if (global != i915_reset_count(&i915->gpu_error)) { + pr_err("Global reset (count=%ld)!\n", + i915_reset_count(&i915->gpu_error) - global); + err = -EIO; + } + + if (err) + break; + + cond_resched(); + } + + if (i915_terminally_wedged(&i915->gpu_error)) + err = -EIO; + + return err; +} + static u32 fake_hangcheck(struct drm_i915_gem_request *rq) { u32 reset_count; @@ -689,6 +852,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) SUBTEST(igt_hang_sanitycheck), SUBTEST(igt_global_reset), SUBTEST(igt_reset_engine), + SUBTEST(igt_reset_active_engines), SUBTEST(igt_wait_reset), SUBTEST(igt_reset_queue), SUBTEST(igt_render_engine_reset_fallback), diff --git a/drivers/gpu/drm/i915/selftests/mock_context.c b/drivers/gpu/drm/i915/selftests/mock_context.c index 9c7c68181f82..d436f2d5089b 100644 --- a/drivers/gpu/drm/i915/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/selftests/mock_context.c @@ -95,3 +95,11 @@ void mock_init_contexts(struct drm_i915_private *i915) INIT_WORK(&i915->contexts.free_work, contexts_free_worker); init_llist_head(&i915->contexts.free_list); } + +struct i915_gem_context * +live_context(struct drm_i915_private *i915, struct drm_file *file) +{ + lockdep_assert_held(&i915->drm.struct_mutex); + + return i915_gem_create_context(i915, file->driver_priv); +} diff --git a/drivers/gpu/drm/i915/selftests/mock_context.h b/drivers/gpu/drm/i915/selftests/mock_context.h index 383941a61124..2f432c03d413 100644 --- a/drivers/gpu/drm/i915/selftests/mock_context.h +++ b/drivers/gpu/drm/i915/selftests/mock_context.h @@ -33,4 +33,7 @@ mock_context(struct drm_i915_private *i915, void mock_context_close(struct i915_gem_context *ctx); +struct i915_gem_context * +live_context(struct drm_i915_private *i915, struct drm_file *file); + #endif /* !__MOCK_CONTEXT_H */ From 5fb9dadf336f3590c799e8cbde348215dccc2aa2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 20 Jul 2017 14:28:20 +0300 Subject: [PATCH 040/179] drm/i915: Fix scaler init during CRTC HW state readout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The scaler allocation code depends on a non-zero default value for the crtc scaler_id, so make sure we initialize the scaler state accordingly even if the crtc is off. This fixes at least an initial YUV420 modeset (added in a follow-up patchset by Shashank) when booting with the screen off: after the initial HW readout and modeset which enables the scaler a subsequent modeset will disable the scaler which isn't properly allocated. This results in a funky HW state where the pipe scaler HW registers can't be modified and the normally black screen is grey and shifted to the right or jitters. The problem was revealed by Shashank's YUV420 patchset and first reported by Ville. v2: - In the stable tag also include versions which need backporting (Jani) Cc: Jani Nikula Cc: Shashank Sharma Cc: Ville Syrjälä Cc: Chandra Konduru Cc: Matt Roper Cc: # 4.2.x Reported-by: Ville Syrjälä Fixes: a1b2278e4dfc ("drm/i915: skylake panel fitting using shared scalers") Signed-off-by: Imre Deak Reviewed-by: Mahesh Kumar Link: https://patchwork.freedesktop.org/patch/msgid/20170720112820.26816-1-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 93330de32fc4..6ec5261f1759 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8989,6 +8989,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, u64 power_domain_mask; bool active; + if (INTEL_GEN(dev_priv) >= 9) { + intel_crtc_init_scalers(crtc, pipe_config); + + pipe_config->scaler_state.scaler_id = -1; + pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); + } + power_domain = POWER_DOMAIN_PIPE(crtc->pipe); if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) return false; @@ -9017,13 +9024,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; - if (INTEL_GEN(dev_priv) >= 9) { - intel_crtc_init_scalers(crtc, pipe_config); - - pipe_config->scaler_state.scaler_id = -1; - pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); - } - power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); From e79dfb512110ce6759f139a286f0e1d6bc5e4c58 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 20 Jul 2017 01:50:57 +0300 Subject: [PATCH 041/179] drm/i915: Simplify scaler init during CRTC HW readout The crtc state starts out being bzero'd, so no need to clear scaler_users. Also intel_crtc_init_scalers() knows already which platforms have scalers, so no need for the platform check here. Similarly intel_crtc_init_scalers() will init scaler_id as required, so no need to do it here separately. Cc: Chandra Konduru Cc: Matt Roper Signed-off-by: Imre Deak Reviewed-by: Mahesh Kumar Link: https://patchwork.freedesktop.org/patch/msgid/20170719225057.20131-2-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6ec5261f1759..6c823cc02db3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8989,12 +8989,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, u64 power_domain_mask; bool active; - if (INTEL_GEN(dev_priv) >= 9) { - intel_crtc_init_scalers(crtc, pipe_config); - - pipe_config->scaler_state.scaler_id = -1; - pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); - } + intel_crtc_init_scalers(crtc, pipe_config); power_domain = POWER_DOMAIN_PIPE(crtc->pipe); if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) From f49193cd62cb014fc0857cc27705002900ce0fc1 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:23 +0300 Subject: [PATCH 042/179] drm/i915/chv: Add unique power well ID for the pipe A power well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The power well IDs are used for lookup, so they must be unique on a given platform; ensure this on CHV. This didn't cause an actual problem since we didn't need to look up power wells which happened to share an ID. Mark this new power well as custom, since its programming pattern doesn't follow that of the rest of VLV/CHV power wells. Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-2-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +++++----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c712d01f92ab..c0199f2da35e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1077,6 +1077,8 @@ enum punit_power_well { PUNIT_POWER_WELL_DPIO_RX0 = 10, PUNIT_POWER_WELL_DPIO_RX1 = 11, PUNIT_POWER_WELL_DPIO_CMN_D = 12, + /* - custom power well */ + CHV_DISP_PW_PIPE_A, /* 13 */ /* Not actual bit groups. Used as IDs for lookup_power_well() */ PUNIT_POWER_WELL_ALWAYS_ON, diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index f630d632a976..44008c6c8fcc 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1672,7 +1672,7 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - enum pipe pipe = power_well->id; + enum pipe pipe = PIPE_A; bool enabled; u32 state, ctrl; @@ -1702,7 +1702,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - enum pipe pipe = power_well->id; + enum pipe pipe = PIPE_A; u32 state; u32 ctrl; @@ -1735,7 +1735,7 @@ out: static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN_ON_ONCE(power_well->id != PIPE_A); + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); chv_set_pipe_power_well(dev_priv, power_well, true); @@ -1745,7 +1745,7 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN_ON_ONCE(power_well->id != PIPE_A); + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); vlv_display_power_well_deinit(dev_priv); @@ -2184,7 +2184,7 @@ static struct i915_power_well chv_power_wells[] = { * required for any pipe to work. */ .domains = CHV_DISPLAY_POWER_DOMAINS, - .id = PIPE_A, + .id = CHV_DISP_PW_PIPE_A, .ops = &chv_pipe_power_well_ops, }, { From 438b8dc457e7274dba6e988ad3406fddb7bdda45 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jul 2017 23:42:30 +0300 Subject: [PATCH 043/179] drm/i915: Unify power well ID enums MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Atm, the power well IDs are defined in separate platform specific enums, which isn't ideal for the following reasons: - the IDs are used by helpers like lookup_power_well() in a platform independent way - the always-on power well is used by multiple platforms and so needs now separate IDs, although these IDs refer to the same thing To make things more consistent use a single enum instead of the two separate ones, listing the IDs per platform (or set of very similar platforms like all GEN9/10). Replace the separate always-on power well IDs with a single ID. While at it also add a note clarifying the distinction between regular power wells that follow a common programming pattern and custom ones that are programmed in some other way. The IDs for regular power wells need to stay fixed, since they also define the request and state HW flag positions in their corresponding power well control register(s). v2: - Add comment about id to req,status bit mapping to the enum. (Rodrigo) Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-1-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 42 ++++++++++++++++--------- drivers/gpu/drm/i915/intel_runtime_pm.c | 29 +++++++++-------- 3 files changed, 45 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b051122c960b..c4c02173b87c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1383,7 +1383,7 @@ struct i915_power_well { bool hw_enabled; u64 domains; /* unique identifier for this power well */ - unsigned long id; + enum i915_power_well_id id; /* * Arbitraty data associated with this power well. Platform and power * well specific. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c0199f2da35e..aee40eecf688 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1063,9 +1063,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) -/* See the PUNIT HAS v0.8 for the below bits */ -enum punit_power_well { - /* These numbers are fixed and must match the position of the pw bits */ +/** + * i915_power_well_id: + * + * Platform specific IDs used to look up power wells and - except for custom + * power wells - to define request/status register flag bit positions. As such + * the set of IDs on a given platform must be unique and except for custom + * power wells their value must stay fixed. + */ +enum i915_power_well_id { + /* + * VLV/CHV + * - PUNIT_REG_PWRGT_CTRL (bit: id*2), + * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) + */ PUNIT_POWER_WELL_RENDER = 0, PUNIT_POWER_WELL_MEDIA = 1, PUNIT_POWER_WELL_DISP2D = 3, @@ -1080,13 +1091,11 @@ enum punit_power_well { /* - custom power well */ CHV_DISP_PW_PIPE_A, /* 13 */ - /* Not actual bit groups. Used as IDs for lookup_power_well() */ - PUNIT_POWER_WELL_ALWAYS_ON, -}; - -enum skl_disp_power_wells { - /* These numbers are fixed and must match the position of the pw bits */ - SKL_DISP_PW_MISC_IO, + /* + * GEN9+ + * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) + */ + SKL_DISP_PW_MISC_IO = 0, SKL_DISP_PW_DDI_A_E, GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, @@ -1105,13 +1114,18 @@ enum skl_disp_power_wells { SKL_DISP_PW_1 = 14, SKL_DISP_PW_2, - /* Not actual bit groups. Used as IDs for lookup_power_well() */ - SKL_DISP_PW_ALWAYS_ON, + /* - custom power wells */ SKL_DISP_PW_DC_OFF, - BXT_DPIO_CMN_A, BXT_DPIO_CMN_BC, - GLK_DPIO_CMN_C, + GLK_DPIO_CMN_C, /* 19 */ + + /* + * Multiple platforms. + * Must start following the highest ID of any platform. + * - custom power wells + */ + I915_DISP_PW_ALWAYS_ON = 20, }; #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 44008c6c8fcc..00ae25b59661 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -50,10 +50,11 @@ */ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, - int power_well_id); + enum i915_power_well_id power_well_id); static struct i915_power_well * -lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id); +lookup_power_well(struct drm_i915_private *dev_priv, + enum i915_power_well_id power_well_id); const char * intel_display_power_domain_str(enum intel_display_power_domain domain) @@ -344,7 +345,7 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - int id = power_well->id; + enum i915_power_well_id id = power_well->id; /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ WARN_ON(intel_wait_for_register(dev_priv, @@ -354,7 +355,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 1)); } -static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id) +static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, + enum i915_power_well_id id) { u32 req_mask = SKL_POWER_WELL_REQ(id); u32 ret; @@ -370,7 +372,7 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id) static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - int id = power_well->id; + enum i915_power_well_id id = power_well->id; bool disabled; u32 reqs; @@ -837,7 +839,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, case CNL_DISP_PW_AUX_D: break; default: - WARN(1, "Unknown power well %lu\n", power_well->id); + WARN(1, "Unknown power well %u\n", power_well->id); return; } @@ -1089,7 +1091,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, static void vlv_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - enum punit_power_well power_well_id = power_well->id; + enum i915_power_well_id power_well_id = power_well->id; u32 mask; u32 state; u32 ctrl; @@ -1137,7 +1139,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv, static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - int power_well_id = power_well->id; + enum i915_power_well_id power_well_id = power_well->id; bool enabled = false; u32 mask; u32 state; @@ -1324,8 +1326,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) -static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, - int power_well_id) +static struct i915_power_well * +lookup_power_well(struct drm_i915_private *dev_priv, + enum i915_power_well_id power_well_id) { struct i915_power_domains *power_domains = &dev_priv->power_domains; int i; @@ -2117,7 +2120,7 @@ static struct i915_power_well vlv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = PUNIT_POWER_WELL_ALWAYS_ON, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2202,7 +2205,7 @@ static struct i915_power_well chv_power_wells[] = { }; bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, - int power_well_id) + enum i915_power_well_id power_well_id) { struct i915_power_well *power_well; bool ret; @@ -2219,7 +2222,7 @@ static struct i915_power_well skl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = SKL_DISP_PW_ALWAYS_ON, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", From 029d80d0fc676c4747502f6854d7c71ea8fa32bf Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:25 +0300 Subject: [PATCH 044/179] drm/i915: Assign everywhere the always-on power well ID Power well IDs are used for lookup so they must be unique. To ensure this assign the always-on power well ID everywhere where it's missing. This didn't cause a problem so far, since we didn't need to look up power wells that happened to share their IDs. Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-4-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 00ae25b59661..bbade8a5918f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2013,6 +2013,7 @@ static struct i915_power_well i9xx_always_on_power_well[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, }; @@ -2029,6 +2030,7 @@ static struct i915_power_well i830_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "pipes", @@ -2071,6 +2073,7 @@ static struct i915_power_well hsw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2085,6 +2088,7 @@ static struct i915_power_well bdw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2178,6 +2182,7 @@ static struct i915_power_well chv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2282,6 +2287,7 @@ static struct i915_power_well bxt_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", @@ -2323,6 +2329,7 @@ static struct i915_power_well glk_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", @@ -2408,6 +2415,7 @@ static struct i915_power_well cnl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", From 120b56a2a7a262c0940299615c7bcf97d3982711 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jul 2017 23:42:31 +0300 Subject: [PATCH 045/179] drm/i915/gen2: Add an ID for the display pipes power well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the I830 power well ID assignment explicit for consistency. v2: - s/GEN2/I830/ in the comment, since other GEN2s don't have the power well. (Ville) Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-2-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index aee40eecf688..ef0c1a86a52f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1072,6 +1072,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) * power wells their value must stay fixed. */ enum i915_power_well_id { + /* + * I830 + * - custom power well + */ + I830_DISP_PW_PIPES = 0, + /* * VLV/CHV * - PUNIT_REG_PWRGT_CTRL (bit: id*2), diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index bbade8a5918f..c36ec160b79f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2036,6 +2036,7 @@ static struct i915_power_well i830_power_wells[] = { .name = "pipes", .domains = I830_PIPES_POWER_DOMAINS, .ops = &i830_pipes_power_well_ops, + .id = I830_DISP_PW_PIPES, }, }; From fb9248e202df17cf731c76305f6015bf409179ca Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jul 2017 23:42:32 +0300 Subject: [PATCH 046/179] drm/i915/hsw, bdw: Add an ID for the global display power well Add an ID for the HSW/BDW global display power well for consistency. The ID is selected so that it can be used to get at the HW request and status flags with the corresponding GEN9+ macros. Unifying the HSW/BDW and GEN9+ versions of these macros and the power well ops using them will be done in follow-up patches. v2: - Rebased on v2 of patch 2. Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-3-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ef0c1a86a52f..23dc1b5328d0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1097,6 +1097,12 @@ enum i915_power_well_id { /* - custom power well */ CHV_DISP_PW_PIPE_A, /* 13 */ + /* + * HSW/BDW + * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) + */ + HSW_DISP_PW_GLOBAL = 15, + /* * GEN9+ * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index c36ec160b79f..7443a61ba0c5 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2080,6 +2080,7 @@ static struct i915_power_well hsw_power_wells[] = { .name = "display", .domains = HSW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, + .id = HSW_DISP_PW_GLOBAL, }, }; @@ -2095,6 +2096,7 @@ static struct i915_power_well bdw_power_wells[] = { .name = "display", .domains = BDW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, + .id = HSW_DISP_PW_GLOBAL, }, }; From 21792c6046f32113c9a6c3a0ab2177afe4f5fbe3 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jul 2017 23:42:33 +0300 Subject: [PATCH 047/179] drm/i915: Check for duplicated power well IDs Check that all the power well IDs are unique on the given platform. v2: - Fix using BIT_ULL() instead of BIT() for 64 bit mask. v3: - Move the check to a separate function. (Ville) Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-4-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 7443a61ba0c5..262c3fa886a9 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2548,6 +2548,22 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, return mask; } +static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) +{ + struct i915_power_domains *power_domains = &dev_priv->power_domains; + u64 power_well_ids; + int i; + + power_well_ids = 0; + for (i = 0; i < power_domains->power_well_count; i++) { + enum i915_power_well_id id = power_domains->power_wells[i].id; + + WARN_ON(id >= sizeof(power_well_ids) * 8); + WARN_ON(power_well_ids & BIT_ULL(id)); + power_well_ids |= BIT_ULL(id); + } +} + #define set_power_wells(power_domains, __power_wells) ({ \ (power_domains)->power_wells = (__power_wells); \ (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ @@ -2599,6 +2615,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) set_power_wells(power_domains, i9xx_always_on_power_well); } + assert_power_well_ids_unique(dev_priv); + return 0; } From b5565a2efc12e2cc04081a6de79ff537a530d64d Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:29 +0300 Subject: [PATCH 048/179] drm/i915/bxt, glk: Give a proper name to the power well struct phy field Follow-up patches will add new fields to the i915_power_well struct that are specific to the hsw_power_well_ops helpers. Prepare for this by changing the generic 'data' field to a union of platform specific structs. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-8-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 6 +++++- drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++----------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c4c02173b87c..eaedca57be38 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1388,7 +1388,11 @@ struct i915_power_well { * Arbitraty data associated with this power well. Platform and power * well specific. */ - unsigned long data; + union { + struct { + enum dpio_phy phy; + } bxt; + }; const struct i915_power_well_ops *ops; }; diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 262c3fa886a9..fc1377e7b149 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -963,19 +963,19 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv, static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - bxt_ddi_phy_init(dev_priv, power_well->data); + bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); } static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - bxt_ddi_phy_uninit(dev_priv, power_well->data); + bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); } static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return bxt_ddi_phy_is_enabled(dev_priv, power_well->data); + return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); } static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) @@ -984,16 +984,16 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); if (IS_GEMINILAKE(dev_priv)) { power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); } } @@ -2315,14 +2315,14 @@ static struct i915_power_well bxt_power_wells[] = { .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .data = DPIO_PHY1, + .bxt.phy = DPIO_PHY1, }, { .name = "dpio-common-bc", .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .data = DPIO_PHY0, + .bxt.phy = DPIO_PHY0, }, }; @@ -2358,21 +2358,21 @@ static struct i915_power_well glk_power_wells[] = { .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .data = DPIO_PHY1, + .bxt.phy = DPIO_PHY1, }, { .name = "dpio-common-b", .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .data = DPIO_PHY0, + .bxt.phy = DPIO_PHY0, }, { .name = "dpio-common-c", .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = GLK_DPIO_CMN_C, - .data = DPIO_PHY2, + .bxt.phy = DPIO_PHY2, }, { .name = "AUX A", From 2efbda7295f573a16a163affddfed849e097647b Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:30 +0300 Subject: [PATCH 049/179] drm/i915/gen9+: Remove redundant power well state assert during enabling We check already for power wells that are unexpectedly on (or forced on) during power well disabling. Those checks also account for other power well requesters like KVMR or DEBUG. As such this check is redundant, let's remove it to simplify things. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-9-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index fc1377e7b149..2fcf72760df7 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -852,13 +852,8 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, skl_power_well_pre_disable(dev_priv, power_well); if (enable) { - if (!enable_requested) { - WARN((tmp & state_mask) && - !I915_READ(HSW_PWR_WELL_BIOS), - "Invalid for power well status to be enabled, unless done by the BIOS, \ - when request is to disable!\n"); + if (!enable_requested) I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); - } if (!is_enabled) { DRM_DEBUG_KMS("Enabling %s\n", power_well->name); From 9137726abc3bc3217dd3adde67c1dce9a1a87c3f Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:31 +0300 Subject: [PATCH 050/179] drm/i915/gen9+: Remove redundant state check during power well toggling Atm we enable/disable a power well only if it wasn't already enabled/disabled respectively. The only reason for this I can think of is to save the extra MMIO writes. Since the HW state matches the power well's usage counter most of the time the overhead due to these MMIOs is insignificant. Let's simplify the code by making the writes unconditional. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-10-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 2fcf72760df7..763730febfde 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -806,7 +806,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, { uint32_t tmp, fuse_status; uint32_t req_mask, state_mask; - bool is_enabled, enable_requested, check_fuse_status = false; + bool check_fuse_status = false; tmp = I915_READ(HSW_PWR_WELL_DRIVER); fuse_status = I915_READ(SKL_FUSE_STATUS); @@ -844,29 +844,22 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, } req_mask = SKL_POWER_WELL_REQ(power_well->id); - enable_requested = tmp & req_mask; state_mask = SKL_POWER_WELL_STATE(power_well->id); - is_enabled = tmp & state_mask; - if (!enable && enable_requested) + if (!enable) skl_power_well_pre_disable(dev_priv, power_well); if (enable) { - if (!enable_requested) - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); - if (!is_enabled) { - DRM_DEBUG_KMS("Enabling %s\n", power_well->name); - check_fuse_status = true; - } + DRM_DEBUG_KMS("Enabling %s\n", power_well->name); + check_fuse_status = true; gen9_wait_for_power_well_enable(dev_priv, power_well); } else { - if (enable_requested) { - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Disabling %s\n", power_well->name); - } + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); + POSTING_READ(HSW_PWR_WELL_DRIVER); + DRM_DEBUG_KMS("Disabling %s\n", power_well->name); gen9_wait_for_power_well_disable(dev_priv, power_well); } @@ -889,7 +882,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, } } - if (enable && !is_enabled) + if (enable) skl_power_well_post_enable(dev_priv, power_well); } From 00742cabcc7a4f6bae03cef538c9bb020875115a Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:32 +0300 Subject: [PATCH 051/179] drm/i915/hsw, bdw: Remove redundant state check during power well toggling Similarly to the GEN9 power well toggling, saving an occasional extra MMIO write is not worth the code complexity, let's simplify things. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-11-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 36 +++++++++---------------- 1 file changed, 13 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 763730febfde..29988d8c0cf6 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -399,36 +399,26 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, static void hsw_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - bool is_enabled, enable_requested; uint32_t tmp; tmp = I915_READ(HSW_PWR_WELL_DRIVER); - is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; - enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; if (enable) { - if (!enable_requested) - I915_WRITE(HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_ENABLE_REQUEST); - - if (!is_enabled) { - DRM_DEBUG_KMS("Enabling power well\n"); - if (intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_STATE_ENABLED, - HSW_PWR_WELL_STATE_ENABLED, - 20)) - DRM_ERROR("Timeout enabling power well\n"); - hsw_power_well_post_enable(dev_priv); - } + I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST); + DRM_DEBUG_KMS("Enabling power well\n"); + if (intel_wait_for_register(dev_priv, + HSW_PWR_WELL_DRIVER, + HSW_PWR_WELL_STATE_ENABLED, + HSW_PWR_WELL_STATE_ENABLED, + 20)) + DRM_ERROR("Timeout enabling power well\n"); + hsw_power_well_post_enable(dev_priv); } else { - if (enable_requested) { - hsw_power_well_pre_disable(dev_priv); - I915_WRITE(HSW_PWR_WELL_DRIVER, 0); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Requesting to disable the power well\n"); - } + hsw_power_well_pre_disable(dev_priv); + I915_WRITE(HSW_PWR_WELL_DRIVER, 0); + POSTING_READ(HSW_PWR_WELL_DRIVER); + DRM_DEBUG_KMS("Requesting to disable the power well\n"); } } From ec46d48360432cbc9280e52692ec2f15bd85bdca Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:33 +0300 Subject: [PATCH 052/179] drm/i915/hsw, bdw: Split power well set to enable/disable helpers We can reduce the code indentation by splitting the set helper to separate enable/disable helpers. This also allows us to unify the HSW/BDW and GEN9+ power well ops in follow-up patches, which introduces some differences between the enable and disable helpers. While at it also remove the redundant enable/disable debug messages, the same info is printed already elsewhere. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-12-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 50 +++++++++---------------- 1 file changed, 17 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 29988d8c0cf6..1caba548a525 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -396,30 +396,26 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); } -static void hsw_set_power_well(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well, bool enable) +static void hsw_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { - uint32_t tmp; + I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST); - tmp = I915_READ(HSW_PWR_WELL_DRIVER); + if (intel_wait_for_register(dev_priv, + HSW_PWR_WELL_DRIVER, + HSW_PWR_WELL_STATE_ENABLED, + HSW_PWR_WELL_STATE_ENABLED, + 20)) + DRM_ERROR("Timeout enabling power well\n"); + hsw_power_well_post_enable(dev_priv); +} - if (enable) { - I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST); - - DRM_DEBUG_KMS("Enabling power well\n"); - if (intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_STATE_ENABLED, - HSW_PWR_WELL_STATE_ENABLED, - 20)) - DRM_ERROR("Timeout enabling power well\n"); - hsw_power_well_post_enable(dev_priv); - } else { - hsw_power_well_pre_disable(dev_priv); - I915_WRITE(HSW_PWR_WELL_DRIVER, 0); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Requesting to disable the power well\n"); - } +static void hsw_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + hsw_power_well_pre_disable(dev_priv); + I915_WRITE(HSW_PWR_WELL_DRIVER, 0); + POSTING_READ(HSW_PWR_WELL_DRIVER); } #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ @@ -889,18 +885,6 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, } } -static void hsw_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - hsw_set_power_well(dev_priv, power_well, true); -} - -static void hsw_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - hsw_set_power_well(dev_priv, power_well, false); -} - static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { From 1af474fef2697a1ab7e497627bddf026a3e767ac Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:34 +0300 Subject: [PATCH 053/179] drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros Although on HSW/BDW there is only a single display global power well, it's programmed the same way as other GEN9+ power wells. This also means we can get at the HSW/BDW request and status flags the same way it's done on GEN9+ by assigning the corresponding HSW/BDW power well ID. This ID was assigned in a recent patch, so we can now switch to using the same macros everywhere on HSW+. Updating the HSW power well control register with RMW is not strictly necessary, but this will allow us to use the same code for GEN9+. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-13-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gvt/handlers.c | 8 ++-- drivers/gpu/drm/i915/i915_reg.h | 8 ++-- drivers/gpu/drm/i915/intel_runtime_pm.c | 58 +++++++++++++++---------- 3 files changed, 44 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 17febe830ff6..aeecf315c5db 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1222,10 +1222,12 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, { write_vreg(vgpu, offset, p_data, bytes); - if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) - vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; + if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) + vgpu_vreg(vgpu, offset) |= + HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); else - vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; + vgpu_vreg(vgpu, offset) &= + ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); return 0; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 23dc1b5328d0..d7241a25a929 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1140,9 +1140,6 @@ enum i915_power_well_id { I915_DISP_PW_ALWAYS_ON = 20, }; -#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) -#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) - #define PUNIT_REG_PWRGT_CTRL 0x60 #define PUNIT_REG_PWRGT_STATUS 0x61 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) @@ -8016,8 +8013,9 @@ enum { #define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ #define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ #define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ -#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) -#define HSW_PWR_WELL_STATE_ENABLED (1<<30) +#define _HSW_PW_SHIFT(pw) ((pw) * 2) +#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) +#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 1caba548a525..483890186cc0 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -177,8 +177,10 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv, static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return I915_READ(HSW_PWR_WELL_DRIVER) == - (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); + enum i915_power_well_id id = power_well->id; + u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); + + return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; } /** @@ -350,15 +352,15 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv, /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ WARN_ON(intel_wait_for_register(dev_priv, HSW_PWR_WELL_DRIVER, - SKL_POWER_WELL_STATE(id), - SKL_POWER_WELL_STATE(id), + HSW_PWR_WELL_CTL_STATE(id), + HSW_PWR_WELL_CTL_STATE(id), 1)); } static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, enum i915_power_well_id id) { - u32 req_mask = SKL_POWER_WELL_REQ(id); + u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); u32 ret; ret = I915_READ(HSW_PWR_WELL_BIOS) & req_mask ? 1 : 0; @@ -386,7 +388,7 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, * diagnostic message. */ wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) & - SKL_POWER_WELL_STATE(id))) || + HSW_PWR_WELL_CTL_STATE(id))) || (reqs = gen9_power_well_requesters(dev_priv, id)), 1); if (disabled) return; @@ -399,12 +401,16 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, static void hsw_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST); + enum i915_power_well_id id = power_well->id; + u32 val; + + val = I915_READ(HSW_PWR_WELL_DRIVER); + I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id)); if (intel_wait_for_register(dev_priv, HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_STATE_ENABLED, - HSW_PWR_WELL_STATE_ENABLED, + HSW_PWR_WELL_CTL_STATE(id), + HSW_PWR_WELL_CTL_STATE(id), 20)) DRM_ERROR("Timeout enabling power well\n"); hsw_power_well_post_enable(dev_priv); @@ -413,8 +419,12 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, static void hsw_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { + enum i915_power_well_id id = power_well->id; + u32 val; + hsw_power_well_pre_disable(dev_priv); - I915_WRITE(HSW_PWR_WELL_DRIVER, 0); + val = I915_READ(HSW_PWR_WELL_DRIVER); + I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id)); POSTING_READ(HSW_PWR_WELL_DRIVER); } @@ -591,7 +601,7 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, "DC5 still not disabled to enable DC9.\n"); WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER) & - SKL_POWER_WELL_REQ(SKL_DISP_PW_2), + HSW_PWR_WELL_CTL_REQ(SKL_DISP_PW_2), "Power well 2 on.\n"); WARN_ONCE(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); @@ -829,8 +839,8 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, return; } - req_mask = SKL_POWER_WELL_REQ(power_well->id); - state_mask = SKL_POWER_WELL_STATE(power_well->id); + req_mask = HSW_PWR_WELL_CTL_REQ(power_well->id); + state_mask = HSW_PWR_WELL_CTL_STATE(power_well->id); if (!enable) skl_power_well_pre_disable(dev_priv, power_well); @@ -875,21 +885,25 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { + enum i915_power_well_id id = power_well->id; + u32 mask = HSW_PWR_WELL_CTL_REQ(id); + u32 bios_req = I915_READ(HSW_PWR_WELL_BIOS); + /* Take over the request bit if set by BIOS. */ - if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) { - if (!(I915_READ(HSW_PWR_WELL_DRIVER) & - HSW_PWR_WELL_ENABLE_REQUEST)) - I915_WRITE(HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_ENABLE_REQUEST); - I915_WRITE(HSW_PWR_WELL_BIOS, 0); + if (bios_req & mask) { + u32 drv_req = I915_READ(HSW_PWR_WELL_DRIVER); + + if (!(drv_req & mask)) + I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask); + I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask); } } static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - uint32_t mask = SKL_POWER_WELL_REQ(power_well->id) | - SKL_POWER_WELL_STATE(power_well->id); + uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id) | + HSW_PWR_WELL_CTL_STATE(power_well->id); return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; } @@ -897,7 +911,7 @@ static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - uint32_t mask = SKL_POWER_WELL_REQ(power_well->id); + uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id); uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS); /* Take over the request bit if set by BIOS. */ From 001bd2cb17f7df768fb3a5c1e7c3d2cd2cfb3439 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 12 Jul 2017 18:54:13 +0300 Subject: [PATCH 054/179] drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes The pattern of a power well backing a set of pipe IRQ or VGA functionality applies to all HSW+ platforms. Using power well attributes instead of platform checks to decide whether to init/reset pipe IRQs and VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and GEN9+ power well code in follow-up patches. Also use u8 for pipe_mask in related helpers to match the type in the power well struct. v2: - Use u8 instead of u32 for irq_pipe_mask. (Ville) v3: - Use u8 for pipe_mask in related helpers too for clarity. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/20170712155413.29839-1-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 6 +++++ drivers/gpu/drm/i915/i915_irq.c | 4 +-- drivers/gpu/drm/i915/intel_drv.h | 4 +-- drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +++++++++++++++---------- 4 files changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index eaedca57be38..1a43adb22162 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1392,6 +1392,12 @@ struct i915_power_well { struct { enum dpio_phy phy; } bxt; + struct { + /* Mask of pipes whose IRQ logic is backed by the pw */ + u8 irq_pipe_mask; + /* The pw is backing the VGA functionality */ + bool has_vga:1; + } hsw; }; const struct i915_power_well_ops *ops; }; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5244fb16fa55..9b46c6169d83 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3038,7 +3038,7 @@ static void gen8_irq_reset(struct drm_device *dev) } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask) + u8 pipe_mask) { uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; @@ -3052,7 +3052,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, } void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask) + u8 pipe_mask) { enum pipe pipe; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 021cc5487853..9c135f7a2868 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1230,9 +1230,9 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) int intel_get_crtc_scanline(struct intel_crtc *crtc); void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask); + u8 pipe_mask); void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask); + u8 pipe_mask); void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 483890186cc0..007e7019130c 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv, * to be enabled, and it will only be disabled if none of the registers is * requesting it to be enabled. */ -static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) +static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, + u8 irq_pipe_mask, bool has_vga) { struct pci_dev *pdev = dev_priv->drm.pdev; @@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) * sure vgacon can keep working normally without triggering interrupts * and error messages. */ - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); - vga_put(pdev, VGA_RSRC_LEGACY_IO); + if (has_vga) { + vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); + outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); + vga_put(pdev, VGA_RSRC_LEGACY_IO); + } - if (IS_BROADWELL(dev_priv)) - gen8_irq_power_well_post_enable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); + if (irq_pipe_mask) + gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); } -static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) +static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, + u8 irq_pipe_mask) { - if (IS_BROADWELL(dev_priv)) - gen8_irq_power_well_pre_disable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); + if (irq_pipe_mask) + gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); } static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -413,7 +415,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, HSW_PWR_WELL_CTL_STATE(id), 20)) DRM_ERROR("Timeout enabling power well\n"); - hsw_power_well_post_enable(dev_priv); + + hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, + power_well->hsw.has_vga); } static void hsw_power_well_disable(struct drm_i915_private *dev_priv, @@ -422,7 +426,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, enum i915_power_well_id id = power_well->id; u32 val; - hsw_power_well_pre_disable(dev_priv); + hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); + val = I915_READ(HSW_PWR_WELL_DRIVER); I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id)); POSTING_READ(HSW_PWR_WELL_DRIVER); @@ -2057,6 +2062,7 @@ static struct i915_power_well hsw_power_wells[] = { .domains = HSW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = HSW_DISP_PW_GLOBAL, + .hsw.has_vga = true, }, }; @@ -2073,6 +2079,8 @@ static struct i915_power_well bdw_power_wells[] = { .domains = BDW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = HSW_DISP_PW_GLOBAL, + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, }, }; From 76347c04d879267839337adc2aea6136b58c2ca7 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:36 +0300 Subject: [PATCH 055/179] drm/i915/hsw, bdw: Wait for the power well disabled state Similarly to GEN9+ waiting for the power well disabled state is a safer option and also provides diagnostic info if the disabling didn't succeed or the power well was forced on by an external requester. While at it also use the existing GEN9+ helper to wait for the enabled state. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-15-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++++++++--------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 007e7019130c..d1289be907d9 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -346,8 +346,8 @@ static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, 1 << PIPE_C | 1 << PIPE_B); } -static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { enum i915_power_well_id id = power_well->id; @@ -359,8 +359,8 @@ static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 1)); } -static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, - enum i915_power_well_id id) +static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, + enum i915_power_well_id id) { u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); u32 ret; @@ -373,8 +373,8 @@ static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, return ret; } -static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { enum i915_power_well_id id = power_well->id; bool disabled; @@ -391,7 +391,7 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, */ wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_CTL_STATE(id))) || - (reqs = gen9_power_well_requesters(dev_priv, id)), 1); + (reqs = hsw_power_well_requesters(dev_priv, id)), 1); if (disabled) return; @@ -408,13 +408,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, val = I915_READ(HSW_PWR_WELL_DRIVER); I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id)); - - if (intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_CTL_STATE(id), - HSW_PWR_WELL_CTL_STATE(id), - 20)) - DRM_ERROR("Timeout enabling power well\n"); + hsw_wait_for_power_well_enable(dev_priv, power_well); hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, power_well->hsw.has_vga); @@ -430,7 +424,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, val = I915_READ(HSW_PWR_WELL_DRIVER); I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id)); - POSTING_READ(HSW_PWR_WELL_DRIVER); + hsw_wait_for_power_well_disable(dev_priv, power_well); } #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ @@ -856,13 +850,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, DRM_DEBUG_KMS("Enabling %s\n", power_well->name); check_fuse_status = true; - gen9_wait_for_power_well_enable(dev_priv, power_well); + hsw_wait_for_power_well_enable(dev_priv, power_well); } else { I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); POSTING_READ(HSW_PWR_WELL_DRIVER); DRM_DEBUG_KMS("Disabling %s\n", power_well->name); - gen9_wait_for_power_well_disable(dev_priv, power_well); + hsw_wait_for_power_well_disable(dev_priv, power_well); } if (check_fuse_status) { From b2891eb2531e5e0d251febd0a395d758111790d4 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jul 2017 23:42:35 +0300 Subject: [PATCH 056/179] drm/i915/hsw+: Add has_fuses power well attribute The pattern of a power well backing a set of fuses whose initialization we need to wait for during power well enabling is common to all GEN9+ platforms. Adding support for this to the HSW power well enable helper allows us to use the HSW/BDW power well code for GEN9+ as well in a follow-up patch. v2: - Use an enum for power gates instead of raw numbers. (Ville) Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-6-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gvt/display.c | 6 ++-- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 14 ++++++--- drivers/gpu/drm/i915/intel_runtime_pm.c | 41 ++++++++++++++++++++----- 4 files changed, 48 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 2deb05f618fb..24cc4b012e93 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SDE_PORTE_HOTPLUG_SPT); vgpu_vreg(vgpu, SKL_FUSE_STATUS) |= SKL_FUSE_DOWNLOAD_STATUS | - SKL_FUSE_PG0_DIST_STATUS | - SKL_FUSE_PG1_DIST_STATUS | - SKL_FUSE_PG2_DIST_STATUS; + SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG2); vgpu_vreg(vgpu, LCPLL1_CTL) |= LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1a43adb22162..0ac66a4c361f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1397,6 +1397,7 @@ struct i915_power_well { u8 irq_pipe_mask; /* The pw is backing the VGA functionality */ bool has_vga:1; + bool has_fuses:1; } hsw; }; const struct i915_power_well_ops *ops; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d7241a25a929..c83f1095cb21 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8023,11 +8023,17 @@ enum { #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) /* SKL Fuse Status */ +enum skl_power_gate { + SKL_PG0, + SKL_PG1, + SKL_PG2, +}; + #define SKL_FUSE_STATUS _MMIO(0x42000) -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) -#define SKL_FUSE_PG0_DIST_STATUS (1<<27) -#define SKL_FUSE_PG1_DIST_STATUS (1<<26) -#define SKL_FUSE_PG2_DIST_STATUS (1<<25) +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */ +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index d1289be907d9..3992de3c9f01 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -400,16 +400,43 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); } +static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, + enum skl_power_gate pg) +{ + /* Timeout 5us for PG#0, for other PGs 1us */ + WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, + SKL_FUSE_PG_DIST_STATUS(pg), + SKL_FUSE_PG_DIST_STATUS(pg), 1)); +} + static void hsw_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { enum i915_power_well_id id = power_well->id; + bool wait_fuses = power_well->hsw.has_fuses; + enum skl_power_gate pg; u32 val; + if (wait_fuses) { + pg = SKL_PW_TO_PG(id); + /* + * For PW1 we have to wait both for the PW0/PG0 fuse state + * before enabling the power well and PW1/PG1's own fuse + * state after the enabling. For all other power wells with + * fuses we only have to wait for that PW/PG's fuse state + * after the enabling. + */ + if (pg == SKL_PG1) + gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); + } + val = I915_READ(HSW_PWR_WELL_DRIVER); I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id)); hsw_wait_for_power_well_enable(dev_priv, power_well); + if (wait_fuses) + gen9_wait_for_power_well_fuses(dev_priv, pg); + hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, power_well->hsw.has_vga); } @@ -810,15 +837,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, case SKL_DISP_PW_1: if (intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, - SKL_FUSE_PG0_DIST_STATUS, - SKL_FUSE_PG0_DIST_STATUS, + SKL_FUSE_PG_DIST_STATUS(SKL_PG0), + SKL_FUSE_PG_DIST_STATUS(SKL_PG0), 1)) { DRM_ERROR("PG0 not enabled\n"); return; } break; case SKL_DISP_PW_2: - if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { + if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(SKL_PG1))) { DRM_ERROR("PG1 in disabled state\n"); return; } @@ -863,15 +890,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, if (power_well->id == SKL_DISP_PW_1) { if (intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, - SKL_FUSE_PG1_DIST_STATUS, - SKL_FUSE_PG1_DIST_STATUS, + SKL_FUSE_PG_DIST_STATUS(SKL_PG1), + SKL_FUSE_PG_DIST_STATUS(SKL_PG1), 1)) DRM_ERROR("PG1 distributing status timeout\n"); } else if (power_well->id == SKL_DISP_PW_2) { if (intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, - SKL_FUSE_PG2_DIST_STATUS, - SKL_FUSE_PG2_DIST_STATUS, + SKL_FUSE_PG_DIST_STATUS(SKL_PG2), + SKL_FUSE_PG_DIST_STATUS(SKL_PG2), 1)) DRM_ERROR("PG2 distributing status timeout\n"); } From 4196b9185d3911724388bb3a597ff8c690012c9c Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jul 2017 23:42:36 +0300 Subject: [PATCH 057/179] drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers After the previous refactorings the HSW/BDW and GEN9+ power well helpers are practically identical, so use the HSW power well helpers for GEN9+ too. This means using the HSW power well ops instead of the SKL one and setting the irq_pipe_mask, has_vga and has_fuses attributes as needed. v2: - Rebased on v2 of patch 15. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-7-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 231 +++++------------------- 1 file changed, 43 insertions(+), 188 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3992de3c9f01..a5c0fcb09997 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -313,38 +313,6 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); } -static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - struct pci_dev *pdev = dev_priv->drm.pdev; - - /* - * After we re-enable the power well, if we touch VGA register 0x3d5 - * we'll get unclaimed register interrupts. This stops after we write - * anything to the VGA MSR register. The vgacon module uses this - * register all the time, so if we unbind our driver and, as a - * consequence, bind vgacon, we'll get stuck in an infinite loop at - * console_unlock(). So make here we touch the VGA MSR register, making - * sure vgacon can keep working normally without triggering interrupts - * and error messages. - */ - if (power_well->id == SKL_DISP_PW_2) { - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); - vga_put(pdev, VGA_RSRC_LEGACY_IO); - - gen8_irq_power_well_post_enable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); - } -} - -static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - if (power_well->id == SKL_DISP_PW_2) - gen8_irq_power_well_pre_disable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); -} static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) @@ -823,91 +791,6 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); } -static void skl_set_power_well(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well, bool enable) -{ - uint32_t tmp, fuse_status; - uint32_t req_mask, state_mask; - bool check_fuse_status = false; - - tmp = I915_READ(HSW_PWR_WELL_DRIVER); - fuse_status = I915_READ(SKL_FUSE_STATUS); - - switch (power_well->id) { - case SKL_DISP_PW_1: - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG_DIST_STATUS(SKL_PG0), - SKL_FUSE_PG_DIST_STATUS(SKL_PG0), - 1)) { - DRM_ERROR("PG0 not enabled\n"); - return; - } - break; - case SKL_DISP_PW_2: - if (!(fuse_status & SKL_FUSE_PG_DIST_STATUS(SKL_PG1))) { - DRM_ERROR("PG1 in disabled state\n"); - return; - } - break; - case SKL_DISP_PW_MISC_IO: - case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */ - case SKL_DISP_PW_DDI_B: - case SKL_DISP_PW_DDI_C: - case SKL_DISP_PW_DDI_D: - case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */ - case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */ - case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */ - case CNL_DISP_PW_AUX_D: - break; - default: - WARN(1, "Unknown power well %u\n", power_well->id); - return; - } - - req_mask = HSW_PWR_WELL_CTL_REQ(power_well->id); - state_mask = HSW_PWR_WELL_CTL_STATE(power_well->id); - - if (!enable) - skl_power_well_pre_disable(dev_priv, power_well); - - if (enable) { - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); - - DRM_DEBUG_KMS("Enabling %s\n", power_well->name); - check_fuse_status = true; - - hsw_wait_for_power_well_enable(dev_priv, power_well); - } else { - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Disabling %s\n", power_well->name); - - hsw_wait_for_power_well_disable(dev_priv, power_well); - } - - if (check_fuse_status) { - if (power_well->id == SKL_DISP_PW_1) { - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG_DIST_STATUS(SKL_PG1), - SKL_FUSE_PG_DIST_STATUS(SKL_PG1), - 1)) - DRM_ERROR("PG1 distributing status timeout\n"); - } else if (power_well->id == SKL_DISP_PW_2) { - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG_DIST_STATUS(SKL_PG2), - SKL_FUSE_PG_DIST_STATUS(SKL_PG2), - 1)) - DRM_ERROR("PG2 distributing status timeout\n"); - } - } - - if (enable) - skl_power_well_post_enable(dev_priv, power_well); -} - static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { @@ -925,43 +808,6 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, } } -static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id) | - HSW_PWR_WELL_CTL_STATE(power_well->id); - - return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; -} - -static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - uint32_t mask = HSW_PWR_WELL_CTL_REQ(power_well->id); - uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS); - - /* Take over the request bit if set by BIOS. */ - if (bios_req & mask) { - uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER); - - if (!(drv_req & mask)) - I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask); - I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask); - } -} - -static void skl_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - skl_set_power_well(dev_priv, power_well, true); -} - -static void skl_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - skl_set_power_well(dev_priv, power_well, false); -} - static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { @@ -2049,13 +1895,6 @@ static const struct i915_power_well_ops hsw_power_well_ops = { .is_enabled = hsw_power_well_enabled, }; -static const struct i915_power_well_ops skl_power_well_ops = { - .sync_hw = skl_power_well_sync_hw, - .enable = skl_power_well_enable, - .disable = skl_power_well_disable, - .is_enabled = skl_power_well_enabled, -}; - static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = gen9_dc_off_power_well_enable, @@ -2241,14 +2080,15 @@ static struct i915_power_well skl_power_wells[] = { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + .hsw.has_fuses = true, }, { .name = "MISC IO power well", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_MISC_IO, }, { @@ -2260,31 +2100,34 @@ static struct i915_power_well skl_power_wells[] = { { .name = "power well 2", .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, }, { .name = "DDI A/E IO power well", .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_A_E, }, { .name = "DDI B IO power well", .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, { .name = "DDI D IO power well", .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_D, }, }; @@ -2300,8 +2143,9 @@ static struct i915_power_well bxt_power_wells[] = { { .name = "power well 1", .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + .hsw.has_fuses = true, }, { .name = "DC off", @@ -2312,8 +2156,11 @@ static struct i915_power_well bxt_power_wells[] = { { .name = "power well 2", .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, }, { .name = "dpio-common-a", @@ -2343,8 +2190,9 @@ static struct i915_power_well glk_power_wells[] = { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + .hsw.has_fuses = true, }, { .name = "DC off", @@ -2355,8 +2203,11 @@ static struct i915_power_well glk_power_wells[] = { { .name = "power well 2", .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, }, { .name = "dpio-common-a", @@ -2382,37 +2233,37 @@ static struct i915_power_well glk_power_wells[] = { { .name = "AUX A", .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_A, }, { .name = "AUX B", .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_B, }, { .name = "AUX C", .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_C, }, { .name = "DDI A IO power well", .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_DDI_A, }, { .name = "DDI B IO power well", .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, }; @@ -2429,31 +2280,32 @@ static struct i915_power_well cnl_power_wells[] = { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + .hsw.has_fuses = true, }, { .name = "AUX A", .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_A, }, { .name = "AUX B", .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_B, }, { .name = "AUX C", .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_C, }, { .name = "AUX D", .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_D, }, { @@ -2465,31 +2317,34 @@ static struct i915_power_well cnl_power_wells[] = { { .name = "power well 2", .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, }, { .name = "DDI A IO power well", .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_DDI_A, }, { .name = "DDI B IO power well", .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, { .name = "DDI D IO power well", .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_D, }, }; From d42539ba4ffc317acd769eec0c19fc59c8319e65 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:39 +0300 Subject: [PATCH 058/179] drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers Move the helper next to the rest of HSW specific code. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-18-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++++++++++------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index a5c0fcb09997..3f24483071af 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -169,20 +169,6 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv, intel_power_well_disable(dev_priv, power_well); } -/* - * We should only use the power well if we explicitly asked the hardware to - * enable it, so check if it's enabled and also check if we've requested it to - * be enabled. - */ -static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - enum i915_power_well_id id = power_well->id; - u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); - - return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; -} - /** * __intel_display_power_is_enabled - unlocked check for a power domain * @dev_priv: i915 device instance @@ -422,6 +408,20 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, hsw_wait_for_power_well_disable(dev_priv, power_well); } +/* + * We should only use the power well if we explicitly asked the hardware to + * enable it, so check if it's enabled and also check if we've requested it to + * be enabled. + */ +static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum i915_power_well_id id = power_well->id; + u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); + + return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; +} + #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ BIT_ULL(POWER_DOMAIN_PIPE_B) | \ From 965a79ad417f9ed6304fd106ffd3dbd1cc65ecfc Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 6 Jul 2017 17:40:40 +0300 Subject: [PATCH 059/179] drm/i915: Gather all the power well->domain mappings to one place Shuffle the power well->domain mapping macros around so they are at one place in old->new GEN order. Signed-off-by: Imre Deak Reviewed-by: Arkadiusz Hiler Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-19-git-send-email-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 408 ++++++++++++------------ 1 file changed, 204 insertions(+), 204 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3f24483071af..a709a686b978 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -422,172 +422,6 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; } -#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) - -#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_GMBUS) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) - -#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) -#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) -#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) -#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) - -#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) - static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) { WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), @@ -1712,37 +1546,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, intel_runtime_pm_put(dev_priv); } -#define HSW_DISPLAY_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) - -#define BDW_DISPLAY_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ +#define I830_PIPES_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ BIT_ULL(POWER_DOMAIN_INIT)) #define VLV_DISPLAY_POWER_DOMAINS ( \ @@ -1825,13 +1635,203 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_AUX_D) | \ BIT_ULL(POWER_DOMAIN_INIT)) -#define I830_PIPES_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ +#define HSW_DISPLAY_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define BDW_DISPLAY_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_GMBUS) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) +#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) +#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) +#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { From 60436fd4d263f23fd4d7805b8d4b8bbb5eef5bd1 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 21 Jul 2017 20:55:04 +0530 Subject: [PATCH 060/179] drm/i915: add config function for YCBCR420 outputs This patch checks encoder level support for YCBCR420 outputs. The logic goes as simple as this: If the input mode is YCBCR420-only mode: prepare HDMI for YCBCR420 output, else continue with RGB output mode. It checks if the mode is YCBCR420 and source can support this output then it marks the ycbcr_420 output indicator into crtc state, for further staging in driver. V2: Split the patch into two, kept helper functions in DRM layer. V3: Changed the compute_config function based on new DRM API. V4: Rebase V5: Rebase V6: Check and handle YCBCR420-only modes, discard the property based approach (Ville) V7: Addressed review comments from Ville - add else case in 12BPC check. - extract ycbcr420 state inside hdmi_12bpc_possible function. V8: Addressed review comments from Ville - Remove extra blank lines. - Remove "HDMI" from the description of ycbcr420 state variable. - Remove local variable, use crtc_state->ycbcr420 instead. Added r-b from Ville. V9: Rebase V10: Added r-b from Imre Cc: Ville Syrjala Cc: Daniel Vetter Cc: Ander Conselvan de Oliveira Reviewed-by: Ville Syrjala Reviewed-by: Imre Deak Signed-off-by: Shashank Sharma Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1500650709-14447-2-git-send-email-shashank.sharma@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 3 +++ drivers/gpu/drm/i915/intel_hdmi.c | 40 +++++++++++++++++++++++++--- 3 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6c823cc02db3..6908d3b4218a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10969,6 +10969,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_I(hdmi_scrambling); PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); PIPE_CONF_CHECK_I(has_infoframe); + PIPE_CONF_CHECK_I(ycbcr420); PIPE_CONF_CHECK_I(has_audio); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9c135f7a2868..ee0daecff713 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -780,6 +780,9 @@ struct intel_crtc_state { /* HDMI High TMDS char rate ratio */ bool hdmi_high_tmds_clock_ratio; + + /* output format is YCBCR 4:2:0 */ + bool ycbcr420; }; struct intel_crtc { diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 2f831cfdd243..0b63b9fcbcc1 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1330,8 +1330,15 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) if (connector_state->crtc != crtc_state->base.crtc) continue; - if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0) - return false; + if (crtc_state->ycbcr420) { + const struct drm_hdmi_info *hdmi = &info->hdmi; + + if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) + return false; + } else { + if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36)) + return false; + } } /* Display Wa #1139 */ @@ -1342,6 +1349,24 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) return true; } +static bool +intel_hdmi_ycbcr420_config(struct drm_connector *connector, + struct intel_crtc_state *config, + int *clock_12bpc, int *clock_8bpc) +{ + if (!connector->ycbcr_420_allowed) { + DRM_ERROR("Platform doesn't support YCBCR420 output\n"); + return false; + } + + /* YCBCR420 TMDS rate requirement is half the pixel clock */ + config->port_clock /= 2; + *clock_12bpc /= 2; + *clock_8bpc /= 2; + config->ycbcr420 = true; + return true; +} + bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) @@ -1349,7 +1374,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; - struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; + struct drm_connector *connector = conn_state->connector; + struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; struct intel_digital_connector_state *intel_conn_state = to_intel_digital_connector_state(conn_state); int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; @@ -1379,6 +1405,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, clock_12bpc *= 2; } + if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { + if (!intel_hdmi_ycbcr420_config(connector, pipe_config, + &clock_12bpc, &clock_8bpc)) { + DRM_ERROR("Can't support YCBCR420 output\n"); + return false; + } + } + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) pipe_config->has_pch_encoder = true; From e5c059316cb2e443710a63e9a60a0f84bfc0fce2 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 21 Jul 2017 20:55:05 +0530 Subject: [PATCH 061/179] drm/i915: prepare scaler for YCBCR420 modeset To get a YCBCR420 output from intel platforms, we need one scaler to scale down YCBCR444 samples to YCBCR420 samples. This patch: - Does scaler allocation for HDMI ycbcr420 outputs. - Programs PIPE_MISC register for ycbcr420 output. V2: rebase V3: rebase V4: rebase V5: addressed review comments from Ander: - No need to check both scaler_user && hdmi_output. Check for scaler_user is enough. V6: rebase V7: Do not create a new scaler user, use existing pipe scaler user. V8: rebase V9: Addressed review comments from Ville: - Remove leftover comment for HDMI scaler user. - Remove unnecessary blank line. - Make scaler alocation failure a DEBUG log instead of ERROR. Added r-b from Ville V10: Update commit message as per latest code (Imre) Added r-b from Imre Cc: Ville Syrjala Cc: Ander Conselvan De Oliveira Cc: Imre Deak Reviewed-by: Ville Syrjala Reviewed-by: Imre Deak Signed-off-by: Shashank Sharma Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1500650709-14447-3-git-send-email-shashank.sharma@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 +++ drivers/gpu/drm/i915/intel_hdmi.c | 12 ++++++++++++ drivers/gpu/drm/i915/intel_panel.c | 3 ++- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6908d3b4218a..77d811993423 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4487,6 +4487,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, */ need_scaling = src_w != dst_w || src_h != dst_h; + if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) + need_scaling = true; + /* * Scaling/fitting not supported in IF-ID mode in GEN9+ * TODO: Interlace fetch mode doesn't support YUV420 planar formats. diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 0b63b9fcbcc1..b62bd8251c2a 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1354,6 +1354,8 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector, struct intel_crtc_state *config, int *clock_12bpc, int *clock_8bpc) { + struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); + if (!connector->ycbcr_420_allowed) { DRM_ERROR("Platform doesn't support YCBCR420 output\n"); return false; @@ -1364,6 +1366,16 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector, *clock_12bpc /= 2; *clock_8bpc /= 2; config->ycbcr420 = true; + + /* YCBCR 420 output conversion needs a scaler */ + if (skl_update_scaler_crtc(config)) { + DRM_DEBUG_KMS("Scaler allocation for output failed\n"); + return false; + } + + intel_pch_panel_fitting(intel_crtc, config, + DRM_MODE_SCALE_FULLSCREEN); + return true; } diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 96c2cbd81869..fd2e0815f06a 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -110,7 +110,8 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc, /* Native modes don't need fitting */ if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && - adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) + adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h && + !pipe_config->ycbcr420) goto done; switch (fitting_mode) { From b22ca995ba1cbe7a04141450b78215e41c361ffa Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Mon, 24 Jul 2017 19:19:32 +0530 Subject: [PATCH 062/179] drm/i915: prepare pipe for YCBCR420 output To get HDMI YCBCR420 output, the PIPEMISC register should be programmed to: - Generate YCBCR output (bit 11) - In case of YCBCR420 outputs, it should be programmed in full blend mode to use the scaler in 5x3 ratio (bits 26 and 27) This patch: - Adds definition of these bits. - Programs PIPEMISC for YCBCR420 outputs. - Adds readouts to compare HW and SW states. V2: rebase V3: rebase V4: rebase V5: added r-b from Ander V6: Handle only YCBCR420 outputs (ville) V7: rebase V8: Addressed review comments from Ville - Add readouts for state->ycbcr420 and 420 pixel_clock. - Handle warning due to mismatch in clock for ycbcr420 clock. - Rename PIPEMISC macros to match the Bspec. - Add a debug print stating if YCBCR 4:2:0 output enabled. Added r-b from Ville V9: Addressed review comments from Imre: - Add 420 mode clock adjustment in intel_hdmi_mode_valid to prevent 420_only modes getting rejected for high clock. - Add port clock adjustment for ycbcr420 modes in ddi_get_clock - Rename macros as per Ville's suggestion. - Remove unnecessary wl changes. V10: Added r-b from Imre V11: Fixed faulty dotclock handling, and addressed missing comment from previous set of review comments (Imre) V12: Fixed dotclock for 12bpc too, removed 420 check for GEN < 10 Cc: Ville Syrjala Cc: Ander Conselvan de Oliveira Cc: Daniel Vetter Cc: Imre Deak Reviewed-by: Ander Conselvan de Oliveira Reviewed-by: Ville Syrjala Reviewed-by: Imre Deak Signed-off-by: Shashank Sharma Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1500904172-31717-1-git-send-email-shashank.sharma@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_ddi.c | 3 +++ drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_hdmi.c | 3 +++ 4 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c83f1095cb21..67be8eb57065 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5252,6 +5252,9 @@ enum { #define _PIPE_MISC_A 0x70030 #define _PIPE_MISC_B 0x71030 +#define PIPEMISC_YUV420_ENABLE (1<<27) +#define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26) +#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11) #define PIPEMISC_DITHER_BPC_MASK (7<<5) #define PIPEMISC_DITHER_8_BPC (0<<5) #define PIPEMISC_DITHER_10_BPC (1<<5) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index efb13582dc73..4a0e35ede643 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1174,6 +1174,9 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) else dotclock = pipe_config->port_clock; + if (pipe_config->ycbcr420) + dotclock *= 2; + if (pipe_config->pixel_multiplier) dotclock /= pipe_config->pixel_multiplier; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 77d811993423..146b8173e365 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7933,6 +7933,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_crtc_state *config = intel_crtc->config; if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { u32 val = 0; @@ -7958,6 +7959,12 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) if (intel_crtc->config->dither) val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; + if (config->ycbcr420) { + val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | + PIPEMISC_YUV420_ENABLE | + PIPEMISC_YUV420_MODE_FULL_BLEND; + } + I915_WRITE(PIPEMISC(intel_crtc->pipe), val); } } @@ -9022,6 +9029,23 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; + if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) { + u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); + bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; + + if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) { + bool blend_mode_420 = tmp & + PIPEMISC_YUV420_MODE_FULL_BLEND; + + pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; + if (pipe_config->ycbcr420 != clrspace_yuv || + pipe_config->ycbcr420 != blend_mode_420) + DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); + } else if (clrspace_yuv) { + DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); + } + } + power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); @@ -10401,6 +10425,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->fdi_lanes, &pipe_config->fdi_m_n); + if (pipe_config->ycbcr420) + DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); + if (intel_crtc_has_dp_encoder(pipe_config)) { intel_dump_m_n_config(pipe_config, "dp m_n", pipe_config->lane_count, &pipe_config->dp_m_n); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index b62bd8251c2a..b0b6dd19a70d 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1295,6 +1295,9 @@ intel_hdmi_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) clock *= 2; + if (drm_mode_is_420_only(&connector->display_info, mode)) + clock /= 2; + /* check if we can do 8bpc */ status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); From 25edf91501b878f548ff1c96692e54684b0f586a Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 21 Jul 2017 20:55:07 +0530 Subject: [PATCH 063/179] drm/i915: prepare csc unit for YCBCR420 output To support ycbcr output, we need a pipe CSC block to do RGB->YCBCR conversion. Current Intel platforms have only one pipe CSC unit, so we can either do color correction using it, or we can perform RGB->YCBCR conversion. This function adds a csc handler, which uses recommended bspec values to perform RGB->YCBCR conversion (target color space BT709) V2: Rebase V3: Rebase V4: Rebase V5: Addressed review comments from Ander - Remove extra line added in the patch - Add the spec details in the commit message - Combine two if(cond) while calling intel_crtc_compute_config V6: Handle YCBCR420 outputs only (Ville) V7: Addressed review comments from Ville: - Add description about target colorspace - Remove the comments from CSC function - DRM_DEBUG->DEBUG_KMS for atomic failure due to CSC unit busy - Remove unnecessary debug message about YCBCR420 possibe V8: Addressed review comments from Ville: - Remove extra comment, not required. - Do not add extra variable for CTM, reuse pipe_config Added r-b from Ville V9: Remove extra whitespace (Imre) V10: Added r-b from Imre Cc: Ville Syrjala Cc: Daniel Vetter Cc: Ander Conselvan de Oliveira Cc: Imre Deak Reviewed-by: Ville Syrjala Reviewed-by: Imre Deak Signed-off-by: Shashank Sharma Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1500650709-14447-5-git-send-email-shashank.sharma@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_color.c | 45 +++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_display.c | 10 +++++++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index f85d57555957..30ed70c3846d 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -41,6 +41,22 @@ #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256) +/* Post offset values for RGB->YCBCR conversion */ +#define POSTOFF_RGB_TO_YUV_HI 0x800 +#define POSTOFF_RGB_TO_YUV_ME 0x100 +#define POSTOFF_RGB_TO_YUV_LO 0x800 + +/* + * These values are direct register values specified in the Bspec, + * for RGB->YUV conversion matrix (colorspace BT709) + */ +#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8 +#define CSC_RGB_TO_YUV_BU 0x37e80000 +#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0 +#define CSC_RGB_TO_YUV_BY 0xb5280000 +#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 +#define CSC_RGB_TO_YUV_BV 0x1e080000 + /* * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point * format). This macro takes the coefficient we want transformed and the @@ -91,6 +107,30 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input) } } +void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc) +{ + int pipe = intel_crtc->pipe; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + + I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); + I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); + I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); + + I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU); + I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU); + + I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY); + I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY); + + I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV); + I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV); + + I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI); + I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME); + I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO); + I915_WRITE(PIPE_CSC_MODE(pipe), 0); +} + /* Set up the pipe CSC unit. */ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) { @@ -101,7 +141,10 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) uint16_t coeffs[9] = { 0, }; struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state); - if (crtc_state->ctm) { + if (intel_crtc_state->ycbcr420) { + i9xx_load_ycbcr_conversion_matrix(intel_crtc); + return; + } else if (crtc_state->ctm) { struct drm_color_ctm *ctm = (struct drm_color_ctm *)crtc_state->ctm->data; uint64_t input[9] = { 0, }; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 146b8173e365..f7b128c33aa1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6140,6 +6140,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, return -EINVAL; } + if (pipe_config->ycbcr420 && pipe_config->base.ctm) { + /* + * There is only one pipe CSC unit per pipe, and we need that + * for output conversion from RGB->YCBCR. So if CTM is already + * applied we can't support YCBCR420 output. + */ + DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); + return -EINVAL; + } + /* * Pipe horizontal size must be even in: * - DVO ganged mode From 2d8bd2bf0d8eb752a58784ca890643176f595651 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 21 Jul 2017 20:55:08 +0530 Subject: [PATCH 064/179] drm/i915: set colorspace for YCBCR420 outputs When output colorspace is YCBCR420, we have to load the corresponding colorspace in AVI infoframe. This patch fills the colorspace of AVI infoframe as per the output mode. V2: Rebase V3: Rebase V4: Rebase V5: Added r-b from Ander V6: Checking RGB/YCBCR420 output only (Ville) V7: Add colorspace info in driver(not drm layer) (Ville) V8: Rebase V9: Added r-b from Ville V10: Added r-b from Imre Cc: Ville Syrjala Cc: Ander Conselvan de Oliveira Cc: Imre Deak Reviewed-by: Ander Conselvan de Oliveira Reviewed-by: Ville Syrjala Reviewed-by: Imre Deak Signed-off-by: Shashank Sharma Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1500650709-14447-6-git-send-email-shashank.sharma@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index b0b6dd19a70d..a025a9d08264 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -472,12 +472,18 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, return; } + if (crtc_state->ycbcr420) + frame.avi.colorspace = HDMI_COLORSPACE_YUV420; + else + frame.avi.colorspace = HDMI_COLORSPACE_RGB; + drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, crtc_state->limited_color_range ? HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL, intel_hdmi->rgb_quant_range_selectable); + /* TODO: handle pixel repetition for YCBCR420 outputs */ intel_write_infoframe(encoder, crtc_state, &frame); } From eadc2e51fd1bfdb06f1e74fbb129dd18f40155b1 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 21 Jul 2017 20:55:09 +0530 Subject: [PATCH 065/179] drm/i915/glk: set HDMI 2.0 identifier This patch sets the is_hdmi2_src identifier in drm connector for GLK platform. GLK contains a native HDMI 2.0 controller. This identifier will help the EDID handling functions to save lot of work which is specific to HDMI 2.0 sources. V3: Added this patch V4: Rebase V4: Rebase V5: Added r-b from Ander V6: Rebase V7: Rebase V8: Rebase V9: Added r-b from Ville V9: Added r-b from Imre Cc: Ville Syrjala Cc: Ander Conselvan de Oliveira Cc: Imre Deak Reviewed-by: Ander Conselvan de Oliveira Reviewed-by: Ville Syrjala Reviewed-by: Imre Deak Signed-off-by: Shashank Sharma Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/1500650709-14447-7-git-send-email-shashank.sharma@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index a025a9d08264..5609976539bf 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1917,6 +1917,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, connector->doublescan_allowed = 0; connector->stereo_allowed = 1; + if (IS_GEMINILAKE(dev_priv)) + connector->ycbcr_420_allowed = true; + intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); switch (port) { From 6492ca79c823f508d3b28526b419c9c584388970 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 17:11:01 +0100 Subject: [PATCH 066/179] drm/i915: Enforce that CS packets are qword aligned We require the caller to ensure that the packets they wish to emit into the CS ring are qword aligned (i.e. have an even number of dwords). Double check this. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20170721161101.1618-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5224b7abb8a3..cdf084ef5aae 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1712,6 +1712,9 @@ u32 *intel_ring_begin(struct drm_i915_gem_request *req, unsigned int total_bytes; u32 *cs; + /* Packets must be qword aligned. */ + GEM_BUG_ON(num_dwords & 1); + total_bytes = bytes + req->reserved_space; GEM_BUG_ON(total_bytes > ring->effective_size); From d1d1ebf4120db07a6706faed970be7460303834e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:33 +0100 Subject: [PATCH 067/179] drm/i915: Don't touch fence->error when resetting an innocent request If the request has been completed before the reset took effect, we don't need to mark it up as being a victim. Touching fence->error after the fence has been signaled is detected by dma_fence_set_error() and triggers a BUG: [ 231.743133] kernel BUG at ./include/linux/dma-fence.h:434! [ 231.743156] invalid opcode: 0000 [#1] SMP KASAN [ 231.743172] Modules linked in: i915 drm_kms_helper drm iptable_nat nf_nat_ipv4 nf_nat x86_pkg_temp_thermal iosf_mbi i2c_algo_bit cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea fb font fbdev [last unloaded: drm] [ 231.743221] CPU: 2 PID: 20 Comm: kworker/2:0 Tainted: G U 4.13.0-rc1+ #52 [ 231.743236] Hardware name: Hewlett-Packard HP EliteBook 8460p/161C, BIOS 68SCF Ver. F.01 03/11/2011 [ 231.743363] Workqueue: events_long i915_hangcheck_elapsed [i915] [ 231.743382] task: ffff8801f42e9780 task.stack: ffff8801f42f8000 [ 231.743489] RIP: 0010:i915_gem_reset_engine+0x45a/0x460 [i915] [ 231.743505] RSP: 0018:ffff8801f42ff770 EFLAGS: 00010202 [ 231.743521] RAX: 0000000000000007 RBX: ffff8801bf6b1880 RCX: ffffffffa02881a6 [ 231.743537] RDX: dffffc0000000000 RSI: dffffc0000000000 RDI: ffff8801bf6b18c8 [ 231.743551] RBP: ffff8801f42ff7c8 R08: 0000000000000001 R09: 0000000000000000 [ 231.743566] R10: 0000000000000000 R11: 0000000000000000 R12: ffff8801edb02d00 [ 231.743581] R13: ffff8801e19d4200 R14: 000000000000001d R15: ffff8801ce2a4000 [ 231.743599] FS: 0000000000000000(0000) GS:ffff8801f5a80000(0000) knlGS:0000000000000000 [ 231.743614] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 231.743629] CR2: 00007f0ebd1add10 CR3: 0000000002621000 CR4: 00000000000406e0 [ 231.743643] Call Trace: [ 231.743752] i915_gem_reset+0x6c/0x150 [i915] [ 231.743853] i915_reset+0x175/0x210 [i915] [ 231.743958] i915_reset_device+0x33b/0x350 [i915] [ 231.744061] ? valleyview_pipestat_irq_handler+0xe0/0xe0 [i915] [ 231.744081] ? trace_hardirqs_off_caller+0x70/0x110 [ 231.744102] ? _raw_spin_unlock_irqrestore+0x46/0x50 [ 231.744120] ? find_held_lock+0x119/0x150 [ 231.744138] ? mark_lock+0x6d/0x850 [ 231.744241] ? gen8_gt_irq_ack+0x1f0/0x1f0 [i915] [ 231.744262] ? work_on_cpu_safe+0x60/0x60 [ 231.744284] ? rcu_read_lock_sched_held+0x57/0xa0 [ 231.744400] ? gen6_read32+0x2ba/0x320 [i915] [ 231.744506] i915_handle_error+0x382/0x5f0 [i915] [ 231.744611] ? gen6_rps_reset_ei+0x20/0x20 [i915] [ 231.744630] ? vsnprintf+0x128/0x8e0 [ 231.744649] ? pointer+0x6b0/0x6b0 [ 231.744667] ? debug_check_no_locks_freed+0x1a0/0x1a0 [ 231.744688] ? scnprintf+0x92/0xe0 [ 231.744706] ? snprintf+0xb0/0xb0 [ 231.744820] hangcheck_declare_hang+0x15a/0x1a0 [i915] [ 231.744932] ? engine_stuck+0x440/0x440 [i915] [ 231.744951] ? rcu_read_lock_sched_held+0x57/0xa0 [ 231.745062] ? gen6_read32+0x2ba/0x320 [i915] [ 231.745173] ? gen6_read16+0x320/0x320 [i915] [ 231.745284] ? intel_engine_get_active_head+0x91/0x170 [i915] [ 231.745401] i915_hangcheck_elapsed+0x3d8/0x400 [i915] [ 231.745424] process_one_work+0x3e8/0xac0 [ 231.745444] ? pwq_dec_nr_in_flight+0x110/0x110 [ 231.745464] ? do_raw_spin_lock+0x8e/0x120 [ 231.745484] worker_thread+0x8d/0x720 [ 231.745506] kthread+0x19e/0x1f0 [ 231.745524] ? process_one_work+0xac0/0xac0 [ 231.745541] ? kthread_create_on_node+0xa0/0xa0 [ 231.745560] ret_from_fork+0x27/0x40 [ 231.745581] Code: 8b 7d c8 e8 49 0d 02 e1 49 8b 7f 38 48 8b 75 b8 48 83 c7 10 e8 b8 89 be e1 e9 95 fc ff ff 4c 89 e7 e8 4b b9 ff ff e9 30 ff ff ff <0f> 0b 0f 1f 40 00 55 48 89 e5 41 57 41 56 41 55 41 54 49 89 fe [ 231.745767] RIP: i915_gem_reset_engine+0x45a/0x460 [i915] RSP: ffff8801f42ff770 At first glance this looks to be related to commit c64992e035d7 ("drm/i915: Look for active requests earlier in the reset path"), but it could easily happen before as well. On the other hand, we no longer logged victims due to the active_request being dropped earlier. v2: Be trickier to unwind the incomplete request as we cannot rely on request retirement for the lockless per-engine reset. v3: Reprobe the active request at the time of the reset. Reported-by: Daniel Vetter Fixes: c64992e035d7 ("drm/i915: Look for active requests earlier in the reset path") Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Cc: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-15-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen #v1 Reviewed-by: Michel Thierry Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 53 +++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a9ea83ea321b..6faabf34f142 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2854,11 +2854,9 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine) if (engine->irq_seqno_barrier) engine->irq_seqno_barrier(engine); - if (engine_stalled(engine)) { - request = i915_gem_find_active_request(engine); - if (request && request->fence.error == -EIO) - request = ERR_PTR(-EIO); /* Previous reset failed! */ - } + request = i915_gem_find_active_request(engine); + if (request && request->fence.error == -EIO) + request = ERR_PTR(-EIO); /* Previous reset failed! */ return request; } @@ -2927,12 +2925,11 @@ static void engine_skip_context(struct drm_i915_gem_request *request) spin_unlock_irqrestore(&engine->timeline->lock, flags); } -/* Returns true if the request was guilty of hang */ -static bool i915_gem_reset_request(struct drm_i915_gem_request *request) +/* Returns the request if it was guilty of the hang */ +static struct drm_i915_gem_request * +i915_gem_reset_request(struct intel_engine_cs *engine, + struct drm_i915_gem_request *request) { - /* Read once and return the resolution */ - const bool guilty = !i915_gem_request_completed(request); - /* The guilty request will get skipped on a hung engine. * * Users of client default contexts do not rely on logical @@ -2954,15 +2951,34 @@ static bool i915_gem_reset_request(struct drm_i915_gem_request *request) * subsequent hangs. */ - if (guilty) { + if (engine_stalled(engine)) { i915_gem_context_mark_guilty(request->ctx); skip_request(request); + + /* If this context is now banned, skip all pending requests. */ + if (i915_gem_context_is_banned(request->ctx)) + engine_skip_context(request); } else { - i915_gem_context_mark_innocent(request->ctx); - dma_fence_set_error(&request->fence, -EAGAIN); + /* + * Since this is not the hung engine, it may have advanced + * since the hang declaration. Double check by refinding + * the active request at the time of the reset. + */ + request = i915_gem_find_active_request(engine); + if (request) { + i915_gem_context_mark_innocent(request->ctx); + dma_fence_set_error(&request->fence, -EAGAIN); + + /* Rewind the engine to replay the incomplete rq */ + spin_lock_irq(&engine->timeline->lock); + request = list_prev_entry(request, link); + if (&request->link == &engine->timeline->requests) + request = NULL; + spin_unlock_irq(&engine->timeline->lock); + } } - return guilty; + return request; } void i915_gem_reset_engine(struct intel_engine_cs *engine, @@ -2970,13 +2986,12 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine, { engine->irq_posted = 0; - if (request && i915_gem_reset_request(request)) { + if (request) + request = i915_gem_reset_request(engine, request); + + if (request) { DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", engine->name, request->global_seqno); - - /* If this context is now banned, skip all pending requests. */ - if (i915_gem_context_is_banned(request->ctx)) - engine_skip_context(request); } /* Setup the CS to resume from the breadcrumb of the hung request */ From 3744d49c6b2d2d08f06715285196a946215887ba Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:35 +0100 Subject: [PATCH 068/179] drm/i915/selftest: Refactor reset locking Extract the common barrier against rogue hangchecks from disrupting our direct testing of resets, and in the process expand the lock to include the per-engine reset shortcuts. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-17-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry Signed-off-by: Daniel Vetter --- .../gpu/drm/i915/selftests/intel_hangcheck.c | 58 ++++++++++++++----- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index cf589e3c7106..d4265ef21875 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -297,6 +297,37 @@ unlock: return err; } +static void global_reset_lock(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags)) + wait_event(i915->gpu_error.reset_queue, + !test_bit(I915_RESET_BACKOFF, + &i915->gpu_error.flags)); + + for_each_engine(engine, i915, id) { + while (test_and_set_bit(I915_RESET_ENGINE + id, + &i915->gpu_error.flags)) + wait_on_bit(&i915->gpu_error.flags, + I915_RESET_ENGINE + id, + TASK_UNINTERRUPTIBLE); + } +} + +static void global_reset_unlock(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + for_each_engine(engine, i915, id) + clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags); + + clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + wake_up_all(&i915->gpu_error.reset_queue); +} + static int igt_global_reset(void *arg) { struct drm_i915_private *i915 = arg; @@ -305,7 +336,7 @@ static int igt_global_reset(void *arg) /* Check that we can issue a global GPU reset */ - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); set_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags); mutex_lock(&i915->drm.struct_mutex); @@ -320,8 +351,7 @@ static int igt_global_reset(void *arg) mutex_unlock(&i915->drm.struct_mutex); GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags)); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) err = -EIO; @@ -571,7 +601,7 @@ static int igt_wait_reset(void *arg) /* Check that we detect a stuck waiter and issue a reset */ - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); @@ -616,8 +646,7 @@ fini: hang_fini(&h); unlock: mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) return -EIO; @@ -638,7 +667,8 @@ static int igt_reset_queue(void *arg) if (!igt_can_mi_store_dword_imm(i915)) return 0; - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); + mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); if (err) @@ -732,8 +762,7 @@ fini: hang_fini(&h); unlock: mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) return -EIO; @@ -755,7 +784,8 @@ static int igt_render_engine_reset_fallback(void *arg) if (!intel_has_reset_engine(i915)) return 0; - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); + mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); @@ -785,8 +815,7 @@ static int igt_render_engine_reset_fallback(void *arg) /* unlock since we'll call handle_error */ mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); i915_handle_error(i915, intel_engine_flag(engine), "live test"); @@ -808,7 +837,7 @@ static int igt_render_engine_reset_fallback(void *arg) * more full reset to re-enable the hw. */ if (i915_terminally_wedged(&i915->gpu_error)) { - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); rq->fence.error = 0; mutex_lock(&i915->drm.struct_mutex); @@ -829,8 +858,7 @@ out_rq: i915_gem_request_put(rq); hang_fini(&h); out_backoff: - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) return -EIO; From 535275d3238f3a302b6b7812b3af6ab5989a06e2 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 13:32:37 +0100 Subject: [PATCH 069/179] drm/i915: Squelch reset messages during selftests During our selftests, we try reseting the GPU tens of thousands of times, flooding the dmesg with our reset spam drowning out any potential warnings. Add an option to i915_reset()/i915_reset_engine() to specify a quiet reset for selftesting. Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170721123238.16428-19-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 48 ++++++++++--------- drivers/gpu/drm/i915/i915_drv.h | 8 +++- drivers/gpu/drm/i915/i915_gem_request.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 4 +- .../gpu/drm/i915/selftests/intel_hangcheck.c | 8 ++-- 5 files changed, 39 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 3ac8215c0e36..214555e813f1 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1831,7 +1831,8 @@ static int i915_resume_switcheroo(struct drm_device *dev) /** * i915_reset - reset chip after a hang - * @dev_priv: device private to reset + * @i915: #drm_i915_private to reset + * @flags: Instructions * * Reset the chip. Useful if a hang is detected. Marks the device as wedged * on failure. @@ -1846,34 +1847,34 @@ static int i915_resume_switcheroo(struct drm_device *dev) * - re-init interrupt state * - re-init display */ -void i915_reset(struct drm_i915_private *dev_priv) +void i915_reset(struct drm_i915_private *i915, unsigned int flags) { - struct i915_gpu_error *error = &dev_priv->gpu_error; + struct i915_gpu_error *error = &i915->gpu_error; int ret; - lockdep_assert_held(&dev_priv->drm.struct_mutex); + lockdep_assert_held(&i915->drm.struct_mutex); GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags)); if (!test_bit(I915_RESET_HANDOFF, &error->flags)) return; /* Clear any previous failed attempts at recovery. Time to try again. */ - if (!i915_gem_unset_wedged(dev_priv)) + if (!i915_gem_unset_wedged(i915)) goto wakeup; - dev_notice(dev_priv->drm.dev, - "Resetting chip after gpu hang\n"); + if (!(flags & I915_RESET_QUIET)) + dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n"); error->reset_count++; - disable_irq(dev_priv->drm.irq); - ret = i915_gem_reset_prepare(dev_priv); + disable_irq(i915->drm.irq); + ret = i915_gem_reset_prepare(i915); if (ret) { DRM_ERROR("GPU recovery failed\n"); - intel_gpu_reset(dev_priv, ALL_ENGINES); + intel_gpu_reset(i915, ALL_ENGINES); goto error; } - ret = intel_gpu_reset(dev_priv, ALL_ENGINES); + ret = intel_gpu_reset(i915, ALL_ENGINES); if (ret) { if (ret != -ENODEV) DRM_ERROR("Failed to reset chip: %i\n", ret); @@ -1882,8 +1883,8 @@ void i915_reset(struct drm_i915_private *dev_priv) goto error; } - i915_gem_reset(dev_priv); - intel_overlay_reset(dev_priv); + i915_gem_reset(i915); + intel_overlay_reset(i915); /* Ok, now get things going again... */ @@ -1899,17 +1900,17 @@ void i915_reset(struct drm_i915_private *dev_priv) * was running at the time of the reset (i.e. we weren't VT * switched away). */ - ret = i915_gem_init_hw(dev_priv); + ret = i915_gem_init_hw(i915); if (ret) { DRM_ERROR("Failed hw init on reset %d\n", ret); goto error; } - i915_queue_hangcheck(dev_priv); + i915_queue_hangcheck(i915); finish: - i915_gem_reset_finish(dev_priv); - enable_irq(dev_priv->drm.irq); + i915_gem_reset_finish(i915); + enable_irq(i915->drm.irq); wakeup: clear_bit(I915_RESET_HANDOFF, &error->flags); @@ -1917,14 +1918,15 @@ wakeup: return; error: - i915_gem_set_wedged(dev_priv); - i915_gem_retire_requests(dev_priv); + i915_gem_set_wedged(i915); + i915_gem_retire_requests(i915); goto finish; } /** * i915_reset_engine - reset GPU engine to recover from a hang * @engine: engine to reset + * @flags: options * * Reset a specific GPU engine. Useful if a hang is detected. * Returns zero on successful reset or otherwise an error code. @@ -1934,7 +1936,7 @@ error: * - reset engine (which will force the engine to idle) * - re-init/configure engine */ -int i915_reset_engine(struct intel_engine_cs *engine) +int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags) { struct i915_gpu_error *error = &engine->i915->gpu_error; struct drm_i915_gem_request *active_request; @@ -1942,8 +1944,10 @@ int i915_reset_engine(struct intel_engine_cs *engine) GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); - dev_notice(engine->i915->drm.dev, - "Resetting %s after gpu hang\n", engine->name); + if (!(flags & I915_RESET_QUIET)) { + dev_notice(engine->i915->drm.dev, + "Resetting %s after gpu hang\n", engine->name); + } error->reset_engine_count[engine->id]++; active_request = i915_gem_reset_prepare_engine(engine); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0ac66a4c361f..037647245e69 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3110,8 +3110,12 @@ extern int i915_driver_load(struct pci_dev *pdev, extern void i915_driver_unload(struct drm_device *dev); extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); -extern void i915_reset(struct drm_i915_private *dev_priv); -extern int i915_reset_engine(struct intel_engine_cs *engine); + +#define I915_RESET_QUIET BIT(0) +extern void i915_reset(struct drm_i915_private *i915, unsigned int flags); +extern int i915_reset_engine(struct intel_engine_cs *engine, + unsigned int flags); + extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); extern int intel_guc_reset(struct drm_i915_private *dev_priv); extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 68e406a53c04..9eedd33eb524 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -1071,7 +1071,7 @@ static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *req return false; __set_current_state(TASK_RUNNING); - i915_reset(request->i915); + i915_reset(request->i915, 0); return true; } diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9b46c6169d83..e682237e7009 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2624,7 +2624,7 @@ static void i915_reset_device(struct drm_i915_private *dev_priv) */ do { if (mutex_trylock(&dev_priv->drm.struct_mutex)) { - i915_reset(dev_priv); + i915_reset(dev_priv, 0); mutex_unlock(&dev_priv->drm.struct_mutex); } } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags, @@ -2739,7 +2739,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv, &dev_priv->gpu_error.flags)) continue; - if (i915_reset_engine(engine) == 0) + if (i915_reset_engine(engine, 0) == 0) engine_mask &= ~intel_engine_flag(engine); clear_bit(I915_RESET_ENGINE + engine->id, diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index d4265ef21875..6896751ee919 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -342,7 +342,7 @@ static int igt_global_reset(void *arg) mutex_lock(&i915->drm.struct_mutex); reset_count = i915_reset_count(&i915->gpu_error); - i915_reset(i915); + i915_reset(i915, I915_RESET_QUIET); if (i915_reset_count(&i915->gpu_error) == reset_count) { pr_err("No GPU reset recorded!\n"); @@ -378,7 +378,7 @@ static int igt_reset_engine(void *arg) reset_engine_count = i915_reset_engine_count(&i915->gpu_error, engine); - err = i915_reset_engine(engine); + err = i915_reset_engine(engine, I915_RESET_QUIET); if (err) { pr_err("i915_reset_engine failed\n"); break; @@ -511,7 +511,7 @@ static int igt_reset_active_engines(void *arg) set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags); do { - err = i915_reset_engine(engine); + err = i915_reset_engine(engine, I915_RESET_QUIET); if (err) { pr_err("i915_reset_engine(%s) failed, err=%d\n", engine->name, err); @@ -715,7 +715,7 @@ static int igt_reset_queue(void *arg) reset_count = fake_hangcheck(prev); - i915_reset(i915); + i915_reset(i915, I915_RESET_QUIET); GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags)); From cb7ffbad1851dc9d86da5c5d69176d21dff042c7 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 25 Jul 2017 13:53:36 +0100 Subject: [PATCH 070/179] drm/i915/selftests: Fix kbuild error After applying af2788925ae0 ("drm/i915: Squelch reset messages during selftests") out of sequence, I missed fixing up a call to i915_reset(). Reported-by: kbuild test robot Fixes: af2788925ae0 ("drm/i915: Squelch reset messages during selftests") Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170725125336.11969-1-chris@chris-wilson.co.uk Reviewed-by: David Weinehall --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 6896751ee919..7c55a4c7f4c9 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -842,7 +842,7 @@ static int igt_render_engine_reset_fallback(void *arg) mutex_lock(&i915->drm.struct_mutex); set_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags); - i915_reset(i915); + i915_reset(i915, I915_RESET_QUIET); GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags)); mutex_unlock(&i915->drm.struct_mutex); From 746a51732688de0b808dbe9562e103bed66b955a Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 14 Jul 2017 14:52:28 -0300 Subject: [PATCH 071/179] drm/i915: cleanup the CHICKEN_MISC_2 (re)definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Don't define it twice. * Define MSBs first, like the rest of i915_reg.h. * Add CNL_ prefix to the bit that arrived in CNL. Cc: Ville Syrjälä Cc: Rodrigo Vivi Signed-off-by: Paulo Zanoni Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20170714175228.27019-1-paulo.r.zanoni@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 8 +++----- drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++-- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 67be8eb57065..1dc7e7a2a23b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6731,12 +6731,10 @@ enum { #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) #define CHICKEN_MISC_2 _MMIO(0x42084) -#define GLK_CL0_PWR_DOWN (1 << 10) -#define GLK_CL1_PWR_DOWN (1 << 11) +#define CNL_COMP_PWR_DOWN (1 << 23) #define GLK_CL2_PWR_DOWN (1 << 12) - -#define CHICKEN_MISC_2 _MMIO(0x42084) -#define COMP_PWR_DOWN (1 << 23) +#define GLK_CL1_PWR_DOWN (1 << 11) +#define GLK_CL0_PWR_DOWN (1 << 10) #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index a709a686b978..347484ed6d2c 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2712,7 +2712,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 2. Enable Comp */ val = I915_READ(CHICKEN_MISC_2); - val &= ~COMP_PWR_DOWN; + val &= ~CNL_COMP_PWR_DOWN; I915_WRITE(CHICKEN_MISC_2, val); val = I915_READ(CNL_PORT_COMP_DW3); @@ -2786,7 +2786,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) /* 5. Disable Comp */ val = I915_READ(CHICKEN_MISC_2); - val |= COMP_PWR_DOWN; + val |= CNL_COMP_PWR_DOWN; I915_WRITE(CHICKEN_MISC_2, val); } From 525a4f938290b6c7c4dd1cf0c86291817f082acf Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 14 Jul 2017 16:38:22 -0300 Subject: [PATCH 072/179] drm/i915/fbc: add comments to the FBC auxiliary structs I wrote this code an year and a half ago and I couldn't exactly remember the main differences of these two structures when reviewing a new FBC patch. Add some comments to help explain what's the purpose of each struct. For the record, the original commits are: b183b3f14395 ("drm/i915/fbc: introduce struct intel_fbc_reg_params") aaf78d276ba0 ("drm/i915/fbc: introduce struct intel_fbc_state_cache") Cc: Praveen Paneri Signed-off-by: Paulo Zanoni Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170714193822.12121-1-paulo.r.zanoni@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 037647245e69..2c7456f4ed38 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1058,6 +1058,11 @@ struct intel_fbc { bool underrun_detected; struct work_struct underrun_work; + /* + * Due to the atomic rules we can't access some structures without the + * appropriate locking, so we cache information here in order to avoid + * these problems. + */ struct intel_fbc_state_cache { struct i915_vma *vma; @@ -1079,6 +1084,13 @@ struct intel_fbc { } fb; } state_cache; + /* + * This structure contains everything that's relevant to program the + * hardware registers. When we want to figure out if we need to disable + * and re-enable FBC for a new configuration we just check if there's + * something different in the struct. The genx_fbc_activate functions + * are supposed to read from it in order to program the registers. + */ struct intel_fbc_reg_params { struct i915_vma *vma; From a8e45a1c42d11597e975f3e5f2fe182f90cdaa7f Mon Sep 17 00:00:00 2001 From: "Navare, Manasi D" Date: Mon, 17 Jul 2017 15:05:22 -0700 Subject: [PATCH 073/179] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence The condition for setting the Loadgen Select bit of PORT_TX_DW4 register during DDI Vswing Sequence should be Bit rate <=6 GHz whereas the existing code checks only Bit Rate < 6GHz. This patch fixes this condition. While at it also remove the redundant paranthesis. Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") Cc: Paulo Zanoni Cc: Rodrigo Vivi Signed-off-by: Manasi Navare Reviewed-by: Paulo Zanoni Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/1500329122-32662-1-git-send-email-manasi.d.navare@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 4a0e35ede643..494fbe0a7678 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2013,8 +2013,8 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level) val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); val &= ~LOADGEN_SELECT; - if (((rate < 600000) && (width == 4) && (ln >= 1)) || - ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) { + if ((rate <= 600000 && width == 4 && ln >= 1) || + (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { val |= LOADGEN_SELECT; } I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); From 67fddd902b8e37b15a905c287ce4e40f52a564af Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 15:50:34 +0100 Subject: [PATCH 074/179] drm/i915: Remove assertion from raw __i915_vma_unpin() After we detect a i915_vma pin overflow, we call __i915_vma_unpin to cleanup. However, on an overflow the pin_count bitfield will be zero, triggering an assertion, even though we the intention is to merely warn and report the error back to the user (as historically the culprit has be a leak in the display code). Fixes: 20dfbde463c8 ("drm/i915: Wrap vma->pin_count accessors with small inline helpers") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20170721145037.25105-2-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_vma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 4a673fc1a432..20cf272c97b1 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -284,12 +284,12 @@ static inline void __i915_vma_pin(struct i915_vma *vma) static inline void __i915_vma_unpin(struct i915_vma *vma) { - GEM_BUG_ON(!i915_vma_is_pinned(vma)); vma->flags--; } static inline void i915_vma_unpin(struct i915_vma *vma) { + GEM_BUG_ON(!i915_vma_is_pinned(vma)); GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); __i915_vma_unpin(vma); } From 1da7b54c46bcfe5484af0b27d8c9003b238031b0 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 15:50:35 +0100 Subject: [PATCH 075/179] drm/i915: Only mark the execobject as pinned on success If we fail to acquire a fence (for old school fenced GPU access) then we unwind the vma reservation, including its pin. However, we were making the execobject as holding the pin before erring out, leading to a double unpin: [ 3193.991802] kernel BUG at drivers/gpu/drm/i915/i915_vma.h:287! [ 3193.998131] invalid opcode: 0000 [#1] PREEMPT SMP [ 3194.002816] Modules linked in: snd_hda_intel i915 vgem snd_hda_codec_analog snd_hda_codec_generic coretemp snd_hda_codec snd_hwdep snd_hda_core snd_pcm lpc_ich mei_me e1000e mei prime_numbers ptp pps_core [last unloaded: i915] [ 3194.022841] CPU: 0 PID: 8123 Comm: kms_flip Tainted: G U 4.13.0-rc1-CI-CI_DRM_471+ #1 [ 3194.031765] Hardware name: Dell Inc. OptiPlex 755 /0PU052, BIOS A04 11/05/2007 [ 3194.040343] task: ffff8800785d4c40 task.stack: ffffc90001768000 [ 3194.046339] RIP: 0010:eb_release_vmas.isra.6+0x119/0x180 [i915] [ 3194.052234] RSP: 0018:ffffc9000176ba80 EFLAGS: 00010246 [ 3194.057439] RAX: 00000000000003c0 RBX: ffff8800710fc2d8 RCX: ffff8800588e4f48 [ 3194.064546] RDX: ffffffff1fffffff RSI: 00000000ffffffff RDI: ffff8800588e00d0 [ 3194.071654] RBP: ffffc9000176bab0 R08: 0000000000000000 R09: 0000000000000000 [ 3194.078761] R10: 0000000000000040 R11: 0000000000000001 R12: ffff880060822f00 [ 3194.085867] R13: 0000000000000310 R14: 00000000000003b8 R15: ffffc9000176bbb0 [ 3194.092975] FS: 00007fd2b94aba40(0000) GS:ffff88007d200000(0000) knlGS:0000000000000000 [ 3194.101033] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3194.106754] CR2: 00007ffbec3ff000 CR3: 0000000074e67000 CR4: 00000000000006f0 [ 3194.113861] Call Trace: [ 3194.116321] eb_relocate_slow+0x67/0x4e0 [i915] [ 3194.120861] i915_gem_do_execbuffer+0x429/0x1260 [i915] [ 3194.126070] ? lock_acquire+0xb5/0x210 [ 3194.129803] ? __might_fault+0x39/0x90 [ 3194.133563] i915_gem_execbuffer2+0x9b/0x1b0 [i915] [ 3194.138447] ? i915_gem_execbuffer+0x2b0/0x2b0 [i915] [ 3194.143478] drm_ioctl_kernel+0x64/0xb0 [ 3194.147298] drm_ioctl+0x2cd/0x390 [ 3194.150710] ? i915_gem_execbuffer+0x2b0/0x2b0 [i915] [ 3194.155741] ? finish_task_switch+0xa5/0x210 [ 3194.159993] ? finish_task_switch+0x6a/0x210 [ 3194.164247] do_vfs_ioctl+0x90/0x670 [ 3194.167806] ? entry_SYSCALL_64_fastpath+0x5/0xb1 [ 3194.172492] ? __this_cpu_preempt_check+0x13/0x20 [ 3194.177176] ? trace_hardirqs_on_caller+0xe7/0x1c0 [ 3194.181946] SyS_ioctl+0x3c/0x70 [ 3194.185159] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 3194.189756] RIP: 0033:0x7fd2b76a8587 [ 3194.193314] RSP: 002b:00007fff074845b8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 3194.200855] RAX: ffffffffffffffda RBX: ffffffff8146da43 RCX: 00007fd2b76a8587 [ 3194.207962] RDX: 00007fff074846e0 RSI: 0000000040406469 RDI: 0000000000000003 [ 3194.215068] RBP: ffffc9000176bf88 R08: 0000000000000000 R09: 0000000000000003 [ 3194.222175] R10: 00007fd2b796bb58 R11: 0000000000000246 R12: 00007fff07484880 [ 3194.229280] R13: 0000000000000003 R14: 0000000040406469 R15: 0000000000000000 [ 3194.236386] ? __this_cpu_preempt_check+0x13/0x20 [ 3194.241070] Code: 24 b0 00 00 00 48 85 c9 0f 84 6c ff ff ff 8b 41 20 85 c0 7e 73 83 e8 01 89 41 20 41 8b 84 24 e8 00 00 00 a8 0f 0f 85 5f ff ff ff <0f> 0b 48 83 c4 08 5b 41 5c 41 5d 41 5e 41 5f 5d f3 c3 49 8b 84 [ 3194.259943] RIP: eb_release_vmas.isra.6+0x119/0x180 [i915] RSP: ffffc9000176ba80 [ 3194.268047] ---[ end trace 1d7348c6575d8800 ]--- [ 3673.658819] softdog: Initiating panic [ 3673.662471] Kernel panic - not syncing: Software Watchdog Timer expired [ 3673.669066] Kernel Offset: disabled [ 3673.672541] Rebooting in 1 seconds.. Reported-by: Tomi Sarvela Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the execobjects array") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20170721145037.25105-3-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index fe3e0d40034c..f30675c6bc4a 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -560,9 +560,6 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, eb->args->flags |= __EXEC_HAS_RELOC; } - entry->flags |= __EXEC_OBJECT_HAS_PIN; - GEM_BUG_ON(eb_vma_misplaced(entry, vma)); - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { err = i915_vma_get_fence(vma); if (unlikely(err)) { @@ -574,6 +571,9 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, entry->flags |= __EXEC_OBJECT_HAS_FENCE; } + entry->flags |= __EXEC_OBJECT_HAS_PIN; + GEM_BUG_ON(eb_vma_misplaced(entry, vma)); + return 0; } From 1f727d9e725a408ef58d159c20fb2e51818ff153 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 15:50:36 +0100 Subject: [PATCH 076/179] drm/i915: Only skip updating execobject.offset after error I was being overly paranoid in not updating the execobject.offset after performing the fallback copy where we set reloc.presumed_offset to -1. The thinking was to ensure that a subsequent NORELOC execbuf would be forced to process the invalid relocations. However this is overkill so long as we *only* update the execobject.offset following a successful update of the relocation value witin the batch. If we have to repeat the execbuf due to a later interruption, then we may skip the relocations on the second pass (honouring NORELOC) since the execobject.offset match the actual offsets (even though reloc.presumed_offset is garbage). Subsequent calls to execbuf with NORELOC should themselves ensure that the reloc.presumed_offset have been corrected in case of future migration. Reporting back the actual execobject.offset, even when reloc.presumed_offset is garbage, ensures that reuse of those objects use the latest information to avoid relocations. Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the execobjects array") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101635 Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20170721145037.25105-4-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index f30675c6bc4a..ae47e1837415 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1776,7 +1776,7 @@ out: } } - return err ?: have_copy; + return err; } static int eb_relocate(struct i915_execbuffer *eb) @@ -2210,7 +2210,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_rpm; err = eb_relocate(&eb); - if (err) + if (err) { /* * If the user expects the execobject.offset and * reloc.presumed_offset to be an exact match, @@ -2219,8 +2219,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, * relocation. */ args->flags &= ~__EXEC_HAS_RELOC; - if (err < 0) goto err_vma; + } if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) { DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); From 0f46daa1a273779a0b73d768a788ca3f04238f9c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 21 Jul 2017 15:50:37 +0100 Subject: [PATCH 077/179] drm/i915: Force CPU synchronisation even if userspace requests ASYNC The goal here was to minimise doing any thing or any check inside the kernel that was not strictly required. For a userspace that assumes complete control over the cache domains, the kernel is usually using outdated information and may trigger clflushes where none were required. However, swapping is a situation where userspace has no knowledge of the domain transfer, and will leave the object in the CPU cache. The kernel must flush this out to the backing storage prior to use with the GPU. As we use an asynchronous task tracked by an implicit fence for this, we also need to cancel the ASYNC flag on the object so that the object will wait for the clflush to complete before being executed. This also absolves userspace of the responsibility imposed by commit 77ae9957897d ("drm/i915: Enable userspace to opt-out of implicit fencing") that its needed to ensure that the object was out of the CPU cache prior to use on the GPU. Fixes: 77ae9957897d ("drm/i915: Enable userspace to opt-out of implicit fencing") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101571 Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Jason Ekstrand Reviewed-by: Jason Ekstrand Link: https://patchwork.freedesktop.org/patch/msgid/20170721145037.25105-5-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_clflush.c | 7 ++++--- drivers/gpu/drm/i915/i915_gem_clflush.h | 2 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 ++++++---- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c index 152f16c11878..348b29a845c9 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c @@ -114,7 +114,7 @@ i915_clflush_notify(struct i915_sw_fence *fence, return NOTIFY_DONE; } -void i915_gem_clflush_object(struct drm_i915_gem_object *obj, +bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, unsigned int flags) { struct clflush *clflush; @@ -128,7 +128,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, */ if (!i915_gem_object_has_struct_page(obj)) { obj->cache_dirty = false; - return; + return false; } /* If the GPU is snooping the contents of the CPU cache, @@ -140,7 +140,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, * tracking. */ if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent) - return; + return false; trace_i915_gem_object_clflush(obj); @@ -179,4 +179,5 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, } obj->cache_dirty = false; + return true; } diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.h b/drivers/gpu/drm/i915/i915_gem_clflush.h index 2455a7820937..f390247561b3 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.h +++ b/drivers/gpu/drm/i915/i915_gem_clflush.h @@ -28,7 +28,7 @@ struct drm_i915_private; struct drm_i915_gem_object; -void i915_gem_clflush_object(struct drm_i915_gem_object *obj, +bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, unsigned int flags); #define I915_CLFLUSH_FORCE BIT(0) #define I915_CLFLUSH_SYNC BIT(1) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index ae47e1837415..5fa44767c29e 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1826,7 +1826,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) int err; for (i = 0; i < count; i++) { - const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; + struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; struct i915_vma *vma = exec_to_vma(entry); struct drm_i915_gem_object *obj = vma->obj; @@ -1842,12 +1842,14 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) eb->request->capture_list = capture; } + if (unlikely(obj->cache_dirty && !obj->cache_coherent)) { + if (i915_gem_clflush_object(obj, 0)) + entry->flags &= ~EXEC_OBJECT_ASYNC; + } + if (entry->flags & EXEC_OBJECT_ASYNC) goto skip_flushes; - if (unlikely(obj->cache_dirty && !obj->cache_coherent)) - i915_gem_clflush_object(obj, 0); - err = i915_gem_request_await_object (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE); if (err) From d38014eaac512761cb9ffa552247a888bf30a2c3 Mon Sep 17 00:00:00 2001 From: Gabriel Krisman Bertazi Date: Wed, 26 Jul 2017 02:30:16 -0300 Subject: [PATCH 078/179] drm/i915: Handle msr read failure gracefully When reading the i915_energy_uJ debugfs file, it tries to fetch MSR_RAPL_POWER_UNIT, which might not be available, like in a vm environment, causing the exception shown below. We can easily prevent it by doing a rdmsrl_safe read instead, which will handle the exception, allowing us to abort the debugfs file read. This was caught by the new igt@debugfs_test@read_all_entries testcase in the CI. unchecked MSR access error: RDMSR from 0x606 at rIP:0xffffffffa0078f66 (i915_energy_uJ+0x36/0xb0 [i915]) Call Trace: seq_read+0xdc/0x3a0 full_proxy_read+0x4f/0x70 __vfs_read+0x23/0x120 ? putname+0x4f/0x60 ? rcu_read_lock_sched_held+0x75/0x80 ? entry_SYSCALL_64_fastpath+0x5/0xb1 vfs_read+0xa0/0x150 SyS_read+0x44/0xb0 entry_SYSCALL_64_fastpath+0x1c/0xb1 RIP: 0033:0x7f1f5e9f4500 RSP: 002b:00007ffc77e65cf8 EFLAGS: 00000246 ORIG_RAX: 0000000000000000 RAX: ffffffffffffffda RBX: ffffffff8146e003 RCX: 00007f1f5e9f4500 RDX: 0000000000000200 RSI: 00007ffc77e65d10 RDI: 0000000000000006 RBP: ffffc900007abf88 R08: 0000000001eaff20 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 0000000000000006 R14: 0000000000000005 R15: 0000000001eb94db ? __this_cpu_preempt_check+0x13/0x20 v2: - Drop unsigned long long cast and improve calculation (Chris) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101901 Signed-off-by: Gabriel Krisman Bertazi Link: https://patchwork.freedesktop.org/patch/msgid/87o9s7zrx3.fsf@dilma.collabora.co.uk Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index ea50c4a1efae..6480897bcaf4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2783,7 +2783,7 @@ out: static int i915_energy_uJ(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - u64 power; + unsigned long long power; u32 units; if (INTEL_GEN(dev_priv) < 6) @@ -2791,15 +2791,18 @@ static int i915_energy_uJ(struct seq_file *m, void *data) intel_runtime_pm_get(dev_priv); - rdmsrl(MSR_RAPL_POWER_UNIT, power); - power = (power & 0x1f00) >> 8; - units = 1000000 / (1 << power); /* convert to uJ */ + if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { + intel_runtime_pm_put(dev_priv); + return -ENODEV; + } + + units = (power & 0x1f00) >> 8; power = I915_READ(MCH_SECP_NRG_STTS); - power *= units; + power = (1000000 * power) >> units; /* convert to uJ */ intel_runtime_pm_put(dev_priv); - seq_printf(m, "%llu", (long long unsigned)power); + seq_printf(m, "%llu", power); return 0; } From fd70075f82b7f471ff923a56dea00fb44463296c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 26 Jul 2017 17:00:36 +0100 Subject: [PATCH 079/179] drm/i915: Trim struct_mutex usage for kms Reduce acquisition of struct_mutex to the critical regions that must hold it; for KMS, we need struct_mutex currently only for the purpose of pinning/unpinning the framebuffer's VMA into the global GTT. This allows us to avoid taking the struct_mutex when disabling the CRTC (i.e. NULL framebuffer objects) before a reset. (Not yet achieving the full goal of avoiding the strut_mutex nesting, but good enough to break the first half of the reset deadlock.) v2: Keep pages pinning inside struct_mutex for the moment. Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170726160038.29487-1-chris@chris-wilson.co.uk [danvet: Drop another case of grabbing dev->struct_mutex around cleanup_planes, which popped up because I had to redo the drm-next backmerge for entirely different reasons. Acked by Chris on irc.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 82 ++++++++++++---------------- 1 file changed, 34 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f7b128c33aa1..87ae355dc75c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11851,16 +11851,7 @@ static int intel_atomic_check(struct drm_device *dev, static int intel_atomic_prepare_commit(struct drm_device *dev, struct drm_atomic_state *state) { - int ret; - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - ret = drm_atomic_helper_prepare_planes(dev, state); - mutex_unlock(&dev->struct_mutex); - - return ret; + return drm_atomic_helper_prepare_planes(dev, state); } u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) @@ -12223,9 +12214,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); } - mutex_lock(&dev->struct_mutex); drm_atomic_helper_cleanup_planes(dev, state); - mutex_unlock(&dev->struct_mutex); drm_atomic_helper_commit_cleanup_done(state); @@ -12340,9 +12329,7 @@ static int intel_atomic_commit(struct drm_device *dev, if (ret) { i915_sw_fence_commit(&intel_state->commit_ready); - mutex_lock(&dev->struct_mutex); drm_atomic_helper_cleanup_planes(dev, state); - mutex_unlock(&dev->struct_mutex); return ret; } dev_priv->wm.distrust_bios_wm = false; @@ -12407,32 +12394,6 @@ intel_prepare_plane_fb(struct drm_plane *plane, struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); int ret; - if (obj) { - if (plane->type == DRM_PLANE_TYPE_CURSOR && - INTEL_INFO(dev_priv)->cursor_needs_physical) { - const int align = intel_cursor_alignment(dev_priv); - - ret = i915_gem_object_attach_phys(obj, align); - if (ret) { - DRM_DEBUG_KMS("failed to attach phys object\n"); - return ret; - } - } else { - struct i915_vma *vma; - - vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); - if (IS_ERR(vma)) { - DRM_DEBUG_KMS("failed to pin object\n"); - return PTR_ERR(vma); - } - - to_intel_plane_state(new_state)->vma = vma; - } - } - - if (!obj && !old_obj) - return 0; - if (old_obj) { struct drm_crtc_state *crtc_state = drm_atomic_get_existing_crtc_state(new_state->state, @@ -12471,6 +12432,31 @@ intel_prepare_plane_fb(struct drm_plane *plane, if (!obj) return 0; + ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); + if (ret) + return ret; + + if (plane->type == DRM_PLANE_TYPE_CURSOR && + INTEL_INFO(dev_priv)->cursor_needs_physical) { + const int align = intel_cursor_alignment(dev_priv); + + ret = i915_gem_object_attach_phys(obj, align); + } else { + struct i915_vma *vma; + + vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); + if (!IS_ERR(vma)) + to_intel_plane_state(new_state)->vma = vma; + else + ret = PTR_ERR(vma); + } + + i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); + + mutex_unlock(&dev_priv->drm.struct_mutex); + if (ret) + return ret; + if (!new_state->fence) { /* implicit fencing */ ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, obj->resv, NULL, @@ -12478,8 +12464,6 @@ intel_prepare_plane_fb(struct drm_plane *plane, GFP_KERNEL); if (ret < 0) return ret; - - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); } return 0; @@ -12502,8 +12486,11 @@ intel_cleanup_plane_fb(struct drm_plane *plane, /* Should only be called after a successful intel_prepare_plane_fb()! */ vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); - if (vma) + if (vma) { + mutex_lock(&plane->dev->struct_mutex); intel_unpin_fb_vma(vma); + mutex_unlock(&plane->dev->struct_mutex); + } } int @@ -12673,7 +12660,7 @@ intel_legacy_cursor_update(struct drm_plane *plane, struct intel_plane *intel_plane = to_intel_plane(plane); struct drm_framebuffer *old_fb; struct drm_crtc_state *crtc_state = crtc->state; - struct i915_vma *old_vma; + struct i915_vma *old_vma, *vma; /* * When crtc is inactive or there is a modeset pending, @@ -12731,8 +12718,6 @@ intel_legacy_cursor_update(struct drm_plane *plane, goto out_unlock; } } else { - struct i915_vma *vma; - vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); if (IS_ERR(vma)) { DRM_DEBUG_KMS("failed to pin object\n"); @@ -12755,7 +12740,7 @@ intel_legacy_cursor_update(struct drm_plane *plane, *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); new_plane_state->fence = NULL; new_plane_state->fb = old_fb; - to_intel_plane_state(new_plane_state)->vma = old_vma; + to_intel_plane_state(new_plane_state)->vma = NULL; if (plane->state->visible) { trace_intel_update_plane(plane, to_intel_crtc(crtc)); @@ -12767,7 +12752,8 @@ intel_legacy_cursor_update(struct drm_plane *plane, intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); } - intel_cleanup_plane_fb(plane, new_plane_state); + if (old_vma) + intel_unpin_fb_vma(old_vma); out_unlock: mutex_unlock(&dev_priv->drm.struct_mutex); From 6ea1d55d31c46e2158a49e8e41cb0be4a8cd8677 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 26 Jul 2017 17:00:37 +0100 Subject: [PATCH 080/179] drm/i915: Make i915_gem_object_phys_attach() use obj->mm.lock more appropriately MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Actually transferring from shmemfs to the physically contiguous set of pages should be wholly guarded by its obj->mm.lock! v2: Remember to free the old pages. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20170726160038.29487-2-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 50 +++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6faabf34f142..12dddba7bf6f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -565,7 +565,8 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) { - int ret; + struct sg_table *pages; + int err; if (align > obj->base.size) return -EINVAL; @@ -573,32 +574,51 @@ i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, if (obj->ops == &i915_gem_phys_ops) return 0; - if (obj->mm.madv != I915_MADV_WILLNEED) - return -EFAULT; - - if (obj->base.filp == NULL) + if (obj->ops != &i915_gem_object_ops) return -EINVAL; - ret = i915_gem_object_unbind(obj); - if (ret) - return ret; + err = i915_gem_object_unbind(obj); + if (err) + return err; - __i915_gem_object_put_pages(obj, I915_MM_NORMAL); - if (obj->mm.pages) - return -EBUSY; + mutex_lock(&obj->mm.lock); - GEM_BUG_ON(obj->ops != &i915_gem_object_ops); + if (obj->mm.madv != I915_MADV_WILLNEED) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.quirked) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.mapping) { + err = -EBUSY; + goto err_unlock; + } + + pages = obj->mm.pages; obj->ops = &i915_gem_phys_ops; - ret = i915_gem_object_pin_pages(obj); - if (ret) + err = __i915_gem_object_get_pages(obj); + if (err) goto err_xfer; + /* Perma-pin (until release) the physical set of pages */ + __i915_gem_object_pin_pages(obj); + + if (!IS_ERR_OR_NULL(pages)) + i915_gem_object_ops.put_pages(obj, pages); + mutex_unlock(&obj->mm.lock); return 0; err_xfer: obj->ops = &i915_gem_object_ops; - return ret; + obj->mm.pages = pages; +err_unlock: + mutex_unlock(&obj->mm.lock); + return err; } static int From 4d3088c7bd4f137eb51bdff6a27d861d3a6361b8 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 26 Jul 2017 17:00:38 +0100 Subject: [PATCH 081/179] drm/i915: Pin the pages before acquiring struct_mutex for display Since we don't need the struct_mutex to acquire the object's pages, call i915_gem_object_pin_pages() before we bind the object into the GGTT. Signed-off-by: Chris Wilson Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170726160038.29487-3-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 87ae355dc75c..5a89db14320f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12432,10 +12432,16 @@ intel_prepare_plane_fb(struct drm_plane *plane, if (!obj) return 0; - ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); + ret = i915_gem_object_pin_pages(obj); if (ret) return ret; + ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); + if (ret) { + i915_gem_object_unpin_pages(obj); + return ret; + } + if (plane->type == DRM_PLANE_TYPE_CURSOR && INTEL_INFO(dev_priv)->cursor_needs_physical) { const int align = intel_cursor_alignment(dev_priv); @@ -12454,6 +12460,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); mutex_unlock(&dev_priv->drm.struct_mutex); + i915_gem_object_unpin_pages(obj); if (ret) return ret; From 8eeb79060b3bea3790e02488d4ebf322487bf8af Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 26 Jul 2017 19:16:01 +0100 Subject: [PATCH 082/179] drm/i915: Move i915_gem_object_phys_attach() Prevent a forward declaration in the next patch. Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170726181602.23527-1-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 118 ++++++++++++++++---------------- 1 file changed, 58 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 12dddba7bf6f..85231d1c39c3 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -561,66 +561,6 @@ static struct intel_rps_client *to_rps_client(struct drm_file *file) return &fpriv->rps; } -int -i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, - int align) -{ - struct sg_table *pages; - int err; - - if (align > obj->base.size) - return -EINVAL; - - if (obj->ops == &i915_gem_phys_ops) - return 0; - - if (obj->ops != &i915_gem_object_ops) - return -EINVAL; - - err = i915_gem_object_unbind(obj); - if (err) - return err; - - mutex_lock(&obj->mm.lock); - - if (obj->mm.madv != I915_MADV_WILLNEED) { - err = -EFAULT; - goto err_unlock; - } - - if (obj->mm.quirked) { - err = -EFAULT; - goto err_unlock; - } - - if (obj->mm.mapping) { - err = -EBUSY; - goto err_unlock; - } - - pages = obj->mm.pages; - obj->ops = &i915_gem_phys_ops; - - err = __i915_gem_object_get_pages(obj); - if (err) - goto err_xfer; - - /* Perma-pin (until release) the physical set of pages */ - __i915_gem_object_pin_pages(obj); - - if (!IS_ERR_OR_NULL(pages)) - i915_gem_object_ops.put_pages(obj, pages); - mutex_unlock(&obj->mm.lock); - return 0; - -err_xfer: - obj->ops = &i915_gem_object_ops; - obj->mm.pages = pages; -err_unlock: - mutex_unlock(&obj->mm.lock); - return err; -} - static int i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, struct drm_i915_gem_pwrite *args, @@ -5346,6 +5286,64 @@ i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, return sg_dma_address(sg) + (offset << PAGE_SHIFT); } +int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) +{ + struct sg_table *pages; + int err; + + if (align > obj->base.size) + return -EINVAL; + + if (obj->ops == &i915_gem_phys_ops) + return 0; + + if (obj->ops != &i915_gem_object_ops) + return -EINVAL; + + err = i915_gem_object_unbind(obj); + if (err) + return err; + + mutex_lock(&obj->mm.lock); + + if (obj->mm.madv != I915_MADV_WILLNEED) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.quirked) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.mapping) { + err = -EBUSY; + goto err_unlock; + } + + pages = obj->mm.pages; + obj->ops = &i915_gem_phys_ops; + + err = __i915_gem_object_get_pages(obj); + if (err) + goto err_xfer; + + /* Perma-pin (until release) the physical set of pages */ + __i915_gem_object_pin_pages(obj); + + if (!IS_ERR_OR_NULL(pages)) + i915_gem_object_ops.put_pages(obj, pages); + mutex_unlock(&obj->mm.lock); + return 0; + +err_xfer: + obj->ops = &i915_gem_object_ops; + obj->mm.pages = pages; +err_unlock: + mutex_unlock(&obj->mm.lock); + return err; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/scatterlist.c" #include "selftests/mock_gem_device.c" From 8fb6a5df4612757d6aa4218750aa3ecaca609bd0 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 26 Jul 2017 19:16:02 +0100 Subject: [PATCH 083/179] drm/i915: Call the unlocked version of i915_gem_object_get_pages() When we hold for the lock for swapping out the shmem pages for the physically contiguous pages, we have to call the unlocked version of get_pages! Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101934 Fixes: 35d23516946e ("drm/i915: Make i915_gem_object_phys_attach() use obj->mm.lock more appropriately") Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170726181602.23527-2-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 85231d1c39c3..000a764ee8d9 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5324,7 +5324,7 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) pages = obj->mm.pages; obj->ops = &i915_gem_phys_ops; - err = __i915_gem_object_get_pages(obj); + err = ____i915_gem_object_get_pages(obj); if (err) goto err_xfer; From a85066840d29fc68d95ce7dbd6bcf15ef2775d66 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 26 Jul 2017 15:26:47 +0200 Subject: [PATCH 084/179] drm/i915: Rework sdvo proxy i2c locking lockdep complaints about a locking recursion for the i2c bus lock because both the sdvo ddc proxy bus and the gmbus nested within use the same locking class. It's not really a deadlock since we never nest the other way round, but it's annoying. Fix it by pulling the gmbus locking into the i2c lock_ops for both i2c_adapater and making sure that the ddc_proxy_xfer function is entirely lockless. Re-layouting the extracted function resulted in some whitespace cleanups, I figured we might as well keep them. v2: Review from Chris: - s/locked/unlocked/ since I got the naming backwards - Use the vfuncs of the proxied adatper instead of re-rolling copies. That's more consistent with the other proxying we're doing. Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170726132647.31833-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_i2c.c | 36 +++++++++++++++++- drivers/gpu/drm/i915/intel_sdvo.c | 62 +++++++++++++++++++++++++------ 2 files changed, 84 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 3c9e00d4ba5a..6698826954e1 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -592,7 +592,6 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) int ret; intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); - mutex_lock(&dev_priv->gmbus_mutex); if (bus->force_bit) { ret = i2c_bit_algo.master_xfer(adapter, msgs, num); @@ -604,7 +603,6 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) bus->force_bit |= GMBUS_FORCE_BIT_RETRY; } - mutex_unlock(&dev_priv->gmbus_mutex); intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); return ret; @@ -624,6 +622,39 @@ static const struct i2c_algorithm gmbus_algorithm = { .functionality = gmbus_func }; +static void gmbus_lock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + mutex_lock(&dev_priv->gmbus_mutex); +} + +static int gmbus_trylock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + return mutex_trylock(&dev_priv->gmbus_mutex); +} + +static void gmbus_unlock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + mutex_unlock(&dev_priv->gmbus_mutex); +} + +const struct i2c_lock_operations gmbus_lock_ops = { + .lock_bus = gmbus_lock_bus, + .trylock_bus = gmbus_trylock_bus, + .unlock_bus = gmbus_unlock_bus, +}; + /** * intel_gmbus_setup - instantiate all Intel i2c GMBuses * @dev_priv: i915 device private @@ -665,6 +696,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) bus->dev_priv = dev_priv; bus->adapter.algo = &gmbus_algorithm; + bus->adapter.lock_ops = &gmbus_lock_ops; /* * We wish to retry with bit banging diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index e58a47db9a9d..c14c05e8a543 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -451,23 +451,24 @@ static const char * const cmd_status_names[] = { "Scaling not supported" }; -static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, - const void *args, int args_len) +static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, + const void *args, int args_len, + bool unlocked) { u8 *buf, status; struct i2c_msg *msgs; int i, ret = true; - /* Would be simpler to allocate both in one go ? */ + /* Would be simpler to allocate both in one go ? */ buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); if (!buf) return false; msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); if (!msgs) { - kfree(buf); + kfree(buf); return false; - } + } intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); @@ -498,7 +499,10 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, msgs[i+2].len = 1; msgs[i+2].buf = &status; - ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); + if (unlocked) + ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); + else + ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); if (ret < 0) { DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); ret = false; @@ -516,6 +520,12 @@ out: return ret; } +static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, + const void *args, int args_len) +{ + return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); +} + static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, void *response, int response_len) { @@ -602,13 +612,13 @@ static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjust return 4; } -static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, - u8 ddc_bus) +static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, + u8 ddc_bus) { /* This must be the immediately preceding write before the i2c xfer */ - return intel_sdvo_write_cmd(intel_sdvo, - SDVO_CMD_SET_CONTROL_BUS_SWITCH, - &ddc_bus, 1); + return __intel_sdvo_write_cmd(intel_sdvo, + SDVO_CMD_SET_CONTROL_BUS_SWITCH, + &ddc_bus, 1, false); } static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) @@ -2926,7 +2936,7 @@ static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, { struct intel_sdvo *sdvo = adapter->algo_data; - if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) + if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) return -EIO; return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); @@ -2943,6 +2953,33 @@ static const struct i2c_algorithm intel_sdvo_ddc_proxy = { .functionality = intel_sdvo_ddc_proxy_func }; +static void proxy_lock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); +} + +static int proxy_trylock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); +} + +static void proxy_unlock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); +} + +const struct i2c_lock_operations proxy_lock_ops = { + .lock_bus = proxy_lock_bus, + .trylock_bus = proxy_trylock_bus, + .unlock_bus = proxy_unlock_bus, +}; + static bool intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, struct drm_i915_private *dev_priv) @@ -2955,6 +2992,7 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, sdvo->ddc.dev.parent = &pdev->dev; sdvo->ddc.algo_data = sdvo; sdvo->ddc.algo = &intel_sdvo_ddc_proxy; + sdvo->ddc.lock_ops = &proxy_lock_ops; return i2c_add_adapter(&sdvo->ddc) == 0; } From de44e256b92c3c378039c6ef39049f1b669c0187 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 26 Jul 2017 21:32:51 +0200 Subject: [PATCH 085/179] drm/i915/sdvo: Shut up state checker with hdmi cards on gen3 The hdmi bits simply don't exist, so nerf them. I think audio doesn't work on gen3 at all, and for the limited color range we should probably use the colorimetry sdvo paramater instead of the bit in the port. But fixing sdvo isn't my goal, I just want to get the backtrace out of the way, and this takes care of that. Still, while at it fix the missing read-out of the gen4 audio bit, maybe that part even works ... v2: Instead of trying to plug the damage in ->compute_config() make sure we never set intel_sdvo->is_hdmi, which stops the bad state at the source. Suggested by Chris Wilson. Also make sure we don't break this by accident by putting a WARN_ON in place. Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170726193251.25393-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_sdvo.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index c14c05e8a543..ab01f9ec80ed 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1359,8 +1359,10 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, else sdvox |= SDVO_PIPE_SEL(crtc->pipe); - if (crtc_state->has_audio) + if (crtc_state->has_audio) { + WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4); sdvox |= SDVO_AUDIO_ENABLE; + } if (INTEL_GEN(dev_priv) >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ @@ -1490,6 +1492,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, if (sdvox & HDMI_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; + if (sdvox & SDVO_AUDIO_ENABLE) + pipe_config->has_audio = true; + if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, &val, 1)) { if (val == SDVO_ENCODE_HDMI) @@ -2465,6 +2470,7 @@ static bool intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) { struct drm_encoder *encoder = &intel_sdvo->base.base; + struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct drm_connector *connector; struct intel_encoder *intel_encoder = to_intel_encoder(encoder); struct intel_connector *intel_connector; @@ -2500,7 +2506,9 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) encoder->encoder_type = DRM_MODE_ENCODER_TMDS; connector->connector_type = DRM_MODE_CONNECTOR_DVID; - if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { + /* gen3 doesn't do the hdmi bits in the SDVO register */ + if (INTEL_GEN(dev_priv) >= 4 && + intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; intel_sdvo->is_hdmi = true; } From 5a9cfff46d193388749f2c4e6ec75f40b47942d2 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 28 Jul 2017 09:50:22 +0100 Subject: [PATCH 086/179] drm/i915: Include mbox details for pcode read/write failures If we fail at punit communication, include both the mbox address and the value we tried to write so that we can identify the invalid sequence. Signed-off-by: Chris Wilson Cc: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170728085022.1586-1-chris@chris-wilson.co.uk Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 48785ef75d33..8711c1f04079 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8831,6 +8831,7 @@ static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv) case GEN6_PCODE_SUCCESS: return 0; case GEN6_PCODE_UNIMPLEMENTED_CMD: + return -ENODEV; case GEN6_PCODE_ILLEGAL_CMD: return -ENXIO; case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: @@ -8878,7 +8879,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val */ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { - DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); + DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n", + mbox, __builtin_return_address(0)); return -EAGAIN; } @@ -8889,7 +8891,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val if (__intel_wait_for_register_fw(dev_priv, GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, 500, 0, NULL)) { - DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); + DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n", + mbox, __builtin_return_address(0)); return -ETIMEDOUT; } @@ -8902,8 +8905,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val status = gen6_check_mailbox_status(dev_priv); if (status) { - DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n", - status); + DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n", + mbox, __builtin_return_address(0), status); return status; } @@ -8923,7 +8926,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, */ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { - DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); + DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n", + val, mbox, __builtin_return_address(0)); return -EAGAIN; } @@ -8934,7 +8938,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, if (__intel_wait_for_register_fw(dev_priv, GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, 500, 0, NULL)) { - DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); + DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n", + val, mbox, __builtin_return_address(0)); return -ETIMEDOUT; } @@ -8946,8 +8951,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, status = gen6_check_mailbox_status(dev_priv); if (status) { - DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n", - status); + DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n", + val, mbox, __builtin_return_address(0), status); return status; } From 03e0c83299556ce02946ce4777a258fc6caf53fb Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 27 Jul 2017 12:01:13 +0100 Subject: [PATCH 087/179] drm/i915: Remove unused i915_err_print_instdone Just a simple code cleanup, below commit forgot to remove a function which it made unused: commit eaa14c24864ecfc60fb591f3b20747af7c67d446 Author: Chris Wilson Date: Wed Oct 19 13:52:03 2016 +0100 drm/i915: Stop reporting error details in dmesg as well as the error-state As we already capture all the information from the registers into the error-state, also dumping that to dmesg just generates noise that upsets CI and users alike (and doesn't provide us with any more information). v2: Chris Wilson dag out the relevant commit. Commit msg updated. Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170727110113.16942-1-tvrtko.ursulin@linux.intel.com --- drivers/gpu/drm/i915/i915_irq.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e682237e7009..196caa463edf 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2640,32 +2640,6 @@ static void i915_reset_device(struct drm_i915_private *dev_priv) KOBJ_CHANGE, reset_done_event); } -static inline void -i915_err_print_instdone(struct drm_i915_private *dev_priv, - struct intel_instdone *instdone) -{ - int slice; - int subslice; - - pr_err(" INSTDONE: 0x%08x\n", instdone->instdone); - - if (INTEL_GEN(dev_priv) <= 3) - return; - - pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common); - - if (INTEL_GEN(dev_priv) <= 6) - return; - - for_each_instdone_slice_subslice(dev_priv, slice, subslice) - pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", - slice, subslice, instdone->sampler[slice][subslice]); - - for_each_instdone_slice_subslice(dev_priv, slice, subslice) - pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n", - slice, subslice, instdone->row[slice][subslice]); -} - static void i915_clear_error_registers(struct drm_i915_private *dev_priv) { u32 eir; From d0604a24d4e47a0196552fe8147792ab68e55f0e Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 31 Jul 2017 10:08:11 +0200 Subject: [PATCH 088/179] drm/i915: Update DRIVER_DATE to 20170731 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2c7456f4ed38..d63645a521c4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -80,8 +80,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20170717" -#define DRIVER_TIMESTAMP 1500275179 +#define DRIVER_DATE "20170731" +#define DRIVER_TIMESTAMP 1501488491 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and * WARN_ON()) for hw state sanity checks to check for unexpected conditions From 09a92bc8773b4314e02b478e003fe5936ce85adb Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Mon, 24 Jul 2017 11:14:31 +0200 Subject: [PATCH 089/179] drm/i915: Fix out-of-bounds array access in bdw_load_gamma_lut bdw_load_gamma_lut is writing beyond the array to the maximum value. The intend of the function is to clamp values > 1 to 1, so write the intended color to the max register. This fixes the following KASAN warning: [ 197.020857] [IGT] kms_pipe_color: executing [ 197.063434] [IGT] kms_pipe_color: starting subtest ctm-0-25-pipe0 [ 197.078989] ================================================================== [ 197.079127] BUG: KASAN: slab-out-of-bounds in bdw_load_gamma_lut.isra.2+0x3b9/0x570 [i915] [ 197.079188] Read of size 2 at addr ffff8800d38db150 by task kms_pipe_color/1839 [ 197.079208] CPU: 2 PID: 1839 Comm: kms_pipe_color Tainted: G U 4.13.0-rc1-patser+ #5211 [ 197.079215] Hardware name: NUC5i7RYB, BIOS RYBDWi35.86A.0246.2015.0309.1355 03/09/2015 [ 197.079220] Call Trace: [ 197.079230] dump_stack+0x68/0x9e [ 197.079239] print_address_description+0x6f/0x250 [ 197.079251] kasan_report+0x216/0x370 [ 197.079374] ? bdw_load_gamma_lut.isra.2+0x3b9/0x570 [i915] [ 197.079451] ? gen8_write16+0x4e0/0x4e0 [i915] [ 197.079460] __asan_report_load2_noabort+0x14/0x20 [ 197.079535] bdw_load_gamma_lut.isra.2+0x3b9/0x570 [i915] [ 197.079612] broadwell_load_luts+0x1df/0x550 [i915] [ 197.079690] intel_color_load_luts+0x7b/0x80 [i915] [ 197.079764] intel_begin_crtc_commit+0x138/0x760 [i915] [ 197.079783] drm_atomic_helper_commit_planes_on_crtc+0x1a3/0x820 [drm_kms_helper] [ 197.079859] ? intel_pre_plane_update+0x571/0x580 [i915] [ 197.079937] intel_update_crtc+0x238/0x330 [i915] [ 197.080016] intel_update_crtcs+0x10f/0x210 [i915] [ 197.080092] intel_atomic_commit_tail+0x1552/0x3340 [i915] [ 197.080101] ? _raw_spin_unlock+0x3c/0x40 [ 197.080110] ? __queue_work+0xb40/0xbf0 [ 197.080188] ? skl_update_crtcs+0xc00/0xc00 [i915] [ 197.080195] ? trace_hardirqs_on+0xd/0x10 [ 197.080269] ? intel_atomic_commit_ready+0x128/0x13c [i915] [ 197.080329] ? __i915_sw_fence_complete+0x5b8/0x6d0 [i915] [ 197.080336] ? debug_object_activate+0x39e/0x580 [ 197.080397] ? i915_sw_fence_await+0x30/0x30 [i915] [ 197.080409] ? __might_sleep+0x15b/0x180 [ 197.080483] intel_atomic_commit+0x944/0xa70 [i915] [ 197.080490] ? refcount_dec_and_test+0x11/0x20 [ 197.080567] ? intel_atomic_commit_tail+0x3340/0x3340 [i915] [ 197.080597] ? drm_atomic_crtc_set_property+0x303/0x580 [drm] [ 197.080674] ? intel_atomic_commit_tail+0x3340/0x3340 [i915] [ 197.080704] drm_atomic_commit+0xd7/0xe0 [drm] [ 197.080722] drm_atomic_helper_crtc_set_property+0xec/0x130 [drm_kms_helper] [ 197.080749] drm_mode_crtc_set_obj_prop+0x7d/0xb0 [drm] [ 197.080775] drm_mode_obj_set_property_ioctl+0x50b/0x5d0 [drm] [ 197.080783] ? __might_fault+0x104/0x180 [ 197.080809] ? drm_mode_obj_find_prop_id+0x160/0x160 [drm] [ 197.080838] ? drm_mode_obj_find_prop_id+0x160/0x160 [drm] [ 197.080861] drm_ioctl_kernel+0x154/0x1a0 [drm] [ 197.080885] drm_ioctl+0x624/0x8f0 [drm] [ 197.080910] ? drm_mode_obj_find_prop_id+0x160/0x160 [drm] [ 197.080934] ? drm_getunique+0x210/0x210 [drm] [ 197.080943] ? __handle_mm_fault+0x1bd0/0x1ce0 [ 197.080949] ? lock_downgrade+0x610/0x610 [ 197.080957] ? __lru_cache_add+0x15a/0x180 [ 197.080967] do_vfs_ioctl+0xd92/0xe40 [ 197.080975] ? ioctl_preallocate+0x1b0/0x1b0 [ 197.080982] ? selinux_capable+0x20/0x20 [ 197.080991] ? __do_page_fault+0x7b7/0x9a0 [ 197.080997] ? lock_downgrade+0x5bb/0x610 [ 197.081007] ? security_file_ioctl+0x57/0x90 [ 197.081016] SyS_ioctl+0x4e/0x80 [ 197.081024] entry_SYSCALL_64_fastpath+0x18/0xad [ 197.081030] RIP: 0033:0x7f61f287a987 [ 197.081035] RSP: 002b:00007fff7d44d188 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 197.081043] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f61f287a987 [ 197.081048] RDX: 00007fff7d44d1c0 RSI: 00000000c01864ba RDI: 0000000000000003 [ 197.081053] RBP: 00007f61f2b3eb00 R08: 0000000000000059 R09: 0000000000000000 [ 197.081058] R10: 0000002ea5c4a290 R11: 0000000000000246 R12: 00007f61f2b3eb58 [ 197.081063] R13: 0000000000001010 R14: 00007f61f2b3eb58 R15: 0000000000002702 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101659 Signed-off-by: Maarten Lankhorst Reported-by: Martin Peres Cc: Martin Peres Fixes: 82cf435b3134 ("drm/i915: Implement color management on bdw/skl/bxt/kbl") Cc: Shashank Sharma Cc: Kiran S Kumar Cc: Kausal Malladi Cc: Lionel Landwerlin Cc: Matt Roper Cc: Daniel Vetter Cc: Jani Nikula Cc: intel-gfx@lists.freedesktop.org Cc: # v4.7+ Link: https://patchwork.freedesktop.org/patch/msgid/20170724091431.24251-1-maarten.lankhorst@linux.intel.com Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_color.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 30ed70c3846d..8e4e829682b9 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -441,6 +441,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset) } /* Program the max register to clamp values > 1.0. */ + i = lut_size - 1; I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), drm_color_lut_extract(lut[i].red, 16)); I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), From 59f3da1e0ecb48e28c2ff6ffed4c354997452e77 Mon Sep 17 00:00:00 2001 From: Bhumika Goyal Date: Wed, 2 Aug 2017 22:50:47 +0530 Subject: [PATCH 090/179] drm/i915: add const to bin_attribute Add const to bin_attribute structures as they are only passed to the functions sysfs_{remove/create}_bin_file or device_{remove/create}_bin_file. The corresponding arguments are of type const, so declare the structures to be const. Signed-off-by: Bhumika Goyal Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/1501694447-14356-1-git-send-email-bhumirks@gmail.com --- drivers/gpu/drm/i915/i915_sysfs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 7fcf00622c4c..d61c8727f756 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -220,7 +220,7 @@ out: return ret; } -static struct bin_attribute dpf_attrs = { +static const struct bin_attribute dpf_attrs = { .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, .read = i915_l3_read, @@ -229,7 +229,7 @@ static struct bin_attribute dpf_attrs = { .private = (void *)0 }; -static struct bin_attribute dpf_attrs_1 = { +static const struct bin_attribute dpf_attrs_1 = { .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, .read = i915_l3_read, @@ -532,7 +532,7 @@ static ssize_t error_state_write(struct file *file, struct kobject *kobj, return count; } -static struct bin_attribute error_state_attr = { +static const struct bin_attribute error_state_attr = { .attr.name = "error", .attr.mode = S_IRUSR | S_IWUSR, .size = 0, From 01d928e9a1644eb2e28f684905f888e700c7b9dc Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 3 Aug 2017 17:58:07 +0100 Subject: [PATCH 091/179] drm/i915/perf: fix flex eu registers programming We were reserving fewer dwords in the ring than necessary. Indeed we're always writing all registers once, so discard the actual number of registers given by the user and just program the whitelisted ones once. Fixes: 19f81df2859e ("drm/i915/perf: Add OA unit support for Gen 8+") Reported-by: Matthew Auld Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld Cc: # v4.12+ Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-6-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 96682fd86f82..df78bfa9e574 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1601,11 +1601,11 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) u32 *cs; int i; - cs = intel_ring_begin(req, n_flex_regs * 2 + 4); + cs = intel_ring_begin(req, ARRAY_SIZE(flex_mmio) * 2 + 4); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(n_flex_regs + 1); + *cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1); *cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL); *cs++ = (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) | From 701f8231a2fe171f8b0f4659cb33cae754be8c3f Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 3 Aug 2017 17:58:08 +0100 Subject: [PATCH 092/179] drm/i915/perf: prune OA configs In the following commit we'll introduce loadable userspace configs. This change reworks how configurations are handled in the perf driver and retains only the test configurations in kernel space. We now store the test config in dev_priv and resolve the id only once when opening the perf stream. The OA config is then handled through a pointer to the structure holding the configuration details. v2: Rework how test configs are handled (Lionel) v3: Use u32 to hold number of register (Matthew) v4: Removed unused dev_priv->perf.oa.current_config variable (Matthew) v5: Lock device when accessing exclusive_stream (Lionel) v6: Ensure OACTXCONTROL is always reprogrammed (Lionel) v7: Switch a couple of index variable from int to u32 (Matthew) Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-3-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 44 +- drivers/gpu/drm/i915/i915_oa_bdw.c | 5314 +------------------------ drivers/gpu/drm/i915/i915_oa_bdw.h | 8 +- drivers/gpu/drm/i915/i915_oa_bxt.c | 2629 +----------- drivers/gpu/drm/i915/i915_oa_bxt.h | 8 +- drivers/gpu/drm/i915/i915_oa_chv.c | 2812 +------------ drivers/gpu/drm/i915/i915_oa_chv.h | 8 +- drivers/gpu/drm/i915/i915_oa_glk.c | 2541 +----------- drivers/gpu/drm/i915/i915_oa_glk.h | 8 +- drivers/gpu/drm/i915/i915_oa_hsw.c | 772 +--- drivers/gpu/drm/i915/i915_oa_hsw.h | 8 +- drivers/gpu/drm/i915/i915_oa_kblgt2.c | 2929 +------------- drivers/gpu/drm/i915/i915_oa_kblgt2.h | 8 +- drivers/gpu/drm/i915/i915_oa_kblgt3.c | 2978 +------------- drivers/gpu/drm/i915/i915_oa_kblgt3.h | 8 +- drivers/gpu/drm/i915/i915_oa_sklgt2.c | 3418 +--------------- drivers/gpu/drm/i915/i915_oa_sklgt2.h | 8 +- drivers/gpu/drm/i915/i915_oa_sklgt3.c | 2977 +------------- drivers/gpu/drm/i915/i915_oa_sklgt3.h | 8 +- drivers/gpu/drm/i915/i915_oa_sklgt4.c | 3031 +------------- drivers/gpu/drm/i915/i915_oa_sklgt4.h | 8 +- drivers/gpu/drm/i915/i915_perf.c | 316 +- 22 files changed, 395 insertions(+), 29446 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d63645a521c4..32749425d7bf 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1921,6 +1921,22 @@ struct i915_oa_reg { u32 value; }; +struct i915_oa_config { + char uuid[UUID_STRING_LEN + 1]; + int id; + + const struct i915_oa_reg *mux_regs; + u32 mux_regs_len; + const struct i915_oa_reg *b_counter_regs; + u32 b_counter_regs_len; + const struct i915_oa_reg *flex_regs; + u32 flex_regs_len; + + struct attribute_group sysfs_metric; + struct attribute *attrs[2]; + struct device_attribute sysfs_metric_id; +}; + struct i915_perf_stream; /** @@ -2033,6 +2049,11 @@ struct i915_perf_stream { * type of configured stream. */ const struct i915_perf_stream_ops *ops; + + /** + * @oa_config: The OA configuration used by the stream. + */ + struct i915_oa_config *oa_config; }; /** @@ -2056,21 +2077,14 @@ struct i915_oa_ops { */ void (*init_oa_buffer)(struct drm_i915_private *dev_priv); - /** - * @select_metric_set: The auto generated code that checks whether a - * requested OA config is applicable to the system and if so sets up - * the mux, oa and flex eu register config pointers according to the - * current dev_priv->perf.oa.metrics_set. - */ - int (*select_metric_set)(struct drm_i915_private *dev_priv); - /** * @enable_metric_set: Selects and applies any MUX configuration to set * up the Boolean and Custom (B/C) counters that are part of the * counter reports being sampled. May apply system constraints such as * disabling EU clock gating as required. */ - int (*enable_metric_set)(struct drm_i915_private *dev_priv); + int (*enable_metric_set)(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config); /** * @disable_metric_set: Remove system constraints associated with using @@ -2452,16 +2466,7 @@ struct drm_i915_private { int period_exponent; int timestamp_frequency; - int metrics_set; - - const struct i915_oa_reg *mux_regs[6]; - int mux_regs_lens[6]; - int n_mux_configs; - - const struct i915_oa_reg *b_counter_regs; - int b_counter_regs_len; - const struct i915_oa_reg *flex_regs; - int flex_regs_len; + struct i915_oa_config test_config; struct { struct i915_vma *vma; @@ -2548,7 +2553,6 @@ struct drm_i915_private { struct i915_oa_ops ops; const struct i915_oa_format *oa_formats; - int n_builtin_sets; } oa; } perf; diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c index d4462c2aaaee..187067001179 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.c +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c @@ -31,3981 +31,6 @@ #include "i915_drv.h" #include "i915_oa_bdw.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_DATA_PORT_READS_COALESCING, - METRIC_SET_ID_DATA_PORT_WRITES_COALESCING, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_L3_4, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER_1, - METRIC_SET_ID_SAMPLER_2, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_bdw = 22; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_0_slices_0x01[] = { - { _MMIO(0x9888), 0x143f000f }, - { _MMIO(0x9888), 0x14110014 }, - { _MMIO(0x9888), 0x14310014 }, - { _MMIO(0x9888), 0x14bf000f }, - { _MMIO(0x9888), 0x118a0317 }, - { _MMIO(0x9888), 0x13837be0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x005c4000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x003d8000 }, - { _MMIO(0x9888), 0x183d0800 }, - { _MMIO(0x9888), 0x0a3f0023 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x00584000 }, - { _MMIO(0x9888), 0x08584000 }, - { _MMIO(0x9888), 0x0a5a4000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b8000 }, - { _MMIO(0x9888), 0x185b2400 }, - { _MMIO(0x9888), 0x0a1d4000 }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18380001 }, - { _MMIO(0x9888), 0x00392000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a391000 }, - { _MMIO(0x9888), 0x00104000 }, - { _MMIO(0x9888), 0x08104000 }, - { _MMIO(0x9888), 0x00110030 }, - { _MMIO(0x9888), 0x08110031 }, - { _MMIO(0x9888), 0x10110000 }, - { _MMIO(0x9888), 0x00134000 }, - { _MMIO(0x9888), 0x16130020 }, - { _MMIO(0x9888), 0x06308000 }, - { _MMIO(0x9888), 0x08308000 }, - { _MMIO(0x9888), 0x06311800 }, - { _MMIO(0x9888), 0x08311880 }, - { _MMIO(0x9888), 0x10310000 }, - { _MMIO(0x9888), 0x0e334000 }, - { _MMIO(0x9888), 0x16330080 }, - { _MMIO(0x9888), 0x0abf1180 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x0ada8000 }, - { _MMIO(0x9888), 0x0a9d8000 }, - { _MMIO(0x9888), 0x109f0002 }, - { _MMIO(0x9888), 0x0ab94000 }, - { _MMIO(0x9888), 0x0d888000 }, - { _MMIO(0x9888), 0x038a0380 }, - { _MMIO(0x9888), 0x058a000e }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a00a0 }, - { _MMIO(0x9888), 0x078a0000 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x238b2820 }, - { _MMIO(0x9888), 0x258b2550 }, - { _MMIO(0x9888), 0x198c1000 }, - { _MMIO(0x9888), 0x0b8d8000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x0d831021 }, - { _MMIO(0x9888), 0x0f83572f }, - { _MMIO(0x9888), 0x01835680 }, - { _MMIO(0x9888), 0x0383002c }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830001 }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0x9888), 0x4d801110 }, - { _MMIO(0x9888), 0x4f800331 }, - { _MMIO(0x9888), 0x43800802 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801465 }, - { _MMIO(0x9888), 0x53801111 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800ca5 }, - { _MMIO(0x9888), 0x41800003 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_1_slices_0x02[] = { - { _MMIO(0x9888), 0x143f000f }, - { _MMIO(0x9888), 0x14bf000f }, - { _MMIO(0x9888), 0x14910014 }, - { _MMIO(0x9888), 0x14b10014 }, - { _MMIO(0x9888), 0x118a0317 }, - { _MMIO(0x9888), 0x13837be0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x0a3f0023 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x0a5a4000 }, - { _MMIO(0x9888), 0x0a1d4000 }, - { _MMIO(0x9888), 0x0e1f8000 }, - { _MMIO(0x9888), 0x0a391000 }, - { _MMIO(0x9888), 0x00dc4000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x00bd8000 }, - { _MMIO(0x9888), 0x18bd0800 }, - { _MMIO(0x9888), 0x0abf1180 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x00d84000 }, - { _MMIO(0x9888), 0x08d84000 }, - { _MMIO(0x9888), 0x0ada8000 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db2400 }, - { _MMIO(0x9888), 0x0a9d8000 }, - { _MMIO(0x9888), 0x0c9f0800 }, - { _MMIO(0x9888), 0x0e9f2a00 }, - { _MMIO(0x9888), 0x109f0002 }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b80001 }, - { _MMIO(0x9888), 0x00b92000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab94000 }, - { _MMIO(0x9888), 0x00904000 }, - { _MMIO(0x9888), 0x08904000 }, - { _MMIO(0x9888), 0x00910030 }, - { _MMIO(0x9888), 0x08910031 }, - { _MMIO(0x9888), 0x10910000 }, - { _MMIO(0x9888), 0x00934000 }, - { _MMIO(0x9888), 0x16930020 }, - { _MMIO(0x9888), 0x06b08000 }, - { _MMIO(0x9888), 0x08b08000 }, - { _MMIO(0x9888), 0x06b11800 }, - { _MMIO(0x9888), 0x08b11880 }, - { _MMIO(0x9888), 0x10b10000 }, - { _MMIO(0x9888), 0x0eb34000 }, - { _MMIO(0x9888), 0x16b30080 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88b800 }, - { _MMIO(0x9888), 0x038a0380 }, - { _MMIO(0x9888), 0x058a000e }, - { _MMIO(0x9888), 0x1b8a0080 }, - { _MMIO(0x9888), 0x078a0000 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x238b2840 }, - { _MMIO(0x9888), 0x258b26a0 }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1100 }, - { _MMIO(0x9888), 0x018d2000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8d8000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x0d831021 }, - { _MMIO(0x9888), 0x0f83572f }, - { _MMIO(0x9888), 0x01835680 }, - { _MMIO(0x9888), 0x0383002c }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830001 }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0x9888), 0x4d801550 }, - { _MMIO(0x9888), 0x4f800331 }, - { _MMIO(0x9888), 0x43800802 }, - { _MMIO(0x9888), 0x51800400 }, - { _MMIO(0x9888), 0x458004a1 }, - { _MMIO(0x9888), 0x53805555 }, - { _MMIO(0x9888), 0x47800421 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f801421 }, - { _MMIO(0x9888), 0x41800845 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) { - regs[n] = mux_config_render_basic_0_slices_0x01; - lens[n] = ARRAY_SIZE(mux_config_render_basic_0_slices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) { - regs[n] = mux_config_render_basic_1_slices_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_basic_1_slices_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01[] = { - { _MMIO(0x9888), 0x105c00e0 }, - { _MMIO(0x9888), 0x105800e0 }, - { _MMIO(0x9888), 0x103800e0 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x065c2100 }, - { _MMIO(0x9888), 0x0a5c0041 }, - { _MMIO(0x9888), 0x0c5c6600 }, - { _MMIO(0x9888), 0x005c6580 }, - { _MMIO(0x9888), 0x085c8000 }, - { _MMIO(0x9888), 0x0e5c8000 }, - { _MMIO(0x9888), 0x00580042 }, - { _MMIO(0x9888), 0x08582080 }, - { _MMIO(0x9888), 0x0c58004c }, - { _MMIO(0x9888), 0x0e582580 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x185b1000 }, - { _MMIO(0x9888), 0x1a5b0104 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x08380042 }, - { _MMIO(0x9888), 0x0a382080 }, - { _MMIO(0x9888), 0x0e38404c }, - { _MMIO(0x9888), 0x0238404b }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x16380000 }, - { _MMIO(0x9888), 0x18381145 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b5550 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f850a80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x03844000 }, - { _MMIO(0x9888), 0x17808137 }, - { _MMIO(0x9888), 0x1980c147 }, - { _MMIO(0x9888), 0x1b80c0e5 }, - { _MMIO(0x9888), 0x1d80c0e3 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x13804000 }, - { _MMIO(0x9888), 0x15800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x4f800111 }, - { _MMIO(0x9888), 0x43800062 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800062 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800062 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f801062 }, - { _MMIO(0x9888), 0x41801084 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_2_slices_0x02[] = { - { _MMIO(0x9888), 0x10dc00e0 }, - { _MMIO(0x9888), 0x10d800e0 }, - { _MMIO(0x9888), 0x10b800e0 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x06dc2100 }, - { _MMIO(0x9888), 0x0adc0041 }, - { _MMIO(0x9888), 0x0cdc6600 }, - { _MMIO(0x9888), 0x00dc6580 }, - { _MMIO(0x9888), 0x08dc8000 }, - { _MMIO(0x9888), 0x0edc8000 }, - { _MMIO(0x9888), 0x00d80042 }, - { _MMIO(0x9888), 0x08d82080 }, - { _MMIO(0x9888), 0x0cd8004c }, - { _MMIO(0x9888), 0x0ed82580 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x18db1000 }, - { _MMIO(0x9888), 0x1adb0104 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x08b80042 }, - { _MMIO(0x9888), 0x0ab82080 }, - { _MMIO(0x9888), 0x0eb8404c }, - { _MMIO(0x9888), 0x02b8404b }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x16b80000 }, - { _MMIO(0x9888), 0x18b81145 }, - { _MMIO(0x9888), 0x04b80000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b92000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x238b0540 }, - { _MMIO(0x9888), 0x258baaa0 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d2000 }, - { _MMIO(0x9888), 0x1f850a80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x03844000 }, - { _MMIO(0x9888), 0x17808137 }, - { _MMIO(0x9888), 0x1980c147 }, - { _MMIO(0x9888), 0x1b80c0e5 }, - { _MMIO(0x9888), 0x1d80c0e3 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x13804000 }, - { _MMIO(0x9888), 0x15800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d805000 }, - { _MMIO(0x9888), 0x4f800555 }, - { _MMIO(0x9888), 0x43800062 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800062 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800062 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800062 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) { - regs[n] = mux_config_compute_basic_0_slices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) { - regs[n] = mux_config_compute_basic_2_slices_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_2_slices_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0a1e0000 }, - { _MMIO(0x9888), 0x0c1f000f }, - { _MMIO(0x9888), 0x10176800 }, - { _MMIO(0x9888), 0x1191001f }, - { _MMIO(0x9888), 0x0b880320 }, - { _MMIO(0x9888), 0x01890c40 }, - { _MMIO(0x9888), 0x118a1c00 }, - { _MMIO(0x9888), 0x118d7c00 }, - { _MMIO(0x9888), 0x118e0020 }, - { _MMIO(0x9888), 0x118f4c00 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x13900001 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x0c3d8000 }, - { _MMIO(0x9888), 0x06584000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x081e0040 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x021f5400 }, - { _MMIO(0x9888), 0x001f0000 }, - { _MMIO(0x9888), 0x101f0010 }, - { _MMIO(0x9888), 0x0e1f0080 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c13c000 }, - { _MMIO(0x9888), 0x06164000 }, - { _MMIO(0x9888), 0x06170012 }, - { _MMIO(0x9888), 0x00170000 }, - { _MMIO(0x9888), 0x01910005 }, - { _MMIO(0x9888), 0x07880002 }, - { _MMIO(0x9888), 0x01880c00 }, - { _MMIO(0x9888), 0x0f880000 }, - { _MMIO(0x9888), 0x0d880000 }, - { _MMIO(0x9888), 0x05880000 }, - { _MMIO(0x9888), 0x09890032 }, - { _MMIO(0x9888), 0x078a0800 }, - { _MMIO(0x9888), 0x0f8a0a00 }, - { _MMIO(0x9888), 0x198a4000 }, - { _MMIO(0x9888), 0x1b8a2000 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x038a4000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b54c0 }, - { _MMIO(0x9888), 0x258baa55 }, - { _MMIO(0x9888), 0x278b0019 }, - { _MMIO(0x9888), 0x198c0100 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x0f8d0015 }, - { _MMIO(0x9888), 0x018d1000 }, - { _MMIO(0x9888), 0x098d8000 }, - { _MMIO(0x9888), 0x0b8df000 }, - { _MMIO(0x9888), 0x0d8d3000 }, - { _MMIO(0x9888), 0x038de000 }, - { _MMIO(0x9888), 0x058d3000 }, - { _MMIO(0x9888), 0x0d8e0004 }, - { _MMIO(0x9888), 0x058e000c }, - { _MMIO(0x9888), 0x098e0000 }, - { _MMIO(0x9888), 0x078e0000 }, - { _MMIO(0x9888), 0x038e0000 }, - { _MMIO(0x9888), 0x0b8f0020 }, - { _MMIO(0x9888), 0x198f0c00 }, - { _MMIO(0x9888), 0x078f8000 }, - { _MMIO(0x9888), 0x098f4000 }, - { _MMIO(0x9888), 0x0b900980 }, - { _MMIO(0x9888), 0x03900d80 }, - { _MMIO(0x9888), 0x01900000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801111 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f801011 }, - { _MMIO(0x9888), 0x43800443 }, - { _MMIO(0x9888), 0x51801111 }, - { _MMIO(0x9888), 0x45800422 }, - { _MMIO(0x9888), 0x53801111 }, - { _MMIO(0x9888), 0x47800c60 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800422 }, - { _MMIO(0x9888), 0x41800021 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x198b0343 }, - { _MMIO(0x9888), 0x13845800 }, - { _MMIO(0x9888), 0x15840018 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b6b62 }, - { _MMIO(0x9888), 0x078b006a }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b0000 }, - { _MMIO(0x9888), 0x258b0000 }, - { _MMIO(0x9888), 0x1f85a080 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385000a }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01840018 }, - { _MMIO(0x9888), 0x07844c80 }, - { _MMIO(0x9888), 0x09840d9a }, - { _MMIO(0x9888), 0x0b840e9c }, - { _MMIO(0x9888), 0x0d840f9e }, - { _MMIO(0x9888), 0x0f840010 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x03848000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x2f8000e5 }, - { _MMIO(0x9888), 0x138080e3 }, - { _MMIO(0x9888), 0x1580c0e1 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f804000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800842 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801042 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800084 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x198b0343 }, - { _MMIO(0x9888), 0x13845400 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3d800805 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b6b62 }, - { _MMIO(0x9888), 0x078b006a }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b0000 }, - { _MMIO(0x9888), 0x258b0000 }, - { _MMIO(0x9888), 0x1f85a080 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x23850002 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01840010 }, - { _MMIO(0x9888), 0x07844880 }, - { _MMIO(0x9888), 0x09840992 }, - { _MMIO(0x9888), 0x0b840a94 }, - { _MMIO(0x9888), 0x0d840b96 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x03848000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x2d800147 }, - { _MMIO(0x9888), 0x2f8000e5 }, - { _MMIO(0x9888), 0x138080e3 }, - { _MMIO(0x9888), 0x1580c0e1 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800842 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801082 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800084 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x143d0160 }, - { _MMIO(0x9888), 0x163d2800 }, - { _MMIO(0x9888), 0x183d0120 }, - { _MMIO(0x9888), 0x105800e0 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x003d0011 }, - { _MMIO(0x9888), 0x063d0900 }, - { _MMIO(0x9888), 0x083d0a13 }, - { _MMIO(0x9888), 0x0a3d0b15 }, - { _MMIO(0x9888), 0x0c3d2317 }, - { _MMIO(0x9888), 0x043d21b7 }, - { _MMIO(0x9888), 0x103d0000 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0e5825c1 }, - { _MMIO(0x9888), 0x00586100 }, - { _MMIO(0x9888), 0x0258204c }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x0c58c000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5400 }, - { _MMIO(0x9888), 0x1a5b0155 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_2_subslices_0x02[] = { - { _MMIO(0x9888), 0x105c00e0 }, - { _MMIO(0x9888), 0x145b0160 }, - { _MMIO(0x9888), 0x165b2800 }, - { _MMIO(0x9888), 0x185b0120 }, - { _MMIO(0x9888), 0x0e5c25c1 }, - { _MMIO(0x9888), 0x005c6100 }, - { _MMIO(0x9888), 0x025c204c }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x005b0011 }, - { _MMIO(0x9888), 0x065b0900 }, - { _MMIO(0x9888), 0x085b0a13 }, - { _MMIO(0x9888), 0x0a5b0b15 }, - { _MMIO(0x9888), 0x0c5b2317 }, - { _MMIO(0x9888), 0x045b21b7 }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x0e5b0000 }, - { _MMIO(0x9888), 0x1a5b0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_4_subslices_0x04[] = { - { _MMIO(0x9888), 0x103800e0 }, - { _MMIO(0x9888), 0x143a0160 }, - { _MMIO(0x9888), 0x163a2800 }, - { _MMIO(0x9888), 0x183a0120 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e38a5c1 }, - { _MMIO(0x9888), 0x0038a100 }, - { _MMIO(0x9888), 0x0238204c }, - { _MMIO(0x9888), 0x16388000 }, - { _MMIO(0x9888), 0x183802aa }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06380000 }, - { _MMIO(0x9888), 0x08388000 }, - { _MMIO(0x9888), 0x0a388000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x003a0011 }, - { _MMIO(0x9888), 0x063a0900 }, - { _MMIO(0x9888), 0x083a0a13 }, - { _MMIO(0x9888), 0x0a3a0b15 }, - { _MMIO(0x9888), 0x0c3a2317 }, - { _MMIO(0x9888), 0x043a21b7 }, - { _MMIO(0x9888), 0x103a0000 }, - { _MMIO(0x9888), 0x0e3a0000 }, - { _MMIO(0x9888), 0x1a3a0000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_1_subslices_0x08[] = { - { _MMIO(0x9888), 0x14bd0160 }, - { _MMIO(0x9888), 0x16bd2800 }, - { _MMIO(0x9888), 0x18bd0120 }, - { _MMIO(0x9888), 0x10d800e0 }, - { _MMIO(0x9888), 0x00dcc000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x00bd0011 }, - { _MMIO(0x9888), 0x06bd0900 }, - { _MMIO(0x9888), 0x08bd0a13 }, - { _MMIO(0x9888), 0x0abd0b15 }, - { _MMIO(0x9888), 0x0cbd2317 }, - { _MMIO(0x9888), 0x04bd21b7 }, - { _MMIO(0x9888), 0x10bd0000 }, - { _MMIO(0x9888), 0x0ebd0000 }, - { _MMIO(0x9888), 0x1abd0000 }, - { _MMIO(0x9888), 0x0ed825c1 }, - { _MMIO(0x9888), 0x00d86100 }, - { _MMIO(0x9888), 0x02d8204c }, - { _MMIO(0x9888), 0x06d88000 }, - { _MMIO(0x9888), 0x08d8c000 }, - { _MMIO(0x9888), 0x0ad8c000 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x04d8c000 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x0edb4000 }, - { _MMIO(0x9888), 0x18db5400 }, - { _MMIO(0x9888), 0x1adb0155 }, - { _MMIO(0x9888), 0x02db4000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db4000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b81555 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_3_subslices_0x10[] = { - { _MMIO(0x9888), 0x10dc00e0 }, - { _MMIO(0x9888), 0x14db0160 }, - { _MMIO(0x9888), 0x16db2800 }, - { _MMIO(0x9888), 0x18db0120 }, - { _MMIO(0x9888), 0x0edc25c1 }, - { _MMIO(0x9888), 0x00dc6100 }, - { _MMIO(0x9888), 0x02dc204c }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x00db0011 }, - { _MMIO(0x9888), 0x06db0900 }, - { _MMIO(0x9888), 0x08db0a13 }, - { _MMIO(0x9888), 0x0adb0b15 }, - { _MMIO(0x9888), 0x0cdb2317 }, - { _MMIO(0x9888), 0x04db21b7 }, - { _MMIO(0x9888), 0x10db0000 }, - { _MMIO(0x9888), 0x0edb0000 }, - { _MMIO(0x9888), 0x1adb0000 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b81555 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_5_subslices_0x20[] = { - { _MMIO(0x9888), 0x10b800e0 }, - { _MMIO(0x9888), 0x14ba0160 }, - { _MMIO(0x9888), 0x16ba2800 }, - { _MMIO(0x9888), 0x18ba0120 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb8a5c1 }, - { _MMIO(0x9888), 0x00b8a100 }, - { _MMIO(0x9888), 0x02b8204c }, - { _MMIO(0x9888), 0x16b88000 }, - { _MMIO(0x9888), 0x18b802aa }, - { _MMIO(0x9888), 0x04b80000 }, - { _MMIO(0x9888), 0x06b80000 }, - { _MMIO(0x9888), 0x08b88000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x00ba0011 }, - { _MMIO(0x9888), 0x06ba0900 }, - { _MMIO(0x9888), 0x08ba0a13 }, - { _MMIO(0x9888), 0x0aba0b15 }, - { _MMIO(0x9888), 0x0cba2317 }, - { _MMIO(0x9888), 0x04ba21b7 }, - { _MMIO(0x9888), 0x10ba0000 }, - { _MMIO(0x9888), 0x0eba0000 }, - { _MMIO(0x9888), 0x1aba0000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 6); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 6); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_compute_extended_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) { - regs[n] = mux_config_compute_extended_1_subslices_0x08; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_1_subslices_0x08); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) { - regs[n] = mux_config_compute_extended_2_subslices_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_2_subslices_0x02); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) { - regs[n] = mux_config_compute_extended_3_subslices_0x10; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_3_subslices_0x10); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) { - regs[n] = mux_config_compute_extended_4_subslices_0x04; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_4_subslices_0x04); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) { - regs[n] = mux_config_compute_extended_5_subslices_0x20; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_5_subslices_0x20); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x143f00b3 }, - { _MMIO(0x9888), 0x14bf00b3 }, - { _MMIO(0x9888), 0x138303c0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800805 }, - { _MMIO(0x9888), 0x003f0029 }, - { _MMIO(0x9888), 0x063f1400 }, - { _MMIO(0x9888), 0x083f1225 }, - { _MMIO(0x9888), 0x0e3f1327 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x005a4000 }, - { _MMIO(0x9888), 0x065a8000 }, - { _MMIO(0x9888), 0x085ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x001d4000 }, - { _MMIO(0x9888), 0x061d8000 }, - { _MMIO(0x9888), 0x081dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1f2a00 }, - { _MMIO(0x9888), 0x101f0280 }, - { _MMIO(0x9888), 0x00391000 }, - { _MMIO(0x9888), 0x06394000 }, - { _MMIO(0x9888), 0x08395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x0abf1429 }, - { _MMIO(0x9888), 0x0cbf1225 }, - { _MMIO(0x9888), 0x00bf1380 }, - { _MMIO(0x9888), 0x02bf0026 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x0adac000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02da4000 }, - { _MMIO(0x9888), 0x0a9dc000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029d4000 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f002a }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0ab95000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b91000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f880003 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a8020 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x238b0520 }, - { _MMIO(0x9888), 0x258ba950 }, - { _MMIO(0x9888), 0x278b0016 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0001 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x03835180 }, - { _MMIO(0x9888), 0x05834022 }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x4f800111 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800840 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800800 }, - { _MMIO(0x9888), 0x418014a2 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_data_port_reads_coalescing[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0xba98ba98 }, - { _MMIO(0x2748), 0xba98ba98 }, - { _MMIO(0x2744), 0x00003377 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fff2 }, - { _MMIO(0x2774), 0x00007ff0 }, - { _MMIO(0x2778), 0x0007ffe2 }, - { _MMIO(0x277c), 0x00007ff0 }, - { _MMIO(0x2780), 0x0007ffc2 }, - { _MMIO(0x2784), 0x00007ff0 }, - { _MMIO(0x2788), 0x0007ff82 }, - { _MMIO(0x278c), 0x00007ff0 }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000bfef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000bfdf }, - { _MMIO(0x27a0), 0x0007fffa }, - { _MMIO(0x27a4), 0x0000bfbf }, - { _MMIO(0x27a8), 0x0007fffa }, - { _MMIO(0x27ac), 0x0000bf7f }, -}; - -static const struct i915_oa_reg flex_eu_config_data_port_reads_coalescing[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_data_port_reads_coalescing_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x103d0005 }, - { _MMIO(0x9888), 0x163d240b }, - { _MMIO(0x9888), 0x1058022f }, - { _MMIO(0x9888), 0x185b5520 }, - { _MMIO(0x9888), 0x198b0003 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065cc000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025c4000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x003d0000 }, - { _MMIO(0x9888), 0x063d00b0 }, - { _MMIO(0x9888), 0x083d0182 }, - { _MMIO(0x9888), 0x0a3d10a0 }, - { _MMIO(0x9888), 0x0c3d11a2 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x183d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0e582242 }, - { _MMIO(0x9888), 0x00586700 }, - { _MMIO(0x9888), 0x0258004f }, - { _MMIO(0x9888), 0x0658c000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x0c58c000 }, - { _MMIO(0x9888), 0x045b6300 }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x1a5b0155 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x0a5b0000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faaa0 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x0639a000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x04398000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b0062 }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b5555 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800001 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800041 }, -}; - -static int -get_data_port_reads_coalescing_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_data_port_reads_coalescing_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_data_port_reads_coalescing_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_data_port_writes_coalescing[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0xba98ba98 }, - { _MMIO(0x2748), 0xba98ba98 }, - { _MMIO(0x2744), 0x00003377 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ff72 }, - { _MMIO(0x2774), 0x0000bfd0 }, - { _MMIO(0x2778), 0x0007ff62 }, - { _MMIO(0x277c), 0x0000bfd0 }, - { _MMIO(0x2780), 0x0007ff42 }, - { _MMIO(0x2784), 0x0000bfd0 }, - { _MMIO(0x2788), 0x0007ff02 }, - { _MMIO(0x278c), 0x0000bfd0 }, - { _MMIO(0x2790), 0x0005fff2 }, - { _MMIO(0x2794), 0x0000bfd0 }, - { _MMIO(0x2798), 0x0005ffe2 }, - { _MMIO(0x279c), 0x0000bfd0 }, - { _MMIO(0x27a0), 0x0005ffc2 }, - { _MMIO(0x27a4), 0x0000bfd0 }, - { _MMIO(0x27a8), 0x0005ff82 }, - { _MMIO(0x27ac), 0x0000bfd0 }, -}; - -static const struct i915_oa_reg flex_eu_config_data_port_writes_coalescing[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_data_port_writes_coalescing_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x103d0005 }, - { _MMIO(0x9888), 0x143d0120 }, - { _MMIO(0x9888), 0x163d2400 }, - { _MMIO(0x9888), 0x1058022f }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x198b0003 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065cc000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025c4000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x003d0000 }, - { _MMIO(0x9888), 0x063d0094 }, - { _MMIO(0x9888), 0x083d0182 }, - { _MMIO(0x9888), 0x0a3d1814 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x183d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0c3d0000 }, - { _MMIO(0x9888), 0x0e582242 }, - { _MMIO(0x9888), 0x00586700 }, - { _MMIO(0x9888), 0x0258004f }, - { _MMIO(0x9888), 0x0658c000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x045b6a80 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5400 }, - { _MMIO(0x9888), 0x1a5b0141 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x0a5b0000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faaa0 }, - { _MMIO(0x9888), 0x101f0282 }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381415 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x0639a000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x04398000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a82a0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b0062 }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b1555 }, - { _MMIO(0x9888), 0x278b0014 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x21852aaa }, - { _MMIO(0x9888), 0x23850028 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830141 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800001 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800041 }, -}; - -static int -get_data_port_writes_coalescing_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_data_port_writes_coalescing_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_data_port_writes_coalescing_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fff7 }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x105c0232 }, - { _MMIO(0x9888), 0x10580232 }, - { _MMIO(0x9888), 0x10380232 }, - { _MMIO(0x9888), 0x10dc0232 }, - { _MMIO(0x9888), 0x10d80232 }, - { _MMIO(0x9888), 0x10b80232 }, - { _MMIO(0x9888), 0x118e4400 }, - { _MMIO(0x9888), 0x025c6080 }, - { _MMIO(0x9888), 0x045c004b }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x00582080 }, - { _MMIO(0x9888), 0x0258004b }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x04386080 }, - { _MMIO(0x9888), 0x0638404b }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a380000 }, - { _MMIO(0x9888), 0x0c380000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0cdc25c1 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0ad825c1 }, - { _MMIO(0x9888), 0x18db4000 }, - { _MMIO(0x9888), 0x1adb0001 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb825c1 }, - { _MMIO(0x9888), 0x18b80154 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baa05 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x098dc000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x098e05c0 }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x198f0020 }, - { _MMIO(0x9888), 0x2185aa0a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x19835000 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x19808000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x51800040 }, - { _MMIO(0x9888), 0x43800400 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800c62 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801042 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x418014a4 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x10bf03da }, - { _MMIO(0x9888), 0x14bf0001 }, - { _MMIO(0x9888), 0x12980340 }, - { _MMIO(0x9888), 0x12990340 }, - { _MMIO(0x9888), 0x0cbf1187 }, - { _MMIO(0x9888), 0x0ebf1205 }, - { _MMIO(0x9888), 0x00bf0500 }, - { _MMIO(0x9888), 0x02bf042b }, - { _MMIO(0x9888), 0x04bf002c }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02dac000 }, - { _MMIO(0x9888), 0x04da4000 }, - { _MMIO(0x9888), 0x04983400 }, - { _MMIO(0x9888), 0x10980000 }, - { _MMIO(0x9888), 0x06990034 }, - { _MMIO(0x9888), 0x10990000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029dc000 }, - { _MMIO(0x9888), 0x049d4000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00ba }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b95000 }, - { _MMIO(0x9888), 0x04b91000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0cba4000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x258b800a }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x103f03da }, - { _MMIO(0x9888), 0x143f0001 }, - { _MMIO(0x9888), 0x12180340 }, - { _MMIO(0x9888), 0x12190340 }, - { _MMIO(0x9888), 0x0c3f1187 }, - { _MMIO(0x9888), 0x0e3f1205 }, - { _MMIO(0x9888), 0x003f0500 }, - { _MMIO(0x9888), 0x023f042b }, - { _MMIO(0x9888), 0x043f002c }, - { _MMIO(0x9888), 0x0c5ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x04183400 }, - { _MMIO(0x9888), 0x10180000 }, - { _MMIO(0x9888), 0x06190034 }, - { _MMIO(0x9888), 0x10190000 }, - { _MMIO(0x9888), 0x0c1dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x101f02a8 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00ba }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a4000 }, - { _MMIO(0x9888), 0x1b8aa800 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258b4005 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x121b0340 }, - { _MMIO(0x9888), 0x103f0274 }, - { _MMIO(0x9888), 0x123f0000 }, - { _MMIO(0x9888), 0x129b0340 }, - { _MMIO(0x9888), 0x10bf0274 }, - { _MMIO(0x9888), 0x12bf0000 }, - { _MMIO(0x9888), 0x041b3400 }, - { _MMIO(0x9888), 0x101b0000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x0a3d4000 }, - { _MMIO(0x9888), 0x003f0080 }, - { _MMIO(0x9888), 0x023f0793 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f002a }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04399000 }, - { _MMIO(0x9888), 0x069b0034 }, - { _MMIO(0x9888), 0x109b0000 }, - { _MMIO(0x9888), 0x06dc4000 }, - { _MMIO(0x9888), 0x0cbd4000 }, - { _MMIO(0x9888), 0x0cbf0981 }, - { _MMIO(0x9888), 0x0ebf0a0f }, - { _MMIO(0x9888), 0x06d84000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0cdb4000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0080 }, - { _MMIO(0x9888), 0x0cb84000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800c00 }, - { _MMIO(0x9888), 0x47800c63 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a5 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800045 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_4[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_4[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_4[] = { - { _MMIO(0x9888), 0x121a0340 }, - { _MMIO(0x9888), 0x103f0017 }, - { _MMIO(0x9888), 0x123f0020 }, - { _MMIO(0x9888), 0x129a0340 }, - { _MMIO(0x9888), 0x10bf0017 }, - { _MMIO(0x9888), 0x12bf0020 }, - { _MMIO(0x9888), 0x041a3400 }, - { _MMIO(0x9888), 0x101a0000 }, - { _MMIO(0x9888), 0x043b8000 }, - { _MMIO(0x9888), 0x0a3e0010 }, - { _MMIO(0x9888), 0x003f0200 }, - { _MMIO(0x9888), 0x023f0113 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x02592000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a1c8000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0a1e8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f001a }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x069a0034 }, - { _MMIO(0x9888), 0x109a0000 }, - { _MMIO(0x9888), 0x06bb4000 }, - { _MMIO(0x9888), 0x0abe0040 }, - { _MMIO(0x9888), 0x0cbf0984 }, - { _MMIO(0x9888), 0x0ebf0a02 }, - { _MMIO(0x9888), 0x02d94000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0c9c0400 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x0c9e0400 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0040 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x47800842 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801084 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800044 }, -}; - -static int -get_l3_4_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_4; - lens[n] = ARRAY_SIZE(mux_config_l3_4); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00006000 }, - { _MMIO(0x2774), 0x0000f3ff }, - { _MMIO(0x2778), 0x00001800 }, - { _MMIO(0x277c), 0x0000fcff }, - { _MMIO(0x2780), 0x00000600 }, - { _MMIO(0x2784), 0x0000ff3f }, - { _MMIO(0x2788), 0x00000180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000060 }, - { _MMIO(0x2794), 0x0000fff3 }, - { _MMIO(0x2798), 0x00000018 }, - { _MMIO(0x279c), 0x0000fffc }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x143b000e }, - { _MMIO(0x9888), 0x043c55c0 }, - { _MMIO(0x9888), 0x0a1e0280 }, - { _MMIO(0x9888), 0x0c1e0408 }, - { _MMIO(0x9888), 0x10390000 }, - { _MMIO(0x9888), 0x12397a1f }, - { _MMIO(0x9888), 0x14bb000e }, - { _MMIO(0x9888), 0x04bc5000 }, - { _MMIO(0x9888), 0x0a9e0296 }, - { _MMIO(0x9888), 0x0c9e0008 }, - { _MMIO(0x9888), 0x10b90000 }, - { _MMIO(0x9888), 0x12b97a1f }, - { _MMIO(0x9888), 0x063b0042 }, - { _MMIO(0x9888), 0x103b0000 }, - { _MMIO(0x9888), 0x083c0000 }, - { _MMIO(0x9888), 0x0a3e0040 }, - { _MMIO(0x9888), 0x043f8000 }, - { _MMIO(0x9888), 0x02594000 }, - { _MMIO(0x9888), 0x045a8000 }, - { _MMIO(0x9888), 0x0c1c0400 }, - { _MMIO(0x9888), 0x041d8000 }, - { _MMIO(0x9888), 0x081e02c0 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1f0260 }, - { _MMIO(0x9888), 0x101f0014 }, - { _MMIO(0x9888), 0x003905e0 }, - { _MMIO(0x9888), 0x06390bc0 }, - { _MMIO(0x9888), 0x02390018 }, - { _MMIO(0x9888), 0x04394000 }, - { _MMIO(0x9888), 0x04bb0042 }, - { _MMIO(0x9888), 0x10bb0000 }, - { _MMIO(0x9888), 0x02bc05c0 }, - { _MMIO(0x9888), 0x08bc0000 }, - { _MMIO(0x9888), 0x0abe0004 }, - { _MMIO(0x9888), 0x02bf8000 }, - { _MMIO(0x9888), 0x02d91000 }, - { _MMIO(0x9888), 0x02da8000 }, - { _MMIO(0x9888), 0x089c8000 }, - { _MMIO(0x9888), 0x029d8000 }, - { _MMIO(0x9888), 0x089e8000 }, - { _MMIO(0x9888), 0x0e9e0000 }, - { _MMIO(0x9888), 0x0e9fa806 }, - { _MMIO(0x9888), 0x109f0142 }, - { _MMIO(0x9888), 0x08b90617 }, - { _MMIO(0x9888), 0x0ab90be0 }, - { _MMIO(0x9888), 0x02b94000 }, - { _MMIO(0x9888), 0x0d88f000 }, - { _MMIO(0x9888), 0x0f88000c }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x1b8a2800 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b52a0 }, - { _MMIO(0x9888), 0x258b6a95 }, - { _MMIO(0x9888), 0x278b0029 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1500 }, - { _MMIO(0x9888), 0x1b8c0014 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d8000 }, - { _MMIO(0x9888), 0x058d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4d800444 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f804000 }, - { _MMIO(0x9888), 0x43801080 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800084 }, - { _MMIO(0x9888), 0x53800044 }, - { _MMIO(0x9888), 0x47801080 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x41800840 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_1[] = { - { _MMIO(0x9888), 0x18921400 }, - { _MMIO(0x9888), 0x149500ab }, - { _MMIO(0x9888), 0x18b21400 }, - { _MMIO(0x9888), 0x14b500ab }, - { _MMIO(0x9888), 0x18d21400 }, - { _MMIO(0x9888), 0x14d500ab }, - { _MMIO(0x9888), 0x0cdc8000 }, - { _MMIO(0x9888), 0x0edc4000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x1abd00a0 }, - { _MMIO(0x9888), 0x0abd8000 }, - { _MMIO(0x9888), 0x0cd88000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x04d88000 }, - { _MMIO(0x9888), 0x1adb0050 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x06db8000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x109f02a0 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x18b82500 }, - { _MMIO(0x9888), 0x02b88000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb98000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x1aba0200 }, - { _MMIO(0x9888), 0x02ba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04908000 }, - { _MMIO(0x9888), 0x04918000 }, - { _MMIO(0x9888), 0x04927300 }, - { _MMIO(0x9888), 0x10920000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a934000 }, - { _MMIO(0x9888), 0x0a946000 }, - { _MMIO(0x9888), 0x0c959000 }, - { _MMIO(0x9888), 0x0e950098 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b04000 }, - { _MMIO(0x9888), 0x04b14000 }, - { _MMIO(0x9888), 0x04b20073 }, - { _MMIO(0x9888), 0x10b20000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x06b38000 }, - { _MMIO(0x9888), 0x08b34000 }, - { _MMIO(0x9888), 0x04b4c000 }, - { _MMIO(0x9888), 0x02b59890 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d04000 }, - { _MMIO(0x9888), 0x06d14000 }, - { _MMIO(0x9888), 0x06d20073 }, - { _MMIO(0x9888), 0x10d20000 }, - { _MMIO(0x9888), 0x18d30020 }, - { _MMIO(0x9888), 0x02d38000 }, - { _MMIO(0x9888), 0x0cd34000 }, - { _MMIO(0x9888), 0x0ad48000 }, - { _MMIO(0x9888), 0x04d42000 }, - { _MMIO(0x9888), 0x0ed59000 }, - { _MMIO(0x9888), 0x00d59800 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0f88000e }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x258b000a }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8d8000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_1; - lens[n] = ARRAY_SIZE(mux_config_sampler_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_2[] = { - { _MMIO(0x9888), 0x18121400 }, - { _MMIO(0x9888), 0x141500ab }, - { _MMIO(0x9888), 0x18321400 }, - { _MMIO(0x9888), 0x143500ab }, - { _MMIO(0x9888), 0x18521400 }, - { _MMIO(0x9888), 0x145500ab }, - { _MMIO(0x9888), 0x0c5c8000 }, - { _MMIO(0x9888), 0x0e5c4000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x1a3d00a0 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0c588000 }, - { _MMIO(0x9888), 0x0e584000 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x1a5b0050 }, - { _MMIO(0x9888), 0x045b8000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x101f02a0 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x18382500 }, - { _MMIO(0x9888), 0x02388000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c398000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x1a3a0200 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x04108000 }, - { _MMIO(0x9888), 0x04118000 }, - { _MMIO(0x9888), 0x04127300 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x1813000a }, - { _MMIO(0x9888), 0x0a134000 }, - { _MMIO(0x9888), 0x0a146000 }, - { _MMIO(0x9888), 0x0c159000 }, - { _MMIO(0x9888), 0x0e150098 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04304000 }, - { _MMIO(0x9888), 0x04314000 }, - { _MMIO(0x9888), 0x04320073 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x04338000 }, - { _MMIO(0x9888), 0x06338000 }, - { _MMIO(0x9888), 0x08334000 }, - { _MMIO(0x9888), 0x0434c000 }, - { _MMIO(0x9888), 0x02359890 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x06504000 }, - { _MMIO(0x9888), 0x06514000 }, - { _MMIO(0x9888), 0x06520073 }, - { _MMIO(0x9888), 0x10520000 }, - { _MMIO(0x9888), 0x18530020 }, - { _MMIO(0x9888), 0x02538000 }, - { _MMIO(0x9888), 0x0c534000 }, - { _MMIO(0x9888), 0x0a548000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x0e559000 }, - { _MMIO(0x9888), 0x00559800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x1b8aa000 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_2; - lens[n] = ARRAY_SIZE(mux_config_sampler_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000ffbf }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fff7 }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fff9 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x16154d60 }, - { _MMIO(0x9888), 0x16352e60 }, - { _MMIO(0x9888), 0x16554d60 }, - { _MMIO(0x9888), 0x16950000 }, - { _MMIO(0x9888), 0x16b50000 }, - { _MMIO(0x9888), 0x16d50000 }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x025b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04388000 }, - { _MMIO(0x9888), 0x06388000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x043a8000 }, - { _MMIO(0x9888), 0x063a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x0a138000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x0415cfc7 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x02338000 }, - { _MMIO(0x9888), 0x0c338000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x0035c700 }, - { _MMIO(0x9888), 0x063500cf }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04538000 }, - { _MMIO(0x9888), 0x06538000 }, - { _MMIO(0x9888), 0x0454c000 }, - { _MMIO(0x9888), 0x0255cfc7 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dc4000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x1abd00a8 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db0800 }, - { _MMIO(0x9888), 0x1adb0254 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b8156a }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x18baa000 }, - { _MMIO(0x9888), 0x1aba0002 }, - { _MMIO(0x9888), 0x16934000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a947000 }, - { _MMIO(0x9888), 0x0c95c5c1 }, - { _MMIO(0x9888), 0x0e9500c3 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x0eb38000 }, - { _MMIO(0x9888), 0x16b30040 }, - { _MMIO(0x9888), 0x18b30020 }, - { _MMIO(0x9888), 0x06b48000 }, - { _MMIO(0x9888), 0x08b41000 }, - { _MMIO(0x9888), 0x0ab48000 }, - { _MMIO(0x9888), 0x06b5c500 }, - { _MMIO(0x9888), 0x08b500c3 }, - { _MMIO(0x9888), 0x0eb5c100 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x16d31500 }, - { _MMIO(0x9888), 0x08d4e000 }, - { _MMIO(0x9888), 0x08d5c100 }, - { _MMIO(0x9888), 0x0ad5c3c5 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baaa5 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800c42 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800063 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800800 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a4 }, - { _MMIO(0x9888), 0x41801042 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000000 }, - { _MMIO(0x2784), 0x0000ff9f }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffe7 }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fffb }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000fffd }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x16150000 }, - { _MMIO(0x9888), 0x16350000 }, - { _MMIO(0x9888), 0x16550000 }, - { _MMIO(0x9888), 0x16952e60 }, - { _MMIO(0x9888), 0x16b54d60 }, - { _MMIO(0x9888), 0x16d52e60 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5c4000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183da000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x08588000 }, - { _MMIO(0x9888), 0x0a584000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5800 }, - { _MMIO(0x9888), 0x1a5b000a }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18382a55 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x1a3a02a0 }, - { _MMIO(0x9888), 0x0e138000 }, - { _MMIO(0x9888), 0x16130500 }, - { _MMIO(0x9888), 0x06148000 }, - { _MMIO(0x9888), 0x08146000 }, - { _MMIO(0x9888), 0x0615c100 }, - { _MMIO(0x9888), 0x0815c500 }, - { _MMIO(0x9888), 0x0a1500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x16335040 }, - { _MMIO(0x9888), 0x08349000 }, - { _MMIO(0x9888), 0x0a341000 }, - { _MMIO(0x9888), 0x083500c1 }, - { _MMIO(0x9888), 0x0a35c500 }, - { _MMIO(0x9888), 0x0c3500c3 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x1853002a }, - { _MMIO(0x9888), 0x0a54e000 }, - { _MMIO(0x9888), 0x0c55c500 }, - { _MMIO(0x9888), 0x0e55c1c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dc4000 }, - { _MMIO(0x9888), 0x04bd8000 }, - { _MMIO(0x9888), 0x06bd8000 }, - { _MMIO(0x9888), 0x02d8c000 }, - { _MMIO(0x9888), 0x02db8000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0aba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04938000 }, - { _MMIO(0x9888), 0x06938000 }, - { _MMIO(0x9888), 0x0494c000 }, - { _MMIO(0x9888), 0x0295cfc7 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x02b38000 }, - { _MMIO(0x9888), 0x08b38000 }, - { _MMIO(0x9888), 0x04b42000 }, - { _MMIO(0x9888), 0x06b41000 }, - { _MMIO(0x9888), 0x00b5c700 }, - { _MMIO(0x9888), 0x04b500cf }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x0ad38000 }, - { _MMIO(0x9888), 0x0cd38000 }, - { _MMIO(0x9888), 0x06d46000 }, - { _MMIO(0x9888), 0x04d5c700 }, - { _MMIO(0x9888), 0x06d500cf }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x258b555a }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800882 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801082 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800002 }, - { _MMIO(0x9888), 0x41800c62 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x161503e0 }, - { _MMIO(0x9888), 0x163503e0 }, - { _MMIO(0x9888), 0x165503e0 }, - { _MMIO(0x9888), 0x169503e0 }, - { _MMIO(0x9888), 0x16b503e0 }, - { _MMIO(0x9888), 0x16d503e0 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x04584000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b8000 }, - { _MMIO(0x9888), 0x0e1f00a8 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x06141000 }, - { _MMIO(0x9888), 0x041500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x0a338000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x0435c300 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x0c538000 }, - { _MMIO(0x9888), 0x06544000 }, - { _MMIO(0x9888), 0x065500c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dc4000 }, - { _MMIO(0x9888), 0x02bd8000 }, - { _MMIO(0x9888), 0x00d88000 }, - { _MMIO(0x9888), 0x02db4000 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f0002 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x06ba8000 }, - { _MMIO(0x9888), 0x02938000 }, - { _MMIO(0x9888), 0x04942000 }, - { _MMIO(0x9888), 0x0095c300 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x04b44000 }, - { _MMIO(0x9888), 0x02b500c3 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d38000 }, - { _MMIO(0x9888), 0x04d48000 }, - { _MMIO(0x9888), 0x02d5c300 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b3500 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c40 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41801482 }, - { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x14100812 }, - { _MMIO(0x9888), 0x14125800 }, - { _MMIO(0x9888), 0x161200c0 }, - { _MMIO(0x9888), 0x14300812 }, - { _MMIO(0x9888), 0x14325800 }, - { _MMIO(0x9888), 0x163200c0 }, - { _MMIO(0x9888), 0x005c4000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x003d8000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183d2800 }, - { _MMIO(0x9888), 0x00584000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b9400 }, - { _MMIO(0x9888), 0x1a5b002a }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f002a }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18380155 }, - { _MMIO(0x9888), 0x00392000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x00100047 }, - { _MMIO(0x9888), 0x06101a80 }, - { _MMIO(0x9888), 0x10100000 }, - { _MMIO(0x9888), 0x0810c000 }, - { _MMIO(0x9888), 0x0811c000 }, - { _MMIO(0x9888), 0x08126151 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x00134000 }, - { _MMIO(0x9888), 0x0e134000 }, - { _MMIO(0x9888), 0x161300a0 }, - { _MMIO(0x9888), 0x0a301ac7 }, - { _MMIO(0x9888), 0x10300000 }, - { _MMIO(0x9888), 0x0c30c000 }, - { _MMIO(0x9888), 0x0c31c000 }, - { _MMIO(0x9888), 0x0c326151 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x16332a00 }, - { _MMIO(0x9888), 0x18330001 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a2aa0 }, - { _MMIO(0x9888), 0x238b0020 }, - { _MMIO(0x9888), 0x258b5550 }, - { _MMIO(0x9888), 0x278b0001 }, - { _MMIO(0x9888), 0x1f850080 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x23850002 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830015 }, - { _MMIO(0x9888), 0x01844000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800002 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800884 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800002 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -4049,1328 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x31800000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_DATA_PORT_READS_COALESCING: - dev_priv->perf.oa.n_mux_configs = - get_data_port_reads_coalescing_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_READS_COALESCING\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_data_port_reads_coalescing; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_data_port_reads_coalescing); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_data_port_reads_coalescing; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_data_port_reads_coalescing); - - return 0; - case METRIC_SET_ID_DATA_PORT_WRITES_COALESCING: - dev_priv->perf.oa.n_mux_configs = - get_data_port_writes_coalescing_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_WRITES_COALESCING\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_data_port_writes_coalescing; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_data_port_writes_coalescing); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_data_port_writes_coalescing; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_data_port_writes_coalescing); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_L3_4: - dev_priv->perf.oa.n_mux_configs = - get_l3_4_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_4; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_4); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_4; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_4); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER_1: - dev_priv->perf.oa.n_mux_configs = - get_sampler_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_1); - - return 0; - case METRIC_SET_ID_SAMPLER_2: - dev_priv->perf.oa.n_mux_configs = - get_sampler_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_2); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "35fbc9b2-a891-40a6-a38d-022bb7057552", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "233d0544-fff7-4281-8291-e02f222aff72", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "e99ccaca-821c-4df9-97a7-96bdb7204e43", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "27a364dc-8225-4ecb-b607-d6f1925598d9", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_data_port_reads_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_READS_COALESCING); -} - -static struct device_attribute dev_attr_data_port_reads_coalescing_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_data_port_reads_coalescing_id, - .store = NULL, -}; - -static struct attribute *attrs_data_port_reads_coalescing[] = { - &dev_attr_data_port_reads_coalescing_id.attr, - NULL, -}; - -static struct attribute_group group_data_port_reads_coalescing = { - .name = "857fc630-2f09-4804-85f1-084adfadd5ab", - .attrs = attrs_data_port_reads_coalescing, -}; - -static ssize_t -show_data_port_writes_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_WRITES_COALESCING); -} - -static struct device_attribute dev_attr_data_port_writes_coalescing_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_data_port_writes_coalescing_id, - .store = NULL, -}; - -static struct attribute *attrs_data_port_writes_coalescing[] = { - &dev_attr_data_port_writes_coalescing_id.attr, - NULL, -}; - -static struct attribute_group group_data_port_writes_coalescing = { - .name = "343ebc99-4a55-414c-8c17-d8e259cf5e20", - .attrs = attrs_data_port_writes_coalescing, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "446ae59b-ff2e-41c9-b49e-0184a54bf00a", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "84a7956f-1ea4-4d0d-837f-e39a0376e38c", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); -} - -static struct device_attribute dev_attr_l3_4_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_4_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_4[] = { - &dev_attr_l3_4_id.attr, - NULL, -}; - -static struct attribute_group group_l3_4 = { - .name = "92b493d9-df18-4bed-be06-5cac6f2a6f5f", - .attrs = attrs_l3_4, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "14345c35-cc46-40d0-bb04-6ed1fbb43679", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); -} - -static struct device_attribute dev_attr_sampler_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_1_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_1[] = { - &dev_attr_sampler_1_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_1 = { - .name = "f0c6ba37-d3d3-4211-91b5-226730312a54", - .attrs = attrs_sampler_1, -}; - -static ssize_t -show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); -} - -static struct device_attribute dev_attr_sampler_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_2_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_2[] = { - &dev_attr_sampler_2_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_2 = { - .name = "30bf3702-48cf-4bca-b412-7cf50bb2f564", - .attrs = attrs_sampler_2, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "238bec85-df05-44f3-b905-d166712f2451", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "24bf02cd-8693-4583-981c-c4165b33da01", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "e1743ca0-7fc8-410b-a066-de7bbb9280b7", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "d6de6f55-e526-4f79-a6a6-d7315c09044e", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); - if (ret) - goto error_data_port_reads_coalescing; - } - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); - if (ret) - goto error_data_port_writes_coalescing; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (ret) - goto error_l3_4; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (ret) - goto error_sampler_1; - } - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (ret) - goto error_sampler_2; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); -error_sampler_2: - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); -error_sampler_1: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); -error_l3_4: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); -error_data_port_writes_coalescing: - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); -error_data_port_reads_coalescing: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "d6de6f55-e526-4f79-a6a6-d7315c09044e", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.h b/drivers/gpu/drm/i915/i915_oa_bdw.h index 6363ff9f64c0..b812d16162ac 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.h +++ b/drivers/gpu/drm/i915/i915_oa_bdw.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_BDW_H__ #define __I915_OA_BDW_H__ -extern int i915_oa_n_builtin_metric_sets_bdw; - -extern int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c b/drivers/gpu/drm/i915/i915_oa_bxt.c index 93864d8f32dd..d52074429def 100644 --- a/drivers/gpu/drm/i915/i915_oa_bxt.c +++ b/drivers/gpu/drm/i915/i915_oa_bxt.c @@ -31,1702 +31,6 @@ #include "i915_drv.h" #include "i915_oa_bxt.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_bxt = 15; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_0_sku_gte_0x03[] = { - { _MMIO(0x9888), 0x166c00f0 }, - { _MMIO(0x9888), 0x12120280 }, - { _MMIO(0x9888), 0x12320280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x419000a0 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2e0800 }, - { _MMIO(0x9888), 0x0e2e5900 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x1c4f0010 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a0fcc00 }, - { _MMIO(0x9888), 0x1c0f0002 }, - { _MMIO(0x9888), 0x1c2c0040 }, - { _MMIO(0x9888), 0x00101000 }, - { _MMIO(0x9888), 0x04101000 }, - { _MMIO(0x9888), 0x00114000 }, - { _MMIO(0x9888), 0x08114000 }, - { _MMIO(0x9888), 0x00120020 }, - { _MMIO(0x9888), 0x08120021 }, - { _MMIO(0x9888), 0x00141000 }, - { _MMIO(0x9888), 0x08141000 }, - { _MMIO(0x9888), 0x02308000 }, - { _MMIO(0x9888), 0x04302000 }, - { _MMIO(0x9888), 0x06318000 }, - { _MMIO(0x9888), 0x08318000 }, - { _MMIO(0x9888), 0x06320800 }, - { _MMIO(0x9888), 0x08320840 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x08344000 }, - { _MMIO(0x9888), 0x0d931831 }, - { _MMIO(0x9888), 0x0f939f3f }, - { _MMIO(0x9888), 0x01939e80 }, - { _MMIO(0x9888), 0x039303bc }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1993002a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900187 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901110 }, - { _MMIO(0x9888), 0x43900423 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900c02 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900020 }, - { _MMIO(0x9888), 0x59901111 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900821 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (dev_priv->drm.pdev->revision >= 0x03) { - regs[n] = mux_config_render_basic_0_sku_gte_0x03; - lens[n] = ARRAY_SIZE(mux_config_render_basic_0_sku_gte_0x03); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d4000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x0c2e1400 }, - { _MMIO(0x9888), 0x0e2e5100 }, - { _MMIO(0x9888), 0x102e0114 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004f6b42 }, - { _MMIO(0x9888), 0x064f6200 }, - { _MMIO(0x9888), 0x084f4100 }, - { _MMIO(0x9888), 0x0a4f0061 }, - { _MMIO(0x9888), 0x0c4f6c4c }, - { _MMIO(0x9888), 0x0e4f4b00 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0f8800 }, - { _MMIO(0x9888), 0x1c0f08a2 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c1451 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c0010 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x19938a28 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x19900177 }, - { _MMIO(0x9888), 0x1b900178 }, - { _MMIO(0x9888), 0x1d900125 }, - { _MMIO(0x9888), 0x1f900123 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c2e001f }, - { _MMIO(0x9888), 0x0a2f0000 }, - { _MMIO(0x9888), 0x10186800 }, - { _MMIO(0x9888), 0x11810019 }, - { _MMIO(0x9888), 0x15810013 }, - { _MMIO(0x9888), 0x13820020 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x17840000 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x21860000 }, - { _MMIO(0x9888), 0x178703e0 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x022e5400 }, - { _MMIO(0x9888), 0x002e0000 }, - { _MMIO(0x9888), 0x0e2e0080 }, - { _MMIO(0x9888), 0x082f0040 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x06174000 }, - { _MMIO(0x9888), 0x06180012 }, - { _MMIO(0x9888), 0x00180000 }, - { _MMIO(0x9888), 0x0d804000 }, - { _MMIO(0x9888), 0x0f804000 }, - { _MMIO(0x9888), 0x05804000 }, - { _MMIO(0x9888), 0x09810200 }, - { _MMIO(0x9888), 0x0b810030 }, - { _MMIO(0x9888), 0x03810003 }, - { _MMIO(0x9888), 0x21819140 }, - { _MMIO(0x9888), 0x23819050 }, - { _MMIO(0x9888), 0x25810018 }, - { _MMIO(0x9888), 0x0b820980 }, - { _MMIO(0x9888), 0x03820d80 }, - { _MMIO(0x9888), 0x11820000 }, - { _MMIO(0x9888), 0x0182c000 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x09824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0d830004 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x0f831000 }, - { _MMIO(0x9888), 0x01848072 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x09844000 }, - { _MMIO(0x9888), 0x0f848000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x09860092 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x01869100 }, - { _MMIO(0x9888), 0x0f870065 }, - { _MMIO(0x9888), 0x01870000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b952000 }, - { _MMIO(0x9888), 0x1d955055 }, - { _MMIO(0x9888), 0x1f951455 }, - { _MMIO(0x9888), 0x0992a000 }, - { _MMIO(0x9888), 0x0f928000 }, - { _MMIO(0x9888), 0x1192a800 }, - { _MMIO(0x9888), 0x1392028a }, - { _MMIO(0x9888), 0x0b92a000 }, - { _MMIO(0x9888), 0x0d922000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c01 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900863 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900c22 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x41900003 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900170 }, - { _MMIO(0x9888), 0x21900171 }, - { _MMIO(0x9888), 0x23900172 }, - { _MMIO(0x9888), 0x25900173 }, - { _MMIO(0x9888), 0x27900174 }, - { _MMIO(0x9888), 0x29900175 }, - { _MMIO(0x9888), 0x2b900176 }, - { _MMIO(0x9888), 0x2d900177 }, - { _MMIO(0x9888), 0x2f90017f }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900000 }, - { _MMIO(0x9888), 0x41900080 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900180 }, - { _MMIO(0x9888), 0x21900181 }, - { _MMIO(0x9888), 0x23900182 }, - { _MMIO(0x9888), 0x25900183 }, - { _MMIO(0x9888), 0x27900184 }, - { _MMIO(0x9888), 0x29900185 }, - { _MMIO(0x9888), 0x2b900186 }, - { _MMIO(0x9888), 0x2d900187 }, - { _MMIO(0x9888), 0x2f900170 }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x141c0160 }, - { _MMIO(0x9888), 0x161c0015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d5000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x0c2e5400 }, - { _MMIO(0x9888), 0x0e2e5515 }, - { _MMIO(0x9888), 0x102e0155 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x0e4cc000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0a4ea000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x0e4f4b41 }, - { _MMIO(0x9888), 0x004f4200 }, - { _MMIO(0x9888), 0x024f404c }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0a1bc000 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x001c0031 }, - { _MMIO(0x9888), 0x061c1900 }, - { _MMIO(0x9888), 0x081c1a33 }, - { _MMIO(0x9888), 0x0a1c1b35 }, - { _MMIO(0x9888), 0x0c1c3337 }, - { _MMIO(0x9888), 0x041c31c7 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0fa8aa }, - { _MMIO(0x9888), 0x1c0f0aaa }, - { _MMIO(0x9888), 0x182c8000 }, - { _MMIO(0x9888), 0x1c2c6aaa }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c2950 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993aaaa }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900400 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900001 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c03b0 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x0c2e0400 }, - { _MMIO(0x9888), 0x0e2e1500 }, - { _MMIO(0x9888), 0x102e0140 }, - { _MMIO(0x9888), 0x044c4000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004e2000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x1a4f4001 }, - { _MMIO(0x9888), 0x1c4f5005 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x180f1000 }, - { _MMIO(0x9888), 0x1a0fa800 }, - { _MMIO(0x9888), 0x1c0f0a00 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c4015 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x03931980 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993a00a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900178 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900400 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x022d4000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x064c8000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x024f6100 }, - { _MMIO(0x9888), 0x044f416b }, - { _MMIO(0x9888), 0x064f004b }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1a0f02a8 }, - { _MMIO(0x9888), 0x1a2c5500 }, - { _MMIO(0x9888), 0x0f808000 }, - { _MMIO(0x9888), 0x25810020 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1f951000 }, - { _MMIO(0x9888), 0x13920200 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4d900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1_0_sku_gte_0x03[] = { - { _MMIO(0x9888), 0x12643400 }, - { _MMIO(0x9888), 0x12653400 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x0a640024 }, - { _MMIO(0x9888), 0x10640000 }, - { _MMIO(0x9888), 0x04640000 }, - { _MMIO(0x9888), 0x0c650024 }, - { _MMIO(0x9888), 0x10650000 }, - { _MMIO(0x9888), 0x06650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static const struct i915_oa_reg mux_config_l3_1_0_sku_lt_0x03[] = { - { _MMIO(0x9888), 0x14640340 }, - { _MMIO(0x9888), 0x14650340 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x04642400 }, - { _MMIO(0x9888), 0x22640000 }, - { _MMIO(0x9888), 0x1a640000 }, - { _MMIO(0x9888), 0x06650024 }, - { _MMIO(0x9888), 0x22650000 }, - { _MMIO(0x9888), 0x1c650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (dev_priv->drm.pdev->revision >= 0x03) { - regs[n] = mux_config_l3_1_0_sku_gte_0x03; - lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_gte_0x03); - n++; - } - if (dev_priv->drm.pdev->revision < 0x03) { - regs[n] = mux_config_l3_1_0_sku_lt_0x03; - lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_lt_0x03); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102d7800 }, - { _MMIO(0x9888), 0x122d79e0 }, - { _MMIO(0x9888), 0x0c2f0004 }, - { _MMIO(0x9888), 0x100e3800 }, - { _MMIO(0x9888), 0x180f0005 }, - { _MMIO(0x9888), 0x002d0940 }, - { _MMIO(0x9888), 0x022d802f }, - { _MMIO(0x9888), 0x042d4013 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0050 }, - { _MMIO(0x9888), 0x022f0010 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x040e0480 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x060f0027 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x1a0f0040 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x439014a0 }, - { _MMIO(0x9888), 0x459000a4 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x121300a0 }, - { _MMIO(0x9888), 0x141600ab }, - { _MMIO(0x9888), 0x123300a0 }, - { _MMIO(0x9888), 0x143600ab }, - { _MMIO(0x9888), 0x125300a0 }, - { _MMIO(0x9888), 0x145600ab }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e01a0 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0065 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0800 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f023f }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2cc030 }, - { _MMIO(0x9888), 0x04132180 }, - { _MMIO(0x9888), 0x02130000 }, - { _MMIO(0x9888), 0x0c148000 }, - { _MMIO(0x9888), 0x0e142000 }, - { _MMIO(0x9888), 0x04148000 }, - { _MMIO(0x9888), 0x1e150140 }, - { _MMIO(0x9888), 0x1c150040 }, - { _MMIO(0x9888), 0x0c163000 }, - { _MMIO(0x9888), 0x0e160068 }, - { _MMIO(0x9888), 0x10160000 }, - { _MMIO(0x9888), 0x18160000 }, - { _MMIO(0x9888), 0x0a164000 }, - { _MMIO(0x9888), 0x04330043 }, - { _MMIO(0x9888), 0x02330000 }, - { _MMIO(0x9888), 0x0234a000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x1c350015 }, - { _MMIO(0x9888), 0x02363460 }, - { _MMIO(0x9888), 0x10360000 }, - { _MMIO(0x9888), 0x04360000 }, - { _MMIO(0x9888), 0x06360000 }, - { _MMIO(0x9888), 0x08364000 }, - { _MMIO(0x9888), 0x06530043 }, - { _MMIO(0x9888), 0x02530000 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x06542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550100 }, - { _MMIO(0x9888), 0x0e563000 }, - { _MMIO(0x9888), 0x00563400 }, - { _MMIO(0x9888), 0x10560000 }, - { _MMIO(0x9888), 0x18560000 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x0c564000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9014a0 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900820 }, - { _MMIO(0x9888), 0x45901022 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x141a0000 }, - { _MMIO(0x9888), 0x143a0000 }, - { _MMIO(0x9888), 0x145a0000 }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0150 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e006a }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0bc0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f0302 }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2c00f0 }, - { _MMIO(0x9888), 0x021a3080 }, - { _MMIO(0x9888), 0x041a31e5 }, - { _MMIO(0x9888), 0x02148000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150054 }, - { _MMIO(0x9888), 0x06168000 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x0c3a3280 }, - { _MMIO(0x9888), 0x0e3a0063 }, - { _MMIO(0x9888), 0x063a0061 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x0c348000 }, - { _MMIO(0x9888), 0x0e342000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1e350140 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x18360028 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x0e5a3080 }, - { _MMIO(0x9888), 0x005a3280 }, - { _MMIO(0x9888), 0x025a0063 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x02542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550001 }, - { _MMIO(0x9888), 0x18560080 }, - { _MMIO(0x9888), 0x02568000 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x45901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x141a026b }, - { _MMIO(0x9888), 0x143a0173 }, - { _MMIO(0x9888), 0x145a026b }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0069 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x180f6000 }, - { _MMIO(0x9888), 0x1a0f030a }, - { _MMIO(0x9888), 0x1a2c03c0 }, - { _MMIO(0x9888), 0x041a37e7 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150050 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x003a3380 }, - { _MMIO(0x9888), 0x063a006f }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x00348000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1a352000 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x02368000 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x025a37e7 }, - { _MMIO(0x9888), 0x0254a000 }, - { _MMIO(0x9888), 0x1c550005 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x06568000 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900020 }, - { _MMIO(0x9888), 0x45901080 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x141a001f }, - { _MMIO(0x9888), 0x143a001f }, - { _MMIO(0x9888), 0x145a001f }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0094 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x1a0f00e0 }, - { _MMIO(0x9888), 0x1a2c0c00 }, - { _MMIO(0x9888), 0x061a0063 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x06142000 }, - { _MMIO(0x9888), 0x1c150100 }, - { _MMIO(0x9888), 0x0c168000 }, - { _MMIO(0x9888), 0x043a3180 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x04348000 }, - { _MMIO(0x9888), 0x1c350040 }, - { _MMIO(0x9888), 0x0a368000 }, - { _MMIO(0x9888), 0x045a0063 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x1c550010 }, - { _MMIO(0x9888), 0x08568000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900004 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1769,922 +73,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "012d72cf-82a9-4d25-8ddf-74076fd30797", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "ce416533-e49e-4211-80af-ec513590a914", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "398e2452-18d7-42d0-b241-e4d0a9148ada", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "00ad5a41-7eab-4f7a-9103-49d411c67219", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "8364e2a8-af63-40af-b0d5-42969a255654", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "d260f03f-b34d-4b49-a44e-436819117332", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a", - .attrs = attrs_compute_extra, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "5ee72f5c-092f-421e-8b70-225f7c3e9612", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "5ee72f5c-092f-421e-8b70-225f7c3e9612", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.h b/drivers/gpu/drm/i915/i915_oa_bxt.h index 6cf7ba746e7e..690b963a2383 100644 --- a/drivers/gpu/drm/i915/i915_oa_bxt.h +++ b/drivers/gpu/drm/i915/i915_oa_bxt.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_BXT_H__ #define __I915_OA_BXT_H__ -extern int i915_oa_n_builtin_metric_sets_bxt; - -extern int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c index aa6bece7e75f..b4832a0fefaa 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.c +++ b/drivers/gpu/drm/i915/i915_oa_chv.c @@ -31,1943 +31,6 @@ #include "i915_drv.h" #include "i915_oa_chv.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_L3_4, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER_1, - METRIC_SET_ID_SAMPLER_2, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_chv = 14; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x285a0006 }, - { _MMIO(0x9888), 0x2c110014 }, - { _MMIO(0x9888), 0x2e110000 }, - { _MMIO(0x9888), 0x2c310014 }, - { _MMIO(0x9888), 0x2e310000 }, - { _MMIO(0x9888), 0x2b8303df }, - { _MMIO(0x9888), 0x3580024f }, - { _MMIO(0x9888), 0x00580888 }, - { _MMIO(0x9888), 0x1e5a0015 }, - { _MMIO(0x9888), 0x205a0014 }, - { _MMIO(0x9888), 0x045a0000 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x02180500 }, - { _MMIO(0x9888), 0x00190555 }, - { _MMIO(0x9888), 0x021d0500 }, - { _MMIO(0x9888), 0x021f0a00 }, - { _MMIO(0x9888), 0x00380444 }, - { _MMIO(0x9888), 0x02390500 }, - { _MMIO(0x9888), 0x003a0666 }, - { _MMIO(0x9888), 0x00100111 }, - { _MMIO(0x9888), 0x06110030 }, - { _MMIO(0x9888), 0x0a110031 }, - { _MMIO(0x9888), 0x0e110046 }, - { _MMIO(0x9888), 0x04110000 }, - { _MMIO(0x9888), 0x00110000 }, - { _MMIO(0x9888), 0x00130111 }, - { _MMIO(0x9888), 0x00300444 }, - { _MMIO(0x9888), 0x08310030 }, - { _MMIO(0x9888), 0x0c310031 }, - { _MMIO(0x9888), 0x10310046 }, - { _MMIO(0x9888), 0x04310000 }, - { _MMIO(0x9888), 0x00310000 }, - { _MMIO(0x9888), 0x00330444 }, - { _MMIO(0x9888), 0x038a0a00 }, - { _MMIO(0x9888), 0x018b0fff }, - { _MMIO(0x9888), 0x038b0a00 }, - { _MMIO(0x9888), 0x01855000 }, - { _MMIO(0x9888), 0x03850055 }, - { _MMIO(0x9888), 0x13830021 }, - { _MMIO(0x9888), 0x15830020 }, - { _MMIO(0x9888), 0x1783002f }, - { _MMIO(0x9888), 0x1983002e }, - { _MMIO(0x9888), 0x1b83002d }, - { _MMIO(0x9888), 0x1d83002c }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x01840555 }, - { _MMIO(0x9888), 0x03840500 }, - { _MMIO(0x9888), 0x23800074 }, - { _MMIO(0x9888), 0x2580007d }, - { _MMIO(0x9888), 0x05800000 }, - { _MMIO(0x9888), 0x01805000 }, - { _MMIO(0x9888), 0x03800055 }, - { _MMIO(0x9888), 0x01865000 }, - { _MMIO(0x9888), 0x03860055 }, - { _MMIO(0x9888), 0x01875000 }, - { _MMIO(0x9888), 0x03870055 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x4380000a }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x4780000a }, - { _MMIO(0x9888), 0x49800000 }, - { _MMIO(0x9888), 0x4b800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x55800000 }, - { _MMIO(0x9888), 0x57800000 }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x2e5800e0 }, - { _MMIO(0x9888), 0x2e3800e0 }, - { _MMIO(0x9888), 0x3580024f }, - { _MMIO(0x9888), 0x3d800140 }, - { _MMIO(0x9888), 0x08580042 }, - { _MMIO(0x9888), 0x0c580040 }, - { _MMIO(0x9888), 0x1058004c }, - { _MMIO(0x9888), 0x1458004b }, - { _MMIO(0x9888), 0x04580000 }, - { _MMIO(0x9888), 0x00580000 }, - { _MMIO(0x9888), 0x00195555 }, - { _MMIO(0x9888), 0x06380042 }, - { _MMIO(0x9888), 0x0a380040 }, - { _MMIO(0x9888), 0x0e38004c }, - { _MMIO(0x9888), 0x1238004b }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x00384444 }, - { _MMIO(0x9888), 0x003a5555 }, - { _MMIO(0x9888), 0x018bffff }, - { _MMIO(0x9888), 0x01845555 }, - { _MMIO(0x9888), 0x17800074 }, - { _MMIO(0x9888), 0x1980007d }, - { _MMIO(0x9888), 0x1b80007c }, - { _MMIO(0x9888), 0x1d8000b6 }, - { _MMIO(0x9888), 0x1f8000b7 }, - { _MMIO(0x9888), 0x05800000 }, - { _MMIO(0x9888), 0x03800000 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x438000aa }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x4980012a }, - { _MMIO(0x9888), 0x4b80012a }, - { _MMIO(0x9888), 0x4d80012a }, - { _MMIO(0x9888), 0x4f80012a }, - { _MMIO(0x9888), 0x518001ce }, - { _MMIO(0x9888), 0x538001ce }, - { _MMIO(0x9888), 0x5580000e }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x261e0000 }, - { _MMIO(0x9888), 0x281f000f }, - { _MMIO(0x9888), 0x2817001a }, - { _MMIO(0x9888), 0x2791001f }, - { _MMIO(0x9888), 0x27880019 }, - { _MMIO(0x9888), 0x2d890000 }, - { _MMIO(0x9888), 0x278a0007 }, - { _MMIO(0x9888), 0x298d001f }, - { _MMIO(0x9888), 0x278e0020 }, - { _MMIO(0x9888), 0x2b8f0012 }, - { _MMIO(0x9888), 0x29900000 }, - { _MMIO(0x9888), 0x00184000 }, - { _MMIO(0x9888), 0x02181000 }, - { _MMIO(0x9888), 0x02194000 }, - { _MMIO(0x9888), 0x141e0002 }, - { _MMIO(0x9888), 0x041e0000 }, - { _MMIO(0x9888), 0x001e0000 }, - { _MMIO(0x9888), 0x221f0015 }, - { _MMIO(0x9888), 0x041f0000 }, - { _MMIO(0x9888), 0x001f4000 }, - { _MMIO(0x9888), 0x021f0000 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0213c000 }, - { _MMIO(0x9888), 0x02164000 }, - { _MMIO(0x9888), 0x24170012 }, - { _MMIO(0x9888), 0x04170000 }, - { _MMIO(0x9888), 0x07910005 }, - { _MMIO(0x9888), 0x05910000 }, - { _MMIO(0x9888), 0x01911500 }, - { _MMIO(0x9888), 0x03910501 }, - { _MMIO(0x9888), 0x0d880002 }, - { _MMIO(0x9888), 0x1d880003 }, - { _MMIO(0x9888), 0x05880000 }, - { _MMIO(0x9888), 0x0b890032 }, - { _MMIO(0x9888), 0x1b890031 }, - { _MMIO(0x9888), 0x05890000 }, - { _MMIO(0x9888), 0x01890040 }, - { _MMIO(0x9888), 0x03890040 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x198a0004 }, - { _MMIO(0x9888), 0x058a0000 }, - { _MMIO(0x9888), 0x018a8050 }, - { _MMIO(0x9888), 0x038a2050 }, - { _MMIO(0x9888), 0x018b95a9 }, - { _MMIO(0x9888), 0x038be5a9 }, - { _MMIO(0x9888), 0x018c1500 }, - { _MMIO(0x9888), 0x038c0501 }, - { _MMIO(0x9888), 0x178d0015 }, - { _MMIO(0x9888), 0x058d0000 }, - { _MMIO(0x9888), 0x138e0004 }, - { _MMIO(0x9888), 0x218e000c }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x018e0500 }, - { _MMIO(0x9888), 0x038e0101 }, - { _MMIO(0x9888), 0x0f8f0027 }, - { _MMIO(0x9888), 0x058f0000 }, - { _MMIO(0x9888), 0x018f0000 }, - { _MMIO(0x9888), 0x038f0001 }, - { _MMIO(0x9888), 0x11900013 }, - { _MMIO(0x9888), 0x1f900017 }, - { _MMIO(0x9888), 0x05900000 }, - { _MMIO(0x9888), 0x01900100 }, - { _MMIO(0x9888), 0x03900001 }, - { _MMIO(0x9888), 0x01845555 }, - { _MMIO(0x9888), 0x03845555 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x438000aa }, - { _MMIO(0x9888), 0x458000aa }, - { _MMIO(0x9888), 0x478000aa }, - { _MMIO(0x9888), 0x4980018c }, - { _MMIO(0x9888), 0x4b80014b }, - { _MMIO(0x9888), 0x4d800128 }, - { _MMIO(0x9888), 0x4f80012a }, - { _MMIO(0x9888), 0x51800187 }, - { _MMIO(0x9888), 0x5380014b }, - { _MMIO(0x9888), 0x55800149 }, - { _MMIO(0x9888), 0x5780010a }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fff7 }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x105c0232 }, - { _MMIO(0x9888), 0x10580232 }, - { _MMIO(0x9888), 0x10380232 }, - { _MMIO(0x9888), 0x10dc0232 }, - { _MMIO(0x9888), 0x10d80232 }, - { _MMIO(0x9888), 0x10b80232 }, - { _MMIO(0x9888), 0x118e4400 }, - { _MMIO(0x9888), 0x025c6080 }, - { _MMIO(0x9888), 0x045c004b }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x00582080 }, - { _MMIO(0x9888), 0x0258004b }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x04386080 }, - { _MMIO(0x9888), 0x0638404b }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a380000 }, - { _MMIO(0x9888), 0x0c380000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0cdc25c1 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0ad825c1 }, - { _MMIO(0x9888), 0x18db4000 }, - { _MMIO(0x9888), 0x1adb0001 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb825c1 }, - { _MMIO(0x9888), 0x18b80154 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baa05 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x098dc000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x098e05c0 }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x198f0020 }, - { _MMIO(0x9888), 0x2185aa0a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x19835000 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x19808000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x51800040 }, - { _MMIO(0x9888), 0x43800400 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800c62 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801042 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x418014a4 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x10bf03da }, - { _MMIO(0x9888), 0x14bf0001 }, - { _MMIO(0x9888), 0x12980340 }, - { _MMIO(0x9888), 0x12990340 }, - { _MMIO(0x9888), 0x0cbf1187 }, - { _MMIO(0x9888), 0x0ebf1205 }, - { _MMIO(0x9888), 0x00bf0500 }, - { _MMIO(0x9888), 0x02bf042b }, - { _MMIO(0x9888), 0x04bf002c }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02dac000 }, - { _MMIO(0x9888), 0x04da4000 }, - { _MMIO(0x9888), 0x04983400 }, - { _MMIO(0x9888), 0x10980000 }, - { _MMIO(0x9888), 0x06990034 }, - { _MMIO(0x9888), 0x10990000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029dc000 }, - { _MMIO(0x9888), 0x049d4000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00ba }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b95000 }, - { _MMIO(0x9888), 0x04b91000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0cba4000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x258b800a }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x103f03da }, - { _MMIO(0x9888), 0x143f0001 }, - { _MMIO(0x9888), 0x12180340 }, - { _MMIO(0x9888), 0x12190340 }, - { _MMIO(0x9888), 0x0c3f1187 }, - { _MMIO(0x9888), 0x0e3f1205 }, - { _MMIO(0x9888), 0x003f0500 }, - { _MMIO(0x9888), 0x023f042b }, - { _MMIO(0x9888), 0x043f002c }, - { _MMIO(0x9888), 0x0c5ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x04183400 }, - { _MMIO(0x9888), 0x10180000 }, - { _MMIO(0x9888), 0x06190034 }, - { _MMIO(0x9888), 0x10190000 }, - { _MMIO(0x9888), 0x0c1dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x101f02a8 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00ba }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a4000 }, - { _MMIO(0x9888), 0x1b8aa800 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258b4005 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x121b0340 }, - { _MMIO(0x9888), 0x103f0274 }, - { _MMIO(0x9888), 0x123f0000 }, - { _MMIO(0x9888), 0x129b0340 }, - { _MMIO(0x9888), 0x10bf0274 }, - { _MMIO(0x9888), 0x12bf0000 }, - { _MMIO(0x9888), 0x041b3400 }, - { _MMIO(0x9888), 0x101b0000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x0a3d4000 }, - { _MMIO(0x9888), 0x003f0080 }, - { _MMIO(0x9888), 0x023f0793 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f002a }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04399000 }, - { _MMIO(0x9888), 0x069b0034 }, - { _MMIO(0x9888), 0x109b0000 }, - { _MMIO(0x9888), 0x06dc4000 }, - { _MMIO(0x9888), 0x0cbd4000 }, - { _MMIO(0x9888), 0x0cbf0981 }, - { _MMIO(0x9888), 0x0ebf0a0f }, - { _MMIO(0x9888), 0x06d84000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0cdb4000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0080 }, - { _MMIO(0x9888), 0x0cb84000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800c00 }, - { _MMIO(0x9888), 0x47800c63 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a5 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800045 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_4[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_4[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_4[] = { - { _MMIO(0x9888), 0x121a0340 }, - { _MMIO(0x9888), 0x103f0017 }, - { _MMIO(0x9888), 0x123f0020 }, - { _MMIO(0x9888), 0x129a0340 }, - { _MMIO(0x9888), 0x10bf0017 }, - { _MMIO(0x9888), 0x12bf0020 }, - { _MMIO(0x9888), 0x041a3400 }, - { _MMIO(0x9888), 0x101a0000 }, - { _MMIO(0x9888), 0x043b8000 }, - { _MMIO(0x9888), 0x0a3e0010 }, - { _MMIO(0x9888), 0x003f0200 }, - { _MMIO(0x9888), 0x023f0113 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x02592000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a1c8000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0a1e8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f001a }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x069a0034 }, - { _MMIO(0x9888), 0x109a0000 }, - { _MMIO(0x9888), 0x06bb4000 }, - { _MMIO(0x9888), 0x0abe0040 }, - { _MMIO(0x9888), 0x0cbf0984 }, - { _MMIO(0x9888), 0x0ebf0a02 }, - { _MMIO(0x9888), 0x02d94000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0c9c0400 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x0c9e0400 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0040 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x47800842 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801084 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800044 }, -}; - -static int -get_l3_4_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_4; - lens[n] = ARRAY_SIZE(mux_config_l3_4); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00006000 }, - { _MMIO(0x2774), 0x0000f3ff }, - { _MMIO(0x2778), 0x00001800 }, - { _MMIO(0x277c), 0x0000fcff }, - { _MMIO(0x2780), 0x00000600 }, - { _MMIO(0x2784), 0x0000ff3f }, - { _MMIO(0x2788), 0x00000180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000060 }, - { _MMIO(0x2794), 0x0000fff3 }, - { _MMIO(0x2798), 0x00000018 }, - { _MMIO(0x279c), 0x0000fffc }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x143b000e }, - { _MMIO(0x9888), 0x043c55c0 }, - { _MMIO(0x9888), 0x0a1e0280 }, - { _MMIO(0x9888), 0x0c1e0408 }, - { _MMIO(0x9888), 0x10390000 }, - { _MMIO(0x9888), 0x12397a1f }, - { _MMIO(0x9888), 0x14bb000e }, - { _MMIO(0x9888), 0x04bc5000 }, - { _MMIO(0x9888), 0x0a9e0296 }, - { _MMIO(0x9888), 0x0c9e0008 }, - { _MMIO(0x9888), 0x10b90000 }, - { _MMIO(0x9888), 0x12b97a1f }, - { _MMIO(0x9888), 0x063b0042 }, - { _MMIO(0x9888), 0x103b0000 }, - { _MMIO(0x9888), 0x083c0000 }, - { _MMIO(0x9888), 0x0a3e0040 }, - { _MMIO(0x9888), 0x043f8000 }, - { _MMIO(0x9888), 0x02594000 }, - { _MMIO(0x9888), 0x045a8000 }, - { _MMIO(0x9888), 0x0c1c0400 }, - { _MMIO(0x9888), 0x041d8000 }, - { _MMIO(0x9888), 0x081e02c0 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1f0260 }, - { _MMIO(0x9888), 0x101f0014 }, - { _MMIO(0x9888), 0x003905e0 }, - { _MMIO(0x9888), 0x06390bc0 }, - { _MMIO(0x9888), 0x02390018 }, - { _MMIO(0x9888), 0x04394000 }, - { _MMIO(0x9888), 0x04bb0042 }, - { _MMIO(0x9888), 0x10bb0000 }, - { _MMIO(0x9888), 0x02bc05c0 }, - { _MMIO(0x9888), 0x08bc0000 }, - { _MMIO(0x9888), 0x0abe0004 }, - { _MMIO(0x9888), 0x02bf8000 }, - { _MMIO(0x9888), 0x02d91000 }, - { _MMIO(0x9888), 0x02da8000 }, - { _MMIO(0x9888), 0x089c8000 }, - { _MMIO(0x9888), 0x029d8000 }, - { _MMIO(0x9888), 0x089e8000 }, - { _MMIO(0x9888), 0x0e9e0000 }, - { _MMIO(0x9888), 0x0e9fa806 }, - { _MMIO(0x9888), 0x109f0142 }, - { _MMIO(0x9888), 0x08b90617 }, - { _MMIO(0x9888), 0x0ab90be0 }, - { _MMIO(0x9888), 0x02b94000 }, - { _MMIO(0x9888), 0x0d88f000 }, - { _MMIO(0x9888), 0x0f88000c }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x1b8a2800 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b52a0 }, - { _MMIO(0x9888), 0x258b6a95 }, - { _MMIO(0x9888), 0x278b0029 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1500 }, - { _MMIO(0x9888), 0x1b8c0014 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d8000 }, - { _MMIO(0x9888), 0x058d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4d800444 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f804000 }, - { _MMIO(0x9888), 0x43801080 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800084 }, - { _MMIO(0x9888), 0x53800044 }, - { _MMIO(0x9888), 0x47801080 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x41800840 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_1[] = { - { _MMIO(0x9888), 0x18921400 }, - { _MMIO(0x9888), 0x149500ab }, - { _MMIO(0x9888), 0x18b21400 }, - { _MMIO(0x9888), 0x14b500ab }, - { _MMIO(0x9888), 0x18d21400 }, - { _MMIO(0x9888), 0x14d500ab }, - { _MMIO(0x9888), 0x0cdc8000 }, - { _MMIO(0x9888), 0x0edc4000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x1abd00a0 }, - { _MMIO(0x9888), 0x0abd8000 }, - { _MMIO(0x9888), 0x0cd88000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x04d88000 }, - { _MMIO(0x9888), 0x1adb0050 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x06db8000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x109f02a0 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x18b82500 }, - { _MMIO(0x9888), 0x02b88000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb98000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x1aba0200 }, - { _MMIO(0x9888), 0x02ba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04908000 }, - { _MMIO(0x9888), 0x04918000 }, - { _MMIO(0x9888), 0x04927300 }, - { _MMIO(0x9888), 0x10920000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a934000 }, - { _MMIO(0x9888), 0x0a946000 }, - { _MMIO(0x9888), 0x0c959000 }, - { _MMIO(0x9888), 0x0e950098 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b04000 }, - { _MMIO(0x9888), 0x04b14000 }, - { _MMIO(0x9888), 0x04b20073 }, - { _MMIO(0x9888), 0x10b20000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x06b38000 }, - { _MMIO(0x9888), 0x08b34000 }, - { _MMIO(0x9888), 0x04b4c000 }, - { _MMIO(0x9888), 0x02b59890 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d04000 }, - { _MMIO(0x9888), 0x06d14000 }, - { _MMIO(0x9888), 0x06d20073 }, - { _MMIO(0x9888), 0x10d20000 }, - { _MMIO(0x9888), 0x18d30020 }, - { _MMIO(0x9888), 0x02d38000 }, - { _MMIO(0x9888), 0x0cd34000 }, - { _MMIO(0x9888), 0x0ad48000 }, - { _MMIO(0x9888), 0x04d42000 }, - { _MMIO(0x9888), 0x0ed59000 }, - { _MMIO(0x9888), 0x00d59800 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0f88000e }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x258b000a }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8d8000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_1; - lens[n] = ARRAY_SIZE(mux_config_sampler_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_2[] = { - { _MMIO(0x9888), 0x18121400 }, - { _MMIO(0x9888), 0x141500ab }, - { _MMIO(0x9888), 0x18321400 }, - { _MMIO(0x9888), 0x143500ab }, - { _MMIO(0x9888), 0x18521400 }, - { _MMIO(0x9888), 0x145500ab }, - { _MMIO(0x9888), 0x0c5c8000 }, - { _MMIO(0x9888), 0x0e5c4000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x1a3d00a0 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0c588000 }, - { _MMIO(0x9888), 0x0e584000 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x1a5b0050 }, - { _MMIO(0x9888), 0x045b8000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x101f02a0 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x18382500 }, - { _MMIO(0x9888), 0x02388000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c398000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x1a3a0200 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x04108000 }, - { _MMIO(0x9888), 0x04118000 }, - { _MMIO(0x9888), 0x04127300 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x1813000a }, - { _MMIO(0x9888), 0x0a134000 }, - { _MMIO(0x9888), 0x0a146000 }, - { _MMIO(0x9888), 0x0c159000 }, - { _MMIO(0x9888), 0x0e150098 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04304000 }, - { _MMIO(0x9888), 0x04314000 }, - { _MMIO(0x9888), 0x04320073 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x04338000 }, - { _MMIO(0x9888), 0x06338000 }, - { _MMIO(0x9888), 0x08334000 }, - { _MMIO(0x9888), 0x0434c000 }, - { _MMIO(0x9888), 0x02359890 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x06504000 }, - { _MMIO(0x9888), 0x06514000 }, - { _MMIO(0x9888), 0x06520073 }, - { _MMIO(0x9888), 0x10520000 }, - { _MMIO(0x9888), 0x18530020 }, - { _MMIO(0x9888), 0x02538000 }, - { _MMIO(0x9888), 0x0c534000 }, - { _MMIO(0x9888), 0x0a548000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x0e559000 }, - { _MMIO(0x9888), 0x00559800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x1b8aa000 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_2; - lens[n] = ARRAY_SIZE(mux_config_sampler_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000ffbf }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fff7 }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fff9 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x16154d60 }, - { _MMIO(0x9888), 0x16352e60 }, - { _MMIO(0x9888), 0x16554d60 }, - { _MMIO(0x9888), 0x16950000 }, - { _MMIO(0x9888), 0x16b50000 }, - { _MMIO(0x9888), 0x16d50000 }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x025b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04388000 }, - { _MMIO(0x9888), 0x06388000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x043a8000 }, - { _MMIO(0x9888), 0x063a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x0a138000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x0415cfc7 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x02338000 }, - { _MMIO(0x9888), 0x0c338000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x0035c700 }, - { _MMIO(0x9888), 0x063500cf }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04538000 }, - { _MMIO(0x9888), 0x06538000 }, - { _MMIO(0x9888), 0x0454c000 }, - { _MMIO(0x9888), 0x0255cfc7 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dc4000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x1abd00a8 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db0800 }, - { _MMIO(0x9888), 0x1adb0254 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b8156a }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x18baa000 }, - { _MMIO(0x9888), 0x1aba0002 }, - { _MMIO(0x9888), 0x16934000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a947000 }, - { _MMIO(0x9888), 0x0c95c5c1 }, - { _MMIO(0x9888), 0x0e9500c3 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x0eb38000 }, - { _MMIO(0x9888), 0x16b30040 }, - { _MMIO(0x9888), 0x18b30020 }, - { _MMIO(0x9888), 0x06b48000 }, - { _MMIO(0x9888), 0x08b41000 }, - { _MMIO(0x9888), 0x0ab48000 }, - { _MMIO(0x9888), 0x06b5c500 }, - { _MMIO(0x9888), 0x08b500c3 }, - { _MMIO(0x9888), 0x0eb5c100 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x16d31500 }, - { _MMIO(0x9888), 0x08d4e000 }, - { _MMIO(0x9888), 0x08d5c100 }, - { _MMIO(0x9888), 0x0ad5c3c5 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baaa5 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800c42 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800063 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800800 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a4 }, - { _MMIO(0x9888), 0x41801042 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000000 }, - { _MMIO(0x2784), 0x0000ff9f }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffe7 }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fffb }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000fffd }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x16150000 }, - { _MMIO(0x9888), 0x16350000 }, - { _MMIO(0x9888), 0x16550000 }, - { _MMIO(0x9888), 0x16952e60 }, - { _MMIO(0x9888), 0x16b54d60 }, - { _MMIO(0x9888), 0x16d52e60 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5c4000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183da000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x08588000 }, - { _MMIO(0x9888), 0x0a584000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5800 }, - { _MMIO(0x9888), 0x1a5b000a }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18382a55 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x1a3a02a0 }, - { _MMIO(0x9888), 0x0e138000 }, - { _MMIO(0x9888), 0x16130500 }, - { _MMIO(0x9888), 0x06148000 }, - { _MMIO(0x9888), 0x08146000 }, - { _MMIO(0x9888), 0x0615c100 }, - { _MMIO(0x9888), 0x0815c500 }, - { _MMIO(0x9888), 0x0a1500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x16335040 }, - { _MMIO(0x9888), 0x08349000 }, - { _MMIO(0x9888), 0x0a341000 }, - { _MMIO(0x9888), 0x083500c1 }, - { _MMIO(0x9888), 0x0a35c500 }, - { _MMIO(0x9888), 0x0c3500c3 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x1853002a }, - { _MMIO(0x9888), 0x0a54e000 }, - { _MMIO(0x9888), 0x0c55c500 }, - { _MMIO(0x9888), 0x0e55c1c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dc4000 }, - { _MMIO(0x9888), 0x04bd8000 }, - { _MMIO(0x9888), 0x06bd8000 }, - { _MMIO(0x9888), 0x02d8c000 }, - { _MMIO(0x9888), 0x02db8000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0aba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04938000 }, - { _MMIO(0x9888), 0x06938000 }, - { _MMIO(0x9888), 0x0494c000 }, - { _MMIO(0x9888), 0x0295cfc7 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x02b38000 }, - { _MMIO(0x9888), 0x08b38000 }, - { _MMIO(0x9888), 0x04b42000 }, - { _MMIO(0x9888), 0x06b41000 }, - { _MMIO(0x9888), 0x00b5c700 }, - { _MMIO(0x9888), 0x04b500cf }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x0ad38000 }, - { _MMIO(0x9888), 0x0cd38000 }, - { _MMIO(0x9888), 0x06d46000 }, - { _MMIO(0x9888), 0x04d5c700 }, - { _MMIO(0x9888), 0x06d500cf }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x258b555a }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800882 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801082 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800002 }, - { _MMIO(0x9888), 0x41800c62 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -2010,864 +73,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x59800000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_L3_4: - dev_priv->perf.oa.n_mux_configs = - get_l3_4_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_4; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_4); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_4; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_4); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER_1: - dev_priv->perf.oa.n_mux_configs = - get_sampler_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_1); - - return 0; - case METRIC_SET_ID_SAMPLER_2: - dev_priv->perf.oa.n_mux_configs = - get_sampler_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_2); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "f522a89c-ecd1-4522-8331-3383c54af5f5", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "a9ccc03d-a943-4e6b-9cd6-13e063075927", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "78a87ff9-543a-49ce-95ea-26d86071ea93", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); -} - -static struct device_attribute dev_attr_l3_4_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_4_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_4[] = { - &dev_attr_l3_4_id.attr, - NULL, -}; - -static struct attribute_group group_l3_4 = { - .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4", - .attrs = attrs_l3_4, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); -} - -static struct device_attribute dev_attr_sampler_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_1_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_1[] = { - &dev_attr_sampler_1_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_1 = { - .name = "71148d78-baf5-474f-878a-e23158d0265d", - .attrs = attrs_sampler_1, -}; - -static ssize_t -show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); -} - -static struct device_attribute dev_attr_sampler_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_2_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_2[] = { - &dev_attr_sampler_2_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_2 = { - .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84", - .attrs = attrs_sampler_2, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d", - .attrs = attrs_tdl_2, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "4a534b07-cba3-414d-8d60-874830e883aa", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (ret) - goto error_l3_4; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (ret) - goto error_sampler_1; - } - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (ret) - goto error_sampler_2; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); -error_sampler_2: - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); -error_sampler_1: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); -error_l3_4: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "4a534b07-cba3-414d-8d60-874830e883aa", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "4a534b07-cba3-414d-8d60-874830e883aa"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_chv.h b/drivers/gpu/drm/i915/i915_oa_chv.h index 8b8bdc26d726..b9622496979e 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.h +++ b/drivers/gpu/drm/i915/i915_oa_chv.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_CHV_H__ #define __I915_OA_CHV_H__ -extern int i915_oa_n_builtin_metric_sets_chv; - -extern int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_glk.c b/drivers/gpu/drm/i915/i915_oa_glk.c index 2f356d51bff8..f0dbab5d19e0 100644 --- a/drivers/gpu/drm/i915/i915_oa_glk.c +++ b/drivers/gpu/drm/i915/i915_oa_glk.c @@ -31,1614 +31,6 @@ #include "i915_drv.h" #include "i915_oa_glk.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_glk = 15; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c00f0 }, - { _MMIO(0x9888), 0x12120280 }, - { _MMIO(0x9888), 0x12320280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x419000a0 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2e0800 }, - { _MMIO(0x9888), 0x0e2e5900 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x1c4f0010 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a0fcc00 }, - { _MMIO(0x9888), 0x1c0f0002 }, - { _MMIO(0x9888), 0x1c2c0040 }, - { _MMIO(0x9888), 0x00101000 }, - { _MMIO(0x9888), 0x04101000 }, - { _MMIO(0x9888), 0x00114000 }, - { _MMIO(0x9888), 0x08114000 }, - { _MMIO(0x9888), 0x00120020 }, - { _MMIO(0x9888), 0x08120021 }, - { _MMIO(0x9888), 0x00141000 }, - { _MMIO(0x9888), 0x08141000 }, - { _MMIO(0x9888), 0x02308000 }, - { _MMIO(0x9888), 0x04302000 }, - { _MMIO(0x9888), 0x06318000 }, - { _MMIO(0x9888), 0x08318000 }, - { _MMIO(0x9888), 0x06320800 }, - { _MMIO(0x9888), 0x08320840 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x08344000 }, - { _MMIO(0x9888), 0x0d931831 }, - { _MMIO(0x9888), 0x0f939f3f }, - { _MMIO(0x9888), 0x01939e80 }, - { _MMIO(0x9888), 0x039303bc }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1993002a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900187 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901110 }, - { _MMIO(0x9888), 0x43900423 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900c02 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900020 }, - { _MMIO(0x9888), 0x59901111 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900821 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d4000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x0c2e1400 }, - { _MMIO(0x9888), 0x0e2e5100 }, - { _MMIO(0x9888), 0x102e0114 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004f6b42 }, - { _MMIO(0x9888), 0x064f6200 }, - { _MMIO(0x9888), 0x084f4100 }, - { _MMIO(0x9888), 0x0a4f0061 }, - { _MMIO(0x9888), 0x0c4f6c4c }, - { _MMIO(0x9888), 0x0e4f4b00 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0f8800 }, - { _MMIO(0x9888), 0x1c0f08a2 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c1451 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c0010 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x19938a28 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x19900177 }, - { _MMIO(0x9888), 0x1b900178 }, - { _MMIO(0x9888), 0x1d900125 }, - { _MMIO(0x9888), 0x1f900123 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c2e001f }, - { _MMIO(0x9888), 0x0a2f0000 }, - { _MMIO(0x9888), 0x10186800 }, - { _MMIO(0x9888), 0x11810019 }, - { _MMIO(0x9888), 0x15810013 }, - { _MMIO(0x9888), 0x13820020 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x17840000 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x21860000 }, - { _MMIO(0x9888), 0x178703e0 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x022e5400 }, - { _MMIO(0x9888), 0x002e0000 }, - { _MMIO(0x9888), 0x0e2e0080 }, - { _MMIO(0x9888), 0x082f0040 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x06174000 }, - { _MMIO(0x9888), 0x06180012 }, - { _MMIO(0x9888), 0x00180000 }, - { _MMIO(0x9888), 0x0d804000 }, - { _MMIO(0x9888), 0x0f804000 }, - { _MMIO(0x9888), 0x05804000 }, - { _MMIO(0x9888), 0x09810200 }, - { _MMIO(0x9888), 0x0b810030 }, - { _MMIO(0x9888), 0x03810003 }, - { _MMIO(0x9888), 0x21819140 }, - { _MMIO(0x9888), 0x23819050 }, - { _MMIO(0x9888), 0x25810018 }, - { _MMIO(0x9888), 0x0b820980 }, - { _MMIO(0x9888), 0x03820d80 }, - { _MMIO(0x9888), 0x11820000 }, - { _MMIO(0x9888), 0x0182c000 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x09824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0d830004 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x0f831000 }, - { _MMIO(0x9888), 0x01848072 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x09844000 }, - { _MMIO(0x9888), 0x0f848000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x09860092 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x01869100 }, - { _MMIO(0x9888), 0x0f870065 }, - { _MMIO(0x9888), 0x01870000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b952000 }, - { _MMIO(0x9888), 0x1d955055 }, - { _MMIO(0x9888), 0x1f951455 }, - { _MMIO(0x9888), 0x0992a000 }, - { _MMIO(0x9888), 0x0f928000 }, - { _MMIO(0x9888), 0x1192a800 }, - { _MMIO(0x9888), 0x1392028a }, - { _MMIO(0x9888), 0x0b92a000 }, - { _MMIO(0x9888), 0x0d922000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c01 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900863 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900c22 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x41900003 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900170 }, - { _MMIO(0x9888), 0x21900171 }, - { _MMIO(0x9888), 0x23900172 }, - { _MMIO(0x9888), 0x25900173 }, - { _MMIO(0x9888), 0x27900174 }, - { _MMIO(0x9888), 0x29900175 }, - { _MMIO(0x9888), 0x2b900176 }, - { _MMIO(0x9888), 0x2d900177 }, - { _MMIO(0x9888), 0x2f90017f }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900000 }, - { _MMIO(0x9888), 0x41900080 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900180 }, - { _MMIO(0x9888), 0x21900181 }, - { _MMIO(0x9888), 0x23900182 }, - { _MMIO(0x9888), 0x25900183 }, - { _MMIO(0x9888), 0x27900184 }, - { _MMIO(0x9888), 0x29900185 }, - { _MMIO(0x9888), 0x2b900186 }, - { _MMIO(0x9888), 0x2d900187 }, - { _MMIO(0x9888), 0x2f900170 }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x141c0160 }, - { _MMIO(0x9888), 0x161c0015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d5000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x0c2e5400 }, - { _MMIO(0x9888), 0x0e2e5515 }, - { _MMIO(0x9888), 0x102e0155 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x0e4cc000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0a4ea000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x0e4f4b41 }, - { _MMIO(0x9888), 0x004f4200 }, - { _MMIO(0x9888), 0x024f404c }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0a1bc000 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x001c0031 }, - { _MMIO(0x9888), 0x061c1900 }, - { _MMIO(0x9888), 0x081c1a33 }, - { _MMIO(0x9888), 0x0a1c1b35 }, - { _MMIO(0x9888), 0x0c1c3337 }, - { _MMIO(0x9888), 0x041c31c7 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0fa8aa }, - { _MMIO(0x9888), 0x1c0f0aaa }, - { _MMIO(0x9888), 0x182c8000 }, - { _MMIO(0x9888), 0x1c2c6aaa }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c2950 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993aaaa }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900400 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900001 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c03b0 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x0c2e0400 }, - { _MMIO(0x9888), 0x0e2e1500 }, - { _MMIO(0x9888), 0x102e0140 }, - { _MMIO(0x9888), 0x044c4000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004e2000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x1a4f4001 }, - { _MMIO(0x9888), 0x1c4f5005 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x180f1000 }, - { _MMIO(0x9888), 0x1a0fa800 }, - { _MMIO(0x9888), 0x1c0f0a00 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c4015 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x03931980 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993a00a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900178 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900400 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x022d4000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x064c8000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x024f6100 }, - { _MMIO(0x9888), 0x044f416b }, - { _MMIO(0x9888), 0x064f004b }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1a0f02a8 }, - { _MMIO(0x9888), 0x1a2c5500 }, - { _MMIO(0x9888), 0x0f808000 }, - { _MMIO(0x9888), 0x25810020 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1f951000 }, - { _MMIO(0x9888), 0x13920200 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4d900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x12643400 }, - { _MMIO(0x9888), 0x12653400 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x0a640024 }, - { _MMIO(0x9888), 0x10640000 }, - { _MMIO(0x9888), 0x04640000 }, - { _MMIO(0x9888), 0x0c650024 }, - { _MMIO(0x9888), 0x10650000 }, - { _MMIO(0x9888), 0x06650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102d7800 }, - { _MMIO(0x9888), 0x122d79e0 }, - { _MMIO(0x9888), 0x0c2f0004 }, - { _MMIO(0x9888), 0x100e3800 }, - { _MMIO(0x9888), 0x180f0005 }, - { _MMIO(0x9888), 0x002d0940 }, - { _MMIO(0x9888), 0x022d802f }, - { _MMIO(0x9888), 0x042d4013 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0050 }, - { _MMIO(0x9888), 0x022f0010 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x040e0480 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x060f0027 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x1a0f0040 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x439014a0 }, - { _MMIO(0x9888), 0x459000a4 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x121300a0 }, - { _MMIO(0x9888), 0x141600ab }, - { _MMIO(0x9888), 0x123300a0 }, - { _MMIO(0x9888), 0x143600ab }, - { _MMIO(0x9888), 0x125300a0 }, - { _MMIO(0x9888), 0x145600ab }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e01a0 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0065 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0800 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f023f }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2cc030 }, - { _MMIO(0x9888), 0x04132180 }, - { _MMIO(0x9888), 0x02130000 }, - { _MMIO(0x9888), 0x0c148000 }, - { _MMIO(0x9888), 0x0e142000 }, - { _MMIO(0x9888), 0x04148000 }, - { _MMIO(0x9888), 0x1e150140 }, - { _MMIO(0x9888), 0x1c150040 }, - { _MMIO(0x9888), 0x0c163000 }, - { _MMIO(0x9888), 0x0e160068 }, - { _MMIO(0x9888), 0x10160000 }, - { _MMIO(0x9888), 0x18160000 }, - { _MMIO(0x9888), 0x0a164000 }, - { _MMIO(0x9888), 0x04330043 }, - { _MMIO(0x9888), 0x02330000 }, - { _MMIO(0x9888), 0x0234a000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x1c350015 }, - { _MMIO(0x9888), 0x02363460 }, - { _MMIO(0x9888), 0x10360000 }, - { _MMIO(0x9888), 0x04360000 }, - { _MMIO(0x9888), 0x06360000 }, - { _MMIO(0x9888), 0x08364000 }, - { _MMIO(0x9888), 0x06530043 }, - { _MMIO(0x9888), 0x02530000 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x06542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550100 }, - { _MMIO(0x9888), 0x0e563000 }, - { _MMIO(0x9888), 0x00563400 }, - { _MMIO(0x9888), 0x10560000 }, - { _MMIO(0x9888), 0x18560000 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x0c564000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9014a0 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900820 }, - { _MMIO(0x9888), 0x45901022 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x141a0000 }, - { _MMIO(0x9888), 0x143a0000 }, - { _MMIO(0x9888), 0x145a0000 }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0150 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e006a }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0bc0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f0302 }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2c00f0 }, - { _MMIO(0x9888), 0x021a3080 }, - { _MMIO(0x9888), 0x041a31e5 }, - { _MMIO(0x9888), 0x02148000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150054 }, - { _MMIO(0x9888), 0x06168000 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x0c3a3280 }, - { _MMIO(0x9888), 0x0e3a0063 }, - { _MMIO(0x9888), 0x063a0061 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x0c348000 }, - { _MMIO(0x9888), 0x0e342000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1e350140 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x18360028 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x0e5a3080 }, - { _MMIO(0x9888), 0x005a3280 }, - { _MMIO(0x9888), 0x025a0063 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x02542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550001 }, - { _MMIO(0x9888), 0x18560080 }, - { _MMIO(0x9888), 0x02568000 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x45901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x141a026b }, - { _MMIO(0x9888), 0x143a0173 }, - { _MMIO(0x9888), 0x145a026b }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0069 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x180f6000 }, - { _MMIO(0x9888), 0x1a0f030a }, - { _MMIO(0x9888), 0x1a2c03c0 }, - { _MMIO(0x9888), 0x041a37e7 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150050 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x003a3380 }, - { _MMIO(0x9888), 0x063a006f }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x00348000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1a352000 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x02368000 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x025a37e7 }, - { _MMIO(0x9888), 0x0254a000 }, - { _MMIO(0x9888), 0x1c550005 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x06568000 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900020 }, - { _MMIO(0x9888), 0x45901080 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x141a001f }, - { _MMIO(0x9888), 0x143a001f }, - { _MMIO(0x9888), 0x145a001f }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0094 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x1a0f00e0 }, - { _MMIO(0x9888), 0x1a2c0c00 }, - { _MMIO(0x9888), 0x061a0063 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x06142000 }, - { _MMIO(0x9888), 0x1c150100 }, - { _MMIO(0x9888), 0x0c168000 }, - { _MMIO(0x9888), 0x043a3180 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x04348000 }, - { _MMIO(0x9888), 0x1c350040 }, - { _MMIO(0x9888), 0x0a368000 }, - { _MMIO(0x9888), 0x045a0063 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x1c550010 }, - { _MMIO(0x9888), 0x08568000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900004 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1681,922 +73,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "814285f6-354d-41d2-ba49-e24e622714a0", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "07d397a6-b3e6-49f6-9433-a4f293d55978", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "1a356946-5428-450b-a2f0-89f8783a302d", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "bc9bcff2-459a-4cbc-986d-a84b077153f3", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "88ec931f-5b4a-453a-9db6-a61232b6143d", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "530d176d-2a18-4014-adf8-1500c6c60835", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "fdee5a5a-f23c-43d1-aa73-f6257c71671d", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "6617623e-ca73-4791-b2b7-ddedd0846a0c", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "f3b2ea63-e82e-4234-b418-44dd20dd34d0", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "14411d35-cbf6-4f5e-b68b-190faf9a1a83", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "15274c82-27d2-4819-876a-7cb1a2c59ba4", - .attrs = attrs_compute_extra, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "dd3fd789-e783-4204-8cd0-b671bbccb0cf", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_glk.h b/drivers/gpu/drm/i915/i915_oa_glk.h index 5511bb1cecf7..63bd113f4bc9 100644 --- a/drivers/gpu/drm/i915/i915_oa_glk.h +++ b/drivers/gpu/drm/i915/i915_oa_glk.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_GLK_H__ #define __I915_OA_GLK_H__ -extern int i915_oa_n_builtin_metric_sets_glk; - -extern int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c index 10f169f683b7..867ec16dd831 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.c +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c @@ -31,17 +31,6 @@ #include "i915_drv.h" #include "i915_oa_hsw.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_SAMPLER_BALANCE, -}; - -int i915_oa_n_builtin_metric_sets_hsw = 6; - static const struct i915_oa_reg b_counter_config_render_basic[] = { { _MMIO(0x2724), 0x00800000 }, { _MMIO(0x2720), 0x00000000 }, @@ -114,750 +103,35 @@ static const struct i915_oa_reg mux_config_render_basic[] = { { _MMIO(0x25428), 0x00042049 }, }; -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2718), 0xaaaaaaaa }, - { _MMIO(0x271c), 0xaaaaaaaa }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2728), 0xaaaaaaaa }, - { _MMIO(0x272c), 0xaaaaaaaa }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00000000 }, - { _MMIO(0x2748), 0x00000000 }, - { _MMIO(0x274c), 0x00000000 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2754), 0x00000000 }, - { _MMIO(0x2758), 0x00000000 }, - { _MMIO(0x275c), 0x00000000 }, - { _MMIO(0x236c), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x253a4), 0x00000000 }, - { _MMIO(0x2681c), 0x01f00800 }, - { _MMIO(0x26820), 0x00001000 }, - { _MMIO(0x2781c), 0x01f00800 }, - { _MMIO(0x26520), 0x00000007 }, - { _MMIO(0x265a0), 0x00000007 }, - { _MMIO(0x25380), 0x00000010 }, - { _MMIO(0x2538c), 0x00300000 }, - { _MMIO(0x25384), 0xaa8aaaaa }, - { _MMIO(0x25404), 0xffffffff }, - { _MMIO(0x26800), 0x00004202 }, - { _MMIO(0x26808), 0x00605817 }, - { _MMIO(0x2680c), 0x10001005 }, - { _MMIO(0x26804), 0x00000000 }, - { _MMIO(0x27800), 0x00000102 }, - { _MMIO(0x27808), 0x0c0701e0 }, - { _MMIO(0x2780c), 0x000200a0 }, - { _MMIO(0x27804), 0x00000000 }, - { _MMIO(0x26484), 0x44000000 }, - { _MMIO(0x26704), 0x44000000 }, - { _MMIO(0x26500), 0x00000006 }, - { _MMIO(0x26510), 0x00000001 }, - { _MMIO(0x26504), 0x88000000 }, - { _MMIO(0x26580), 0x00000006 }, - { _MMIO(0x26590), 0x00000020 }, - { _MMIO(0x26584), 0x00000000 }, - { _MMIO(0x26104), 0x55822222 }, - { _MMIO(0x26184), 0xaa866666 }, - { _MMIO(0x25420), 0x08320c83 }, - { _MMIO(0x25424), 0x06820c83 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000c03 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2770), 0x0007fe2a }, - { _MMIO(0x2774), 0x0000ff00 }, - { _MMIO(0x2778), 0x0007fe6a }, - { _MMIO(0x277c), 0x0000ff00 }, - { _MMIO(0x2780), 0x0007fe92 }, - { _MMIO(0x2784), 0x0000ff00 }, - { _MMIO(0x2788), 0x0007fea2 }, - { _MMIO(0x278c), 0x0000ff00 }, - { _MMIO(0x2790), 0x0007fe32 }, - { _MMIO(0x2794), 0x0000ff00 }, - { _MMIO(0x2798), 0x0007fe9a }, - { _MMIO(0x279c), 0x0000ff00 }, - { _MMIO(0x27a0), 0x0007ff23 }, - { _MMIO(0x27a4), 0x0000ff00 }, - { _MMIO(0x27a8), 0x0007fff3 }, - { _MMIO(0x27ac), 0x0000fffe }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x2681c), 0x3eb00800 }, - { _MMIO(0x26820), 0x00900000 }, - { _MMIO(0x25384), 0x02aaaaaa }, - { _MMIO(0x25404), 0x03ffffff }, - { _MMIO(0x26800), 0x00142284 }, - { _MMIO(0x26808), 0x0e629062 }, - { _MMIO(0x2680c), 0x3f6f55cb }, - { _MMIO(0x26810), 0x00000014 }, - { _MMIO(0x26804), 0x00000000 }, - { _MMIO(0x26104), 0x02aaaaaa }, - { _MMIO(0x26184), 0x02aaaaaa }, - { _MMIO(0x25420), 0x00000000 }, - { _MMIO(0x25424), 0x00000000 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x76543298 }, - { _MMIO(0x2748), 0x98989898 }, - { _MMIO(0x2744), 0x000000e4 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x98a98a98 }, - { _MMIO(0x2758), 0x88888888 }, - { _MMIO(0x2754), 0x000c5500 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fc00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fc00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fc00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fc00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fc00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fc00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fc00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fc00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x253a4), 0x34300000 }, - { _MMIO(0x25440), 0x2d800000 }, - { _MMIO(0x25444), 0x00000008 }, - { _MMIO(0x25128), 0x0e600000 }, - { _MMIO(0x25380), 0x00000450 }, - { _MMIO(0x25390), 0x00052c43 }, - { _MMIO(0x25384), 0x00000000 }, - { _MMIO(0x25400), 0x00006144 }, - { _MMIO(0x25408), 0x0a418820 }, - { _MMIO(0x2540c), 0x000820e6 }, - { _MMIO(0x25404), 0xff500000 }, - { _MMIO(0x25100), 0x000005d6 }, - { _MMIO(0x2510c), 0x0ef00000 }, - { _MMIO(0x25104), 0x00000000 }, - { _MMIO(0x25420), 0x02108421 }, - { _MMIO(0x25424), 0x00008421 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x76543298 }, - { _MMIO(0x2748), 0x98989898 }, - { _MMIO(0x2744), 0x000000e4 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0xbabababa }, - { _MMIO(0x2758), 0x88888888 }, - { _MMIO(0x2754), 0x000c5500 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fc00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fc00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fc00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fc00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fc00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fc00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fc00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fc00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x253a4), 0x34300000 }, - { _MMIO(0x25440), 0x01500000 }, - { _MMIO(0x25444), 0x00000120 }, - { _MMIO(0x25128), 0x0c200000 }, - { _MMIO(0x25380), 0x00000450 }, - { _MMIO(0x25390), 0x00052c43 }, - { _MMIO(0x25384), 0x00000000 }, - { _MMIO(0x25400), 0x00007184 }, - { _MMIO(0x25408), 0x0a418820 }, - { _MMIO(0x2540c), 0x000820e6 }, - { _MMIO(0x25404), 0xff500000 }, - { _MMIO(0x25100), 0x000005d6 }, - { _MMIO(0x2510c), 0x1e700000 }, - { _MMIO(0x25104), 0x00000000 }, - { _MMIO(0x25420), 0x02108421 }, - { _MMIO(0x25424), 0x00008421 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_balance[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_balance[] = { -}; - -static const struct i915_oa_reg mux_config_sampler_balance[] = { - { _MMIO(0x2eb9c), 0x01906400 }, - { _MMIO(0x2fb9c), 0x01906400 }, - { _MMIO(0x253a4), 0x00000000 }, - { _MMIO(0x26b9c), 0x01906400 }, - { _MMIO(0x27b9c), 0x01906400 }, - { _MMIO(0x27104), 0x00a00000 }, - { _MMIO(0x27184), 0x00a50000 }, - { _MMIO(0x2e804), 0x00500000 }, - { _MMIO(0x2e984), 0x00500000 }, - { _MMIO(0x2eb04), 0x00500000 }, - { _MMIO(0x2eb80), 0x00000084 }, - { _MMIO(0x2eb8c), 0x14200000 }, - { _MMIO(0x2eb84), 0x00000000 }, - { _MMIO(0x2f804), 0x00050000 }, - { _MMIO(0x2f984), 0x00050000 }, - { _MMIO(0x2fb04), 0x00050000 }, - { _MMIO(0x2fb80), 0x00000084 }, - { _MMIO(0x2fb8c), 0x00050800 }, - { _MMIO(0x2fb84), 0x00000000 }, - { _MMIO(0x25380), 0x00000010 }, - { _MMIO(0x2538c), 0x000000c0 }, - { _MMIO(0x25384), 0xaa550000 }, - { _MMIO(0x25404), 0xffffc000 }, - { _MMIO(0x26804), 0x50000000 }, - { _MMIO(0x26984), 0x50000000 }, - { _MMIO(0x26b04), 0x50000000 }, - { _MMIO(0x26b80), 0x00000084 }, - { _MMIO(0x26b90), 0x00050800 }, - { _MMIO(0x26b84), 0x00000000 }, - { _MMIO(0x27804), 0x05000000 }, - { _MMIO(0x27984), 0x05000000 }, - { _MMIO(0x27b04), 0x05000000 }, - { _MMIO(0x27b80), 0x00000084 }, - { _MMIO(0x27b90), 0x00000142 }, - { _MMIO(0x27b84), 0x00000000 }, - { _MMIO(0x26104), 0xa0000000 }, - { _MMIO(0x26184), 0xa5000000 }, - { _MMIO(0x25424), 0x00008620 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x0004a54a }, -}; - -static int -get_sampler_balance_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_balance; - lens[n] = ARRAY_SIZE(mux_config_sampler_balance); - n++; - - return n; -} - -int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_SAMPLER_BALANCE: - dev_priv->perf.oa.n_mux_configs = - get_sampler_balance_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_BALANCE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_balance; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_balance); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_balance; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_balance); - - return 0; - default: - return -ENODEV; - } -} - static ssize_t show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "403d8832-1a27-4aa6-a64e-f5389ce7b212", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "3865be28-6982-49fe-9494-e4d1b4795413", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "bb5ed49b-2497-4095-94f6-26ba294db88a", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "3358d639-9b5f-45ab-976d-9b08cbfc6240", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_sampler_balance_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_BALANCE); -} - -static struct device_attribute dev_attr_sampler_balance_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_balance_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_balance[] = { - &dev_attr_sampler_balance_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_balance = { - .name = "bc274488-b4b6-40c7-90da-b77d7ad16189", - .attrs = attrs_sampler_balance, -}; - -int -i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); - if (ret) - goto error_sampler_balance; - } - - return 0; - -error_sampler_balance: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "403d8832-1a27-4aa6-a64e-f5389ce7b212", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); + dev_priv->perf.oa.test_config.mux_regs = mux_config_render_basic; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_render_basic; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_render_basic; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_render_basic_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.h b/drivers/gpu/drm/i915/i915_oa_hsw.h index 6fe7e0690ef3..74d03439c157 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.h +++ b/drivers/gpu/drm/i915/i915_oa_hsw.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_HSW_H__ #define __I915_OA_HSW_H__ -extern int i915_oa_n_builtin_metric_sets_hsw; - -extern int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.c b/drivers/gpu/drm/i915/i915_oa_kblgt2.c index 87dbd0a0b076..2e8700c74227 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.c @@ -31,1828 +31,6 @@ #include "i915_drv.h" #include "i915_oa_kblgt2.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_kblgt2 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0080 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0d2000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162c2200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190001f }, - { _MMIO(0x9888), 0x51904400 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c21 }, - { _MMIO(0x9888), 0x47900061 }, - { _MMIO(0x9888), 0x57904440 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900004 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57900400 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53904444 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0e0f006c }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1190e000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c00 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x143a5800 }, - { _MMIO(0x9888), 0x163a00c0 }, - { _MMIO(0x9888), 0x12380240 }, - { _MMIO(0x9888), 0x14380002 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c1500 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f9500 }, - { _MMIO(0x9888), 0x100f002a }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x0a2dc000 }, - { _MMIO(0x9888), 0x0c2dc000 }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x06393000 }, - { _MMIO(0x9888), 0x0c3a28c1 }, - { _MMIO(0x9888), 0x003a0000 }, - { _MMIO(0x9888), 0x0a33f000 }, - { _MMIO(0x9888), 0x0c33f000 }, - { _MMIO(0x9888), 0x0a37a000 }, - { _MMIO(0x9888), 0x0c37a000 }, - { _MMIO(0x9888), 0x0a380977 }, - { _MMIO(0x9888), 0x08380000 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06383000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900800 }, - { _MMIO(0x9888), 0x47901000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900844 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1896,1096 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "f8d677e9-ff6f-4df1-9310-0334c6efacce", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "e17fc42a-e614-41b6-90c4-1074841a6c77", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "d7a17a3a-ca71-40d2-a919-ace80d50633f", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "57b59202-172b-477a-87de-33f85572c589", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "4af0400a-81c3-47db-a6b6-deddbd75680e", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "0e22f995-79ca-4f67-83ab-e9d9772488d8", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "d2bbe790-f058-42d9-81c6-cdedcf655bc2", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "2f8e32e4-5956-46e2-af31-c8ea95887332", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "ca046aad-b5fb-4101-adce-6473ee6e5b14", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "605f388f-24bb-455c-88e3-8d57ae0d7e9f", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "105db928-5542-466b-9128-e1f3c91426cb", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "03db94d2-b37f-4c58-a791-0d2067b013bb", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "baa3c7e4-52b6-4b85-801e-465a94b746dd", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "baa3c7e4-52b6-4b85-801e-465a94b746dd", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "baa3c7e4-52b6-4b85-801e-465a94b746dd"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.h b/drivers/gpu/drm/i915/i915_oa_kblgt2.h index 7e61bfc4f9f5..25b803546dc1 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt2.h +++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_KBLGT2_H__ #define __I915_OA_KBLGT2_H__ -extern int i915_oa_n_builtin_metric_sets_kblgt2; - -extern int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.c b/drivers/gpu/drm/i915/i915_oa_kblgt3.c index 6ed092566a32..ea524e024c72 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.c @@ -31,1877 +31,6 @@ #include "i915_drv.h" #include "i915_oa_kblgt3.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_kblgt3 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0380 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162ca200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0200 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x51902240 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900242 }, - { _MMIO(0x9888), 0x45900084 }, - { _MMIO(0x9888), 0x47901400 }, - { _MMIO(0x9888), 0x57902220 }, - { _MMIO(0x9888), 0x49900c60 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900002 }, - { _MMIO(0x9888), 0x43900c63 }, - { _MMIO(0x9888), 0x53902222 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57900400 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53904444 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900002 }, - { _MMIO(0x9888), 0x53900420 }, - { _MMIO(0x9888), 0x459000a1 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900040 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900004 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x479008a5 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1945,1096 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "0286c920-2f6d-493b-b22d-7a5280df43de", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "9823aaa1-b06f-40ce-884b-cd798c79f0c2", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "c7c735f3-ce58-45cf-aa04-30b183f1faff", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "96ec2219-040b-428a-856a-6bc03363a057", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "03372b64-4996-4d3b-aa18-790e75eeb9c2", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "2ce0911a-27fc-4887-96f0-11084fa807c3", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "546c4c1d-99b8-42fb-a107-5aaabb5314a8", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "4e93d156-9b39-4268-8544-a8e0480806d7", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "de1bec86-ca92-4b43-89fa-147653221cc0", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "469a05e5-e299-46f7-9598-7b05f3c34991", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "52f925c6-786a-4ec6-86ce-cba85c83453a", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "efc497ac-884e-4ee4-a4a8-15fba22aaf21", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "bfd9764d-2c5b-4c16-bfc1-89de3ca10917", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "f1792f32-6db2-4b50-b4b2-557128f1688d", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "f1792f32-6db2-4b50-b4b2-557128f1688d", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "f1792f32-6db2-4b50-b4b2-557128f1688d"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.h b/drivers/gpu/drm/i915/i915_oa_kblgt3.h index b0ca7f3114d3..d5b5b5c1923e 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt3.h +++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_KBLGT3_H__ #define __I915_OA_KBLGT3_H__ -extern int i915_oa_n_builtin_metric_sets_kblgt3; - -extern int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c b/drivers/gpu/drm/i915/i915_oa_sklgt2.c index 1268beda212c..93267e55f190 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c @@ -31,2317 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt2.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt2 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_1_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0080 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0d2000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162c2200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190001f }, - { _MMIO(0x9888), 0x51904400 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c21 }, - { _MMIO(0x9888), 0x47900061 }, - { _MMIO(0x9888), 0x57904440 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900004 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (dev_priv->drm.pdev->revision >= 0x02) { - regs[n] = mux_config_render_basic_1_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_basic_1_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8200 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x004f0db2 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f1880 }, - { _MMIO(0x9888), 0x0a4f0011 }, - { _MMIO(0x9888), 0x0c4f0e3c }, - { _MMIO(0x9888), 0x0e4f1d80 }, - { _MMIO(0x9888), 0x086c0002 }, - { _MMIO(0x9888), 0x0a6c0100 }, - { _MMIO(0x9888), 0x0e6c000c }, - { _MMIO(0x9888), 0x026c000b }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x081b4000 }, - { _MMIO(0x9888), 0x0a1b8000 }, - { _MMIO(0x9888), 0x0e1b4000 }, - { _MMIO(0x9888), 0x021b4000 }, - { _MMIO(0x9888), 0x1a1c4000 }, - { _MMIO(0x9888), 0x1c1c0012 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x005bc000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5bc000 }, - { _MMIO(0x9888), 0x0e5b8000 }, - { _MMIO(0x9888), 0x105c8000 }, - { _MMIO(0x9888), 0x1a5ca000 }, - { _MMIO(0x9888), 0x1c5c002d }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x0a4c0800 }, - { _MMIO(0x9888), 0x0c4c0082 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002cc000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cbe00 }, - { _MMIO(0x9888), 0x182c00ef }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900167 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900840 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900842 }, - { _MMIO(0x9888), 0x47900840 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900840 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900840 }, - { _MMIO(0x9888), 0x53901111 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1810 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0000 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900167 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900842 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53901111 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x15968000 }, - { _MMIO(0x9888), 0x17968000 }, - { _MMIO(0x9888), 0x0f96c000 }, - { _MMIO(0x9888), 0x1f950011 }, - { _MMIO(0x9888), 0x1d950014 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x0b978000 }, - { _MMIO(0x9888), 0x0f974000 }, - { _MMIO(0x9888), 0x11974000 }, - { _MMIO(0x9888), 0x13978000 }, - { _MMIO(0x9888), 0x09974000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x419010a0 }, - { _MMIO(0x9888), 0x55904000 }, - { _MMIO(0x9888), 0x45901000 }, - { _MMIO(0x9888), 0x47900084 }, - { _MMIO(0x9888), 0x57904400 }, - { _MMIO(0x9888), 0x499000a5 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900081 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x439014a4 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x05e5a000 }, - { _MMIO(0x9888), 0x01e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x419010a0 }, - { _MMIO(0x9888), 0x55904000 }, - { _MMIO(0x9888), 0x45901000 }, - { _MMIO(0x9888), 0x47900084 }, - { _MMIO(0x9888), 0x57904400 }, - { _MMIO(0x9888), 0x499000a5 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900081 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x439014a4 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (dev_priv->drm.pdev->revision < 0x02) { - regs[n] = mux_config_render_pipe_profile_0_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_lt_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x02) { - regs[n] = mux_config_render_pipe_profile_0_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13946000 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x0f968000 }, - { _MMIO(0x9888), 0x1196c000 }, - { _MMIO(0x9888), 0x13964000 }, - { _MMIO(0x9888), 0x11938000 }, - { _MMIO(0x9888), 0x1b93fe00 }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x19940000 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x1d940000 }, - { _MMIO(0x9888), 0x1b954000 }, - { _MMIO(0x9888), 0x1d95a550 }, - { _MMIO(0x9888), 0x1f9502aa }, - { _MMIO(0x9888), 0x2f900157 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13946000 }, - { _MMIO(0x9888), 0x15940016 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x1b93aa55 }, - { _MMIO(0x9888), 0x1d9300aa }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x0f940018 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x01e58000 }, - { _MMIO(0x9888), 0x03e57000 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c20 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900421 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900421 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_sku_gte_0x05[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((dev_priv->drm.pdev->revision < 0x05) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x05) { - regs[n] = mux_config_memory_reads_0_sku_gte_0x05; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_gte_0x05); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13945400 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901400 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x0f968000 }, - { _MMIO(0x9888), 0x1196c000 }, - { _MMIO(0x9888), 0x13964000 }, - { _MMIO(0x9888), 0x11938000 }, - { _MMIO(0x9888), 0x1b93fe00 }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x19940000 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x1d940000 }, - { _MMIO(0x9888), 0x1b954000 }, - { _MMIO(0x9888), 0x1d95a550 }, - { _MMIO(0x9888), 0x1f9502aa }, - { _MMIO(0x9888), 0x2f900167 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13945400 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901400 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x1b93aa55 }, - { _MMIO(0x9888), 0x1d93002a }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x01e58000 }, - { _MMIO(0x9888), 0x03e57000 }, - { _MMIO(0x9888), 0x2f900167 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c20 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900421 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900421 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_sku_gte_0x05[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((dev_priv->drm.pdev->revision < 0x05) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x05) { - regs[n] = mux_config_memory_writes_0_sku_gte_0x05; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_gte_0x05); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_compute_extended_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900167 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900042 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53901111 }, - { _MMIO(0x9888), 0x43900420 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9000a0 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0e0f006c }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1190e000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c00 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x143a5800 }, - { _MMIO(0x9888), 0x163a00c0 }, - { _MMIO(0x9888), 0x12380240 }, - { _MMIO(0x9888), 0x14380002 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c1500 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f9500 }, - { _MMIO(0x9888), 0x100f002a }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x0a2dc000 }, - { _MMIO(0x9888), 0x0c2dc000 }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x06393000 }, - { _MMIO(0x9888), 0x0c3a28c1 }, - { _MMIO(0x9888), 0x003a0000 }, - { _MMIO(0x9888), 0x0a33f000 }, - { _MMIO(0x9888), 0x0c33f000 }, - { _MMIO(0x9888), 0x0a37a000 }, - { _MMIO(0x9888), 0x0c37a000 }, - { _MMIO(0x9888), 0x0a380977 }, - { _MMIO(0x9888), 0x08380000 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06383000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900800 }, - { _MMIO(0x9888), 0x47901000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900844 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2714), 0xf0800000 }, @@ -2384,1096 +73,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "f519e481-24d2-4d42-87c9-3fdd12c00202", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "fe47b29d-ae51-423e-bff4-27d965a95b60", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "e0ad5ae0-84ba-4f29-a723-1906c12cb774", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "9bc436dd-6130-4add-affc-283eb6eaa864", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "2ea0da8f-3527-4669-9d9d-13099a7435bf", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "d97d16af-028b-4cd1-a672-6210cb5513dd", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "9fb22842-e708-43f7-9752-e0e41670c39e", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "5378e2a1-4248-4188-a4ae-da25a794c603", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "f42cdd6a-b000-42cb-870f-5eb423a7f514", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "b9bf2423-d88c-4a7b-a051-627611d00dcc", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "2414a93d-d84f-406e-99c0-472161194b40", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "b4cff514-a91e-4798-a0b3-426ca13fc9c1", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "7821d13b-9b8b-4405-9618-78cd56b62cce", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "893f1a4d-919d-4388-8cb7-746d73ea7259", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "41a24047-7484-4ead-ae37-de907e5ff2b2", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "95910492-943f-44bd-9461-390240f243fd", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "1651949f-0ac0-4cb1-a06f-dafd74a407d1", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.h b/drivers/gpu/drm/i915/i915_oa_sklgt2.h index f4397baf3328..fe1aa2c03958 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt2.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT2_H__ #define __I915_OA_SKLGT2_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt2; - -extern int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c b/drivers/gpu/drm/i915/i915_oa_sklgt3.c index 7765e22dfa17..2e342b4bc3a5 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c @@ -31,1876 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt3.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt3 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0380 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162ca200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0200 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x51907710 }, - { _MMIO(0x9888), 0x419020a0 }, - { _MMIO(0x9888), 0x55901515 }, - { _MMIO(0x9888), 0x45900529 }, - { _MMIO(0x9888), 0x47901025 }, - { _MMIO(0x9888), 0x57907770 }, - { _MMIO(0x9888), 0x49902100 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900108 }, - { _MMIO(0x9888), 0x59900007 }, - { _MMIO(0x9888), 0x43902108 }, - { _MMIO(0x9888), 0x53907777 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900863 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900c62 }, - { _MMIO(0x9888), 0x53903333 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51901150 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x55905111 }, - { _MMIO(0x9888), 0x45901400 }, - { _MMIO(0x9888), 0x479004a5 }, - { _MMIO(0x9888), 0x57903455 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b9000a0 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x43900005 }, - { _MMIO(0x9888), 0x53900455 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900063 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53903333 }, - { _MMIO(0x9888), 0x43900840 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900005 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900402 }, - { _MMIO(0x9888), 0x53901550 }, - { _MMIO(0x9888), 0x45900080 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900050 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900115 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900884 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1944,1096 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "4616d450-2393-4836-8146-53c5ed84d359", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "4ca0f3fe-7fd3-4924-98cb-1807d9879767", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "a0c0172c-ee13-403d-99ff-2bdf6936cf14", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "52435e0b-f188-42ea-8680-21a56ee20dee", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "27076eeb-49f3-4fed-8423-c66506005c63", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "8071b409-c39a-4674-94d7-32962ecfb512", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "25dc828e-1d2d-426e-9546-a1d4233cdf16", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "3dba9405-2d7e-4d70-8199-e734e82fd6bf", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "b375c985-9953-455b-bda2-b03f7594e9db", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "3e2be2bb-884a-49bb-82c5-2358e6bd5f2d", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "cfae9232-6ffc-42cc-a703-9790016925f0", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "2b985803-d3c9-4629-8a4f-634bfecba0e8", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "2b985803-d3c9-4629-8a4f-634bfecba0e8", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.h b/drivers/gpu/drm/i915/i915_oa_sklgt3.h index c0accb1f9b74..06746b2616c8 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt3.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT3_H__ #define __I915_OA_SKLGT3_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt3; - -extern int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c b/drivers/gpu/drm/i915/i915_oa_sklgt4.c index 9ddab43a2176..f933f497c15a 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt4.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c @@ -31,1930 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt4.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt4 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x176c01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e03b0 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4ca400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0230 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0acc2000 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x088d8000 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x0e8f1000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8800 }, - { _MMIO(0x9888), 0x1b4e0020 }, - { _MMIO(0x9888), 0x096c5300 }, - { _MMIO(0x9888), 0x116c0000 }, - { _MMIO(0x9888), 0x1d6c0000 }, - { _MMIO(0x9888), 0x091b8000 }, - { _MMIO(0x9888), 0x1b1c8000 }, - { _MMIO(0x9888), 0x0b4c2000 }, - { _MMIO(0x9888), 0x090d8000 }, - { _MMIO(0x9888), 0x0f0f1000 }, - { _MMIO(0x9888), 0x172c0800 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x5190ff30 }, - { _MMIO(0x9888), 0x41900060 }, - { _MMIO(0x9888), 0x55903033 }, - { _MMIO(0x9888), 0x45901421 }, - { _MMIO(0x9888), 0x47900803 }, - { _MMIO(0x9888), 0x5790fff1 }, - { _MMIO(0x9888), 0x49900001 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x5990000f }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x5390ffff }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53905555 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51901110 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55901111 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57901411 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900411 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53905555 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x131203e0 }, - { _MMIO(0x9888), 0x133203e0 }, - { _MMIO(0x9888), 0x135203e0 }, - { _MMIO(0x9888), 0x1a4ef000 }, - { _MMIO(0x9888), 0x1c4e0003 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0c4c02a0 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0150 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x182c00a8 }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1acef000 }, - { _MMIO(0x9888), 0x1cce0003 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0ccc02a0 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x0c8d8000 }, - { _MMIO(0x9888), 0x0e8da000 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x108f0150 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x18ac00a8 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x072f8000 }, - { _MMIO(0x9888), 0x0d4c0100 }, - { _MMIO(0x9888), 0x0d0d8000 }, - { _MMIO(0x9888), 0x0f0da000 }, - { _MMIO(0x9888), 0x110f01b0 }, - { _MMIO(0x9888), 0x192c0080 }, - { _MMIO(0x9888), 0x0f2d4000 }, - { _MMIO(0x9888), 0x0f108000 }, - { _MMIO(0x9888), 0x0f118000 }, - { _MMIO(0x9888), 0x0f121980 }, - { _MMIO(0x9888), 0x01120000 }, - { _MMIO(0x9888), 0x0f134000 }, - { _MMIO(0x9888), 0x0f304000 }, - { _MMIO(0x9888), 0x0f314000 }, - { _MMIO(0x9888), 0x0f320033 }, - { _MMIO(0x9888), 0x01320000 }, - { _MMIO(0x9888), 0x0f331000 }, - { _MMIO(0x9888), 0x0d508000 }, - { _MMIO(0x9888), 0x0d518000 }, - { _MMIO(0x9888), 0x0d521980 }, - { _MMIO(0x9888), 0x01520000 }, - { _MMIO(0x9888), 0x0d534000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51901100 }, - { _MMIO(0x9888), 0x41901000 }, - { _MMIO(0x9888), 0x43901423 }, - { _MMIO(0x9888), 0x53903331 }, - { _MMIO(0x9888), 0x45900044 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900010 }, - { _MMIO(0x9888), 0x41900060 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900821 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1998,1096 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "bad77c24-cc64-480d-99bf-e7b740713800", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "7277228f-e7f3-4743-945a-6a2049d11377", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "463c668c-3f60-49b6-8f85-d995b635b3b2", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "055f256d-4052-467c-8dec-6064a4806433", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "753972d4-87cd-4460-824d-754463ac5054", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "d9e86d70-462b-462a-851e-fd63e8c13d63", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "1988315f-0a26-44df-acb0-df7ec86b1456", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "97875e21-6624-4aee-9191-682feb3eae21", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); -} - -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "882fa433-1f4a-4a67-a962-c741888fe5f5", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; - - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } - - return 0; - -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; + return sprintf(buf, "1\n"); } void -i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv) +i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + strncpy(dev_priv->perf.oa.test_config.uuid, + "882fa433-1f4a-4a67-a962-c741888fe5f5", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); + + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); + + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); + + dev_priv->perf.oa.test_config.sysfs_metric.name = "882fa433-1f4a-4a67-a962-c741888fe5f5"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; + + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.h b/drivers/gpu/drm/i915/i915_oa_sklgt4.h index 1b718f15f62e..944fd525c8b1 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt4.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT4_H__ #define __I915_OA_SKLGT4_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt4; - -extern int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index df78bfa9e574..7ca03351f5bc 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1249,7 +1249,9 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) * Unset exclusive_stream first, it might be checked while * disabling the metric set on gen8+. */ + mutex_lock(&dev_priv->drm.struct_mutex); dev_priv->perf.oa.exclusive_stream = NULL; + mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv->perf.oa.ops.disable_metric_set(dev_priv); @@ -1440,9 +1442,9 @@ unlock: static void config_oa_regs(struct drm_i915_private *dev_priv, const struct i915_oa_reg *regs, - int n_regs) + u32 n_regs) { - int i; + u32 i; for (i = 0; i < n_regs; i++) { const struct i915_oa_reg *reg = regs + i; @@ -1451,14 +1453,9 @@ static void config_oa_regs(struct drm_i915_private *dev_priv, } } -static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) +static int hsw_enable_metric_set(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { - int ret = i915_oa_select_metric_set_hsw(dev_priv); - int i; - - if (ret) - return ret; - I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) | GT_NOA_ENABLE)); @@ -1476,10 +1473,7 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | GEN6_CSUNIT_CLOCK_GATE_DISABLE)); - for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) { - config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i], - dev_priv->perf.oa.mux_regs_lens[i]); - } + config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); /* It apparently takes a fairly long time for a new MUX * configuration to be be applied after these register writes. @@ -1504,8 +1498,8 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) */ usleep_range(15000, 20000); - config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, - dev_priv->perf.oa.b_counter_regs_len); + config_oa_regs(dev_priv, oa_config->b_counter_regs, + oa_config->b_counter_regs_len); return 0; } @@ -1529,11 +1523,10 @@ static void hsw_disable_metric_set(struct drm_i915_private *dev_priv) * in the case that the OA unit has been disabled. */ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, - u32 *reg_state) + u32 *reg_state, + const struct i915_oa_config *oa_config) { struct drm_i915_private *dev_priv = ctx->i915; - const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; - int n_flex_regs = dev_priv->perf.oa.flex_regs_len; u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset; u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset; /* The MMIO offsets for Flex EU registers aren't contiguous */ @@ -1565,12 +1558,15 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, * will be an explicit 'No Event' we can select, but not yet... */ u32 value = 0; - int j; - for (j = 0; j < n_flex_regs; j++) { - if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) { - value = flex_regs[j].value; - break; + if (oa_config) { + u32 j; + + for (j = 0; j < oa_config->flex_regs_len; j++) { + if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) { + value = oa_config->flex_regs[j].value; + break; + } } } @@ -1583,11 +1579,10 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, * Same as gen8_update_reg_state_unlocked only through the batchbuffer. This * is only used by the kernel context. */ -static int gen8_emit_oa_config(struct drm_i915_gem_request *req) +static int gen8_emit_oa_config(struct drm_i915_gem_request *req, + const struct i915_oa_config *oa_config) { struct drm_i915_private *dev_priv = req->i915; - const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; - int n_flex_regs = dev_priv->perf.oa.flex_regs_len; /* The MMIO offsets for Flex EU registers aren't contiguous */ u32 flex_mmio[] = { i915_mmio_reg_offset(EU_PERF_CNTL0), @@ -1622,12 +1617,15 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) * yet... */ u32 value = 0; - int j; - for (j = 0; j < n_flex_regs; j++) { - if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) { - value = flex_regs[j].value; - break; + if (oa_config) { + u32 j; + + for (j = 0; j < oa_config->flex_regs_len; j++) { + if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) { + value = oa_config->flex_regs[j].value; + break; + } } } @@ -1641,7 +1639,8 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) return 0; } -static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv) +static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { struct intel_engine_cs *engine = dev_priv->engine[RCS]; struct i915_gem_timeline *timeline; @@ -1656,7 +1655,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr if (IS_ERR(req)) return PTR_ERR(req); - ret = gen8_emit_oa_config(req); + ret = gen8_emit_oa_config(req, oa_config); if (ret) { i915_add_request(req); return ret; @@ -1707,6 +1706,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr * Note: it's only the RCS/Render context that has any OA state. */ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config, bool interruptible) { struct i915_gem_context *ctx; @@ -1724,7 +1724,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, } /* Switch away from any user context. */ - ret = gen8_switch_to_updated_kernel_context(dev_priv); + ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config); if (ret) goto out; @@ -1763,7 +1763,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, ce->state->obj->mm.dirty = true; regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs); - gen8_update_reg_state_unlocked(ctx, regs); + gen8_update_reg_state_unlocked(ctx, regs, oa_config); i915_gem_object_unpin_map(ce->state->obj); } @@ -1774,13 +1774,10 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, return ret; } -static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) +static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { - int ret = dev_priv->perf.oa.ops.select_metric_set(dev_priv); - int i; - - if (ret) - return ret; + int ret; /* * We disable slice/unslice clock ratio change reports on SKL since @@ -1817,19 +1814,18 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) * to make sure all slices/subslices are ON before writing to NOA * registers. */ - ret = gen8_configure_all_contexts(dev_priv, true); + ret = gen8_configure_all_contexts(dev_priv, oa_config, true); if (ret) return ret; I915_WRITE(GDT_CHICKEN_BITS, 0xA0); - for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) { - config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i], - dev_priv->perf.oa.mux_regs_lens[i]); - } + + config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); + I915_WRITE(GDT_CHICKEN_BITS, 0x80); - config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, - dev_priv->perf.oa.b_counter_regs_len); + config_oa_regs(dev_priv, oa_config->b_counter_regs, + oa_config->b_counter_regs_len); return 0; } @@ -1837,7 +1833,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) static void gen8_disable_metric_set(struct drm_i915_private *dev_priv) { /* Reset all contexts' slices/subslices configurations. */ - gen8_configure_all_contexts(dev_priv, false); + gen8_configure_all_contexts(dev_priv, NULL, false); } static void gen7_oa_enable(struct drm_i915_private *dev_priv) @@ -1957,6 +1953,15 @@ static const struct i915_perf_stream_ops i915_oa_stream_ops = { .read = i915_oa_read, }; +static struct i915_oa_config *get_oa_config(struct drm_i915_private *dev_priv, + int metrics_set) +{ + if (metrics_set == 1) + return &dev_priv->perf.oa.test_config; + + return NULL; +} + /** * i915_oa_stream_init - validate combined props for OA stream and init * @stream: An i915 perf stream @@ -2011,11 +2016,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, return -EBUSY; } - if (!props->metrics_set) { - DRM_DEBUG("OA metric set not specified\n"); - return -EINVAL; - } - if (!props->oa_format) { DRM_DEBUG("OA report format not specified\n"); return -EINVAL; @@ -2055,8 +2055,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, dev_priv->perf.oa.oa_buffer.format = dev_priv->perf.oa.oa_formats[props->oa_format].format; - dev_priv->perf.oa.metrics_set = props->metrics_set; - dev_priv->perf.oa.periodic = props->oa_periodic; if (dev_priv->perf.oa.periodic) dev_priv->perf.oa.period_exponent = props->oa_period_exponent; @@ -2067,6 +2065,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, return ret; } + stream->oa_config = get_oa_config(dev_priv, props->metrics_set); + if (!stream->oa_config) + return -EINVAL; + /* PRM - observability performance counters: * * OACONTROL, performance counter enable, note: @@ -2086,16 +2088,29 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, if (ret) goto err_oa_buf_alloc; - ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv); + ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv, + stream->oa_config); if (ret) goto err_enable; stream->ops = &i915_oa_stream_ops; + /* Lock device for exclusive_stream access late because + * enable_metric_set() might lock as well on gen8+. + */ + ret = i915_mutex_lock_interruptible(&dev_priv->drm); + if (ret) + goto err_lock; + dev_priv->perf.oa.exclusive_stream = stream; + mutex_unlock(&dev_priv->drm.struct_mutex); + return 0; +err_lock: + dev_priv->perf.oa.ops.disable_metric_set(dev_priv); + err_enable: free_oa_buffer(dev_priv); @@ -2113,6 +2128,7 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, u32 *reg_state) { struct drm_i915_private *dev_priv = engine->i915; + struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream; if (engine->id != RCS) return; @@ -2120,7 +2136,8 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, if (!dev_priv->perf.initialized) return; - gen8_update_reg_state_unlocked(ctx, reg_state); + if (stream) + gen8_update_reg_state_unlocked(ctx, reg_state, stream->oa_config); } /** @@ -2643,7 +2660,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, struct perf_open_properties *props) { u64 __user *uprop = uprops; - int i; + u32 i; memset(props, 0, sizeof(struct perf_open_properties)); @@ -2690,8 +2707,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, props->sample_flags |= SAMPLE_OA_REPORT; break; case DRM_I915_PERF_PROP_OA_METRICS_SET: - if (value == 0 || - value > dev_priv->perf.oa.n_builtin_sets) { + if (value == 0) { DRM_DEBUG("Unknown OA metric set ID\n"); return -EINVAL; } @@ -2830,6 +2846,8 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data, */ void i915_perf_register(struct drm_i915_private *dev_priv) { + int ret; + if (!dev_priv->perf.initialized) return; @@ -2845,44 +2863,40 @@ void i915_perf_register(struct drm_i915_private *dev_priv) if (!dev_priv->perf.metrics_kobj) goto exit; + memset(&dev_priv->perf.oa.test_config, 0, + sizeof(dev_priv->perf.oa.test_config)); + if (IS_HASWELL(dev_priv)) { - if (i915_perf_register_sysfs_hsw(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_hsw(dev_priv); } else if (IS_BROADWELL(dev_priv)) { - if (i915_perf_register_sysfs_bdw(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_bdw(dev_priv); } else if (IS_CHERRYVIEW(dev_priv)) { - if (i915_perf_register_sysfs_chv(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_chv(dev_priv); } else if (IS_SKYLAKE(dev_priv)) { - if (IS_SKL_GT2(dev_priv)) { - if (i915_perf_register_sysfs_sklgt2(dev_priv)) - goto sysfs_error; - } else if (IS_SKL_GT3(dev_priv)) { - if (i915_perf_register_sysfs_sklgt3(dev_priv)) - goto sysfs_error; - } else if (IS_SKL_GT4(dev_priv)) { - if (i915_perf_register_sysfs_sklgt4(dev_priv)) - goto sysfs_error; - } else - goto sysfs_error; + if (IS_SKL_GT2(dev_priv)) + i915_perf_load_test_config_sklgt2(dev_priv); + else if (IS_SKL_GT3(dev_priv)) + i915_perf_load_test_config_sklgt3(dev_priv); + else if (IS_SKL_GT4(dev_priv)) + i915_perf_load_test_config_sklgt4(dev_priv); } else if (IS_BROXTON(dev_priv)) { - if (i915_perf_register_sysfs_bxt(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_bxt(dev_priv); } else if (IS_KABYLAKE(dev_priv)) { - if (IS_KBL_GT2(dev_priv)) { - if (i915_perf_register_sysfs_kblgt2(dev_priv)) - goto sysfs_error; - } else if (IS_KBL_GT3(dev_priv)) { - if (i915_perf_register_sysfs_kblgt3(dev_priv)) - goto sysfs_error; - } else - goto sysfs_error; + if (IS_KBL_GT2(dev_priv)) + i915_perf_load_test_config_kblgt2(dev_priv); + else if (IS_KBL_GT3(dev_priv)) + i915_perf_load_test_config_kblgt3(dev_priv); } else if (IS_GEMINILAKE(dev_priv)) { - if (i915_perf_register_sysfs_glk(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_glk(dev_priv); } + if (dev_priv->perf.oa.test_config.id == 0) + goto sysfs_error; + + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, + &dev_priv->perf.oa.test_config.sysfs_metric); + if (ret) + goto sysfs_error; goto exit; sysfs_error: @@ -2907,29 +2921,8 @@ void i915_perf_unregister(struct drm_i915_private *dev_priv) if (!dev_priv->perf.metrics_kobj) return; - if (IS_HASWELL(dev_priv)) - i915_perf_unregister_sysfs_hsw(dev_priv); - else if (IS_BROADWELL(dev_priv)) - i915_perf_unregister_sysfs_bdw(dev_priv); - else if (IS_CHERRYVIEW(dev_priv)) - i915_perf_unregister_sysfs_chv(dev_priv); - else if (IS_SKYLAKE(dev_priv)) { - if (IS_SKL_GT2(dev_priv)) - i915_perf_unregister_sysfs_sklgt2(dev_priv); - else if (IS_SKL_GT3(dev_priv)) - i915_perf_unregister_sysfs_sklgt3(dev_priv); - else if (IS_SKL_GT4(dev_priv)) - i915_perf_unregister_sysfs_sklgt4(dev_priv); - } else if (IS_BROXTON(dev_priv)) - i915_perf_unregister_sysfs_bxt(dev_priv); - else if (IS_KABYLAKE(dev_priv)) { - if (IS_KBL_GT2(dev_priv)) - i915_perf_unregister_sysfs_kblgt2(dev_priv); - else if (IS_KBL_GT3(dev_priv)) - i915_perf_unregister_sysfs_kblgt3(dev_priv); - } else if (IS_GEMINILAKE(dev_priv)) - i915_perf_unregister_sysfs_glk(dev_priv); - + sysfs_remove_group(dev_priv->perf.metrics_kobj, + &dev_priv->perf.oa.test_config.sysfs_metric); kobject_put(dev_priv->perf.metrics_kobj); dev_priv->perf.metrics_kobj = NULL; @@ -2988,7 +2981,7 @@ static struct ctl_table dev_root[] = { */ void i915_perf_init(struct drm_i915_private *dev_priv) { - dev_priv->perf.oa.n_builtin_sets = 0; + dev_priv->perf.oa.timestamp_frequency = 0; if (IS_HASWELL(dev_priv)) { dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer; @@ -3003,9 +2996,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 12500000; dev_priv->perf.oa.oa_formats = hsw_oa_formats; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_hsw; } else if (i915.enable_execlists) { /* Note: that although we could theoretically also support the * legacy ringbuffer mode on BDW (and earlier iterations of @@ -3014,6 +3004,16 @@ void i915_perf_init(struct drm_i915_private *dev_priv) * execlist mode by default. */ + dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; + dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set; + dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable; + dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable; + dev_priv->perf.oa.ops.read = gen8_oa_read; + dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; + + dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats; + if (IS_GEN8(dev_priv)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce; @@ -3021,85 +3021,31 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 12500000; dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25); - - if (IS_BROADWELL(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_bdw; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_bdw; - } else if (IS_CHERRYVIEW(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_chv; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_chv; - } } else if (IS_GEN9(dev_priv)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; - dev_priv->perf.oa.timestamp_frequency = 12000000; - dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); - if (IS_SKL_GT2(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt2; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt2; - } else if (IS_SKL_GT3(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt3; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt3; - } else if (IS_SKL_GT4(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt4; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt4; - } else if (IS_BROXTON(dev_priv)) { + switch (dev_priv->info.platform) { + case INTEL_BROXTON: + case INTEL_GEMINILAKE: dev_priv->perf.oa.timestamp_frequency = 19200000; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_bxt; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_bxt; - } else if (IS_KBL_GT2(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_kblgt2; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_kblgt2; - } else if (IS_KBL_GT3(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_kblgt3; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_kblgt3; - } else if (IS_GEMINILAKE(dev_priv)) { - dev_priv->perf.oa.timestamp_frequency = 19200000; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_glk; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_glk; + break; + case INTEL_SKYLAKE: + case INTEL_KABYLAKE: + dev_priv->perf.oa.timestamp_frequency = 12000000; + break; + default: + /* Leave timestamp_frequency to 0 so we can + * detect unsupported platforms. + */ + break; } } - - if (dev_priv->perf.oa.n_builtin_sets) { - dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; - dev_priv->perf.oa.ops.enable_metric_set = - gen8_enable_metric_set; - dev_priv->perf.oa.ops.disable_metric_set = - gen8_disable_metric_set; - dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable; - dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable; - dev_priv->perf.oa.ops.read = gen8_oa_read; - dev_priv->perf.oa.ops.oa_hw_tail_read = - gen8_oa_hw_tail_read; - - dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats; - } } - if (dev_priv->perf.oa.n_builtin_sets) { + if (dev_priv->perf.oa.timestamp_frequency) { hrtimer_init(&dev_priv->perf.oa.poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb; From 3802c5cb209f6e2735c4ced7462b637a7e16bbf5 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 3 Aug 2017 17:58:09 +0100 Subject: [PATCH 093/179] drm/i915/perf: leave GDT_CHICKEN_BITS programming in configs There will be a need for userspaces configurations to set this register. We can apply the same model inside the kernel for test configs. Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-4-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_oa_bdw.c | 2 ++ drivers/gpu/drm/i915/i915_oa_bxt.c | 1 + drivers/gpu/drm/i915/i915_oa_chv.c | 2 ++ drivers/gpu/drm/i915/i915_oa_glk.c | 1 + drivers/gpu/drm/i915/i915_oa_hsw.c | 1 + drivers/gpu/drm/i915/i915_oa_kblgt2.c | 1 + drivers/gpu/drm/i915/i915_oa_kblgt3.c | 1 + drivers/gpu/drm/i915/i915_oa_sklgt2.c | 1 + drivers/gpu/drm/i915/i915_oa_sklgt3.c | 1 + drivers/gpu/drm/i915/i915_oa_sklgt4.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 7 ------- 11 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c index 187067001179..abdf4d0abcce 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.c +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x000000a0 }, { _MMIO(0x9888), 0x198b0000 }, { _MMIO(0x9888), 0x078b0066 }, { _MMIO(0x9888), 0x118b0000 }, @@ -72,6 +73,7 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x4f800000 }, { _MMIO(0x9888), 0x41800000 }, { _MMIO(0x9888), 0x31800000 }, + { _MMIO(0x9840), 0x00000080 }, }; static ssize_t diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c b/drivers/gpu/drm/i915/i915_oa_bxt.c index d52074429def..b69b900de0fe 100644 --- a/drivers/gpu/drm/i915/i915_oa_bxt.c +++ b/drivers/gpu/drm/i915/i915_oa_bxt.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x19800000 }, { _MMIO(0x9888), 0x07800063 }, { _MMIO(0x9888), 0x11800000 }, diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c index b4832a0fefaa..322a3f94cd16 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.c +++ b/drivers/gpu/drm/i915/i915_oa_chv.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x000000a0 }, { _MMIO(0x9888), 0x59800000 }, { _MMIO(0x9888), 0x59800001 }, { _MMIO(0x9888), 0x338b0000 }, @@ -71,6 +72,7 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x57800000 }, { _MMIO(0x1823a4), 0x00000000 }, { _MMIO(0x9888), 0x59800000 }, + { _MMIO(0x9840), 0x00000080 }, }; static ssize_t diff --git a/drivers/gpu/drm/i915/i915_oa_glk.c b/drivers/gpu/drm/i915/i915_oa_glk.c index f0dbab5d19e0..4ee527e4c926 100644 --- a/drivers/gpu/drm/i915/i915_oa_glk.c +++ b/drivers/gpu/drm/i915/i915_oa_glk.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x19800000 }, { _MMIO(0x9888), 0x07800063 }, { _MMIO(0x9888), 0x11800000 }, diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c index 867ec16dd831..56b03773bb9d 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.c +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c @@ -42,6 +42,7 @@ static const struct i915_oa_reg flex_eu_config_render_basic[] = { }; static const struct i915_oa_reg mux_config_render_basic[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x253a4), 0x01600000 }, { _MMIO(0x25440), 0x00100000 }, { _MMIO(0x25128), 0x00000000 }, diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.c b/drivers/gpu/drm/i915/i915_oa_kblgt2.c index 2e8700c74227..b6e7cc774136 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.c b/drivers/gpu/drm/i915/i915_oa_kblgt3.c index ea524e024c72..5576afdd9a7e 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c b/drivers/gpu/drm/i915/i915_oa_sklgt2.c index 93267e55f190..890d55879946 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c @@ -59,6 +59,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810016 }, { _MMIO(0x9888), 0x1f810000 }, diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c b/drivers/gpu/drm/i915/i915_oa_sklgt3.c index 2e342b4bc3a5..85e51addf86a 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c b/drivers/gpu/drm/i915/i915_oa_sklgt4.c index f933f497c15a..bce031ee4445 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt4.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c @@ -60,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 7ca03351f5bc..f1993bbfd4fa 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1456,9 +1456,6 @@ static void config_oa_regs(struct drm_i915_private *dev_priv, static int hsw_enable_metric_set(struct drm_i915_private *dev_priv, const struct i915_oa_config *oa_config) { - I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) | - GT_NOA_ENABLE)); - /* PRM: * * OA unit is using “crclk” for its functionality. When trunk @@ -1818,12 +1815,8 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, if (ret) return ret; - I915_WRITE(GDT_CHICKEN_BITS, 0xA0); - config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); - I915_WRITE(GDT_CHICKEN_BITS, 0x80); - config_oa_regs(dev_priv, oa_config->b_counter_regs, oa_config->b_counter_regs_len); From 28964cf25ee67e1128f7fbb7da3a792471adf47e Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 3 Aug 2017 17:58:10 +0100 Subject: [PATCH 094/179] drm/i915/perf: disable NOA logic when not used We already do it on Haswell and the documentation says it saves power. Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-5-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_perf.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index f1993bbfd4fa..06a5e1e83e6c 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1827,6 +1827,10 @@ static void gen8_disable_metric_set(struct drm_i915_private *dev_priv) { /* Reset all contexts' slices/subslices configurations. */ gen8_configure_all_contexts(dev_priv, NULL, false); + + I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) & + ~GT_NOA_ENABLE)); + } static void gen7_oa_enable(struct drm_i915_private *dev_priv) From 7853d92e8e95da56016a3ada0fe06296eaaac3f6 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 3 Aug 2017 17:58:11 +0100 Subject: [PATCH 095/179] drm/i915: reorder NOA register definition to follow addresses It makes things easier to read when implementing whitelisting in the following patches. Signed-off-by: Lionel Landwerlin Reviewed-by: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-6-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 212 ++++++++++++++++---------------- 1 file changed, 106 insertions(+), 106 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1dc7e7a2a23b..0a42b6071ea1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -736,112 +736,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) * OA Boolean state */ -#define OAREPORTTRIG1 _MMIO(0x2740) -#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ - -#define OAREPORTTRIG2 _MMIO(0x2744) -#define OAREPORTTRIG2_INVERT_A_0 (1<<0) -#define OAREPORTTRIG2_INVERT_A_1 (1<<1) -#define OAREPORTTRIG2_INVERT_A_2 (1<<2) -#define OAREPORTTRIG2_INVERT_A_3 (1<<3) -#define OAREPORTTRIG2_INVERT_A_4 (1<<4) -#define OAREPORTTRIG2_INVERT_A_5 (1<<5) -#define OAREPORTTRIG2_INVERT_A_6 (1<<6) -#define OAREPORTTRIG2_INVERT_A_7 (1<<7) -#define OAREPORTTRIG2_INVERT_A_8 (1<<8) -#define OAREPORTTRIG2_INVERT_A_9 (1<<9) -#define OAREPORTTRIG2_INVERT_A_10 (1<<10) -#define OAREPORTTRIG2_INVERT_A_11 (1<<11) -#define OAREPORTTRIG2_INVERT_A_12 (1<<12) -#define OAREPORTTRIG2_INVERT_A_13 (1<<13) -#define OAREPORTTRIG2_INVERT_A_14 (1<<14) -#define OAREPORTTRIG2_INVERT_A_15 (1<<15) -#define OAREPORTTRIG2_INVERT_B_0 (1<<16) -#define OAREPORTTRIG2_INVERT_B_1 (1<<17) -#define OAREPORTTRIG2_INVERT_B_2 (1<<18) -#define OAREPORTTRIG2_INVERT_B_3 (1<<19) -#define OAREPORTTRIG2_INVERT_C_0 (1<<20) -#define OAREPORTTRIG2_INVERT_C_1 (1<<21) -#define OAREPORTTRIG2_INVERT_D_0 (1<<22) -#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) -#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) - -#define OAREPORTTRIG3 _MMIO(0x2748) -#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG4 _MMIO(0x274c) -#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 - -#define OAREPORTTRIG5 _MMIO(0x2750) -#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ - -#define OAREPORTTRIG6 _MMIO(0x2754) -#define OAREPORTTRIG6_INVERT_A_0 (1<<0) -#define OAREPORTTRIG6_INVERT_A_1 (1<<1) -#define OAREPORTTRIG6_INVERT_A_2 (1<<2) -#define OAREPORTTRIG6_INVERT_A_3 (1<<3) -#define OAREPORTTRIG6_INVERT_A_4 (1<<4) -#define OAREPORTTRIG6_INVERT_A_5 (1<<5) -#define OAREPORTTRIG6_INVERT_A_6 (1<<6) -#define OAREPORTTRIG6_INVERT_A_7 (1<<7) -#define OAREPORTTRIG6_INVERT_A_8 (1<<8) -#define OAREPORTTRIG6_INVERT_A_9 (1<<9) -#define OAREPORTTRIG6_INVERT_A_10 (1<<10) -#define OAREPORTTRIG6_INVERT_A_11 (1<<11) -#define OAREPORTTRIG6_INVERT_A_12 (1<<12) -#define OAREPORTTRIG6_INVERT_A_13 (1<<13) -#define OAREPORTTRIG6_INVERT_A_14 (1<<14) -#define OAREPORTTRIG6_INVERT_A_15 (1<<15) -#define OAREPORTTRIG6_INVERT_B_0 (1<<16) -#define OAREPORTTRIG6_INVERT_B_1 (1<<17) -#define OAREPORTTRIG6_INVERT_B_2 (1<<18) -#define OAREPORTTRIG6_INVERT_B_3 (1<<19) -#define OAREPORTTRIG6_INVERT_C_0 (1<<20) -#define OAREPORTTRIG6_INVERT_C_1 (1<<21) -#define OAREPORTTRIG6_INVERT_D_0 (1<<22) -#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) -#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) - -#define OAREPORTTRIG7 _MMIO(0x2758) -#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG8 _MMIO(0x275c) -#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 - #define OASTARTTRIG1 _MMIO(0x2710) #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff @@ -956,6 +850,112 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 +#define OAREPORTTRIG1 _MMIO(0x2740) +#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG2 _MMIO(0x2744) +#define OAREPORTTRIG2_INVERT_A_0 (1<<0) +#define OAREPORTTRIG2_INVERT_A_1 (1<<1) +#define OAREPORTTRIG2_INVERT_A_2 (1<<2) +#define OAREPORTTRIG2_INVERT_A_3 (1<<3) +#define OAREPORTTRIG2_INVERT_A_4 (1<<4) +#define OAREPORTTRIG2_INVERT_A_5 (1<<5) +#define OAREPORTTRIG2_INVERT_A_6 (1<<6) +#define OAREPORTTRIG2_INVERT_A_7 (1<<7) +#define OAREPORTTRIG2_INVERT_A_8 (1<<8) +#define OAREPORTTRIG2_INVERT_A_9 (1<<9) +#define OAREPORTTRIG2_INVERT_A_10 (1<<10) +#define OAREPORTTRIG2_INVERT_A_11 (1<<11) +#define OAREPORTTRIG2_INVERT_A_12 (1<<12) +#define OAREPORTTRIG2_INVERT_A_13 (1<<13) +#define OAREPORTTRIG2_INVERT_A_14 (1<<14) +#define OAREPORTTRIG2_INVERT_A_15 (1<<15) +#define OAREPORTTRIG2_INVERT_B_0 (1<<16) +#define OAREPORTTRIG2_INVERT_B_1 (1<<17) +#define OAREPORTTRIG2_INVERT_B_2 (1<<18) +#define OAREPORTTRIG2_INVERT_B_3 (1<<19) +#define OAREPORTTRIG2_INVERT_C_0 (1<<20) +#define OAREPORTTRIG2_INVERT_C_1 (1<<21) +#define OAREPORTTRIG2_INVERT_D_0 (1<<22) +#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG3 _MMIO(0x2748) +#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG4 _MMIO(0x274c) +#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 + +#define OAREPORTTRIG5 _MMIO(0x2750) +#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG6 _MMIO(0x2754) +#define OAREPORTTRIG6_INVERT_A_0 (1<<0) +#define OAREPORTTRIG6_INVERT_A_1 (1<<1) +#define OAREPORTTRIG6_INVERT_A_2 (1<<2) +#define OAREPORTTRIG6_INVERT_A_3 (1<<3) +#define OAREPORTTRIG6_INVERT_A_4 (1<<4) +#define OAREPORTTRIG6_INVERT_A_5 (1<<5) +#define OAREPORTTRIG6_INVERT_A_6 (1<<6) +#define OAREPORTTRIG6_INVERT_A_7 (1<<7) +#define OAREPORTTRIG6_INVERT_A_8 (1<<8) +#define OAREPORTTRIG6_INVERT_A_9 (1<<9) +#define OAREPORTTRIG6_INVERT_A_10 (1<<10) +#define OAREPORTTRIG6_INVERT_A_11 (1<<11) +#define OAREPORTTRIG6_INVERT_A_12 (1<<12) +#define OAREPORTTRIG6_INVERT_A_13 (1<<13) +#define OAREPORTTRIG6_INVERT_A_14 (1<<14) +#define OAREPORTTRIG6_INVERT_A_15 (1<<15) +#define OAREPORTTRIG6_INVERT_B_0 (1<<16) +#define OAREPORTTRIG6_INVERT_B_1 (1<<17) +#define OAREPORTTRIG6_INVERT_B_2 (1<<18) +#define OAREPORTTRIG6_INVERT_B_3 (1<<19) +#define OAREPORTTRIG6_INVERT_C_0 (1<<20) +#define OAREPORTTRIG6_INVERT_C_1 (1<<21) +#define OAREPORTTRIG6_INVERT_D_0 (1<<22) +#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG7 _MMIO(0x2758) +#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG8 _MMIO(0x275c) +#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 + /* CECX_0 */ #define OACEC_COMPARE_LESS_OR_EQUAL 6 #define OACEC_COMPARE_NOT_EQUAL 5 From f89823c212246d0671cc51e69894a3df1a743aee Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 3 Aug 2017 18:05:50 +0100 Subject: [PATCH 096/179] drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface The motivation behind this new interface is expose at runtime the creation of new OA configs which can be used as part of the i915 perf open interface. This will enable the kernel to learn new configs which may be experimental, or otherwise not part of the core set currently available through the i915 perf interface. v2: Drop DRM_ERROR for userspace errors (Matthew) Add padding to userspace structure (Matthew) s/guid/uuid/ (Matthew) v3: Use u32 instead of int to iterate through registers (Matthew) v4: Lock access to dynamic config list (Lionel) v5: by Matthew: Fix uninitialized error values Fix incorrect unwiding when opening perf stream Use kmalloc_array() to store register Use uuid_is_valid() to valid config uuids Declare ioctls as write only Check padding members are set to 0 by Lionel: Return ENOENT rather than EINVAL when trying to remove non existing config v6: by Chris: Use ref counts for OA configs Store UUID in drm_i915_perf_oa_config rather then using pointer Shuffle fields of drm_i915_perf_oa_config to avoid padding v7: by Chris Rename uapi pointers fields to end with '_ptr' v8: by Andrzej, Marek, Sebastian Update register whitelisting by Lionel Add more register names for documentation Allow configuration programming in non-paranoid mode Add support for value filter for a couple of registers already programmed in other part of the kernel v9: Documentation fix (Lionel) Allow writing WAIT_FOR_RC6_EXIT only on Gen8+ (Andrzej) v10: Perform read access_ok() on register pointers (Lionel) Signed-off-by: Matthew Auld Signed-off-by: Lionel Landwerlin Signed-off-by: Andrzej Datczuk Reviewed-by: Andrzej Datczuk Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-2-lionel.g.landwerlin@intel.com --- Documentation/gpu/i915.rst | 4 + drivers/gpu/drm/i915/i915_drv.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 47 +++ drivers/gpu/drm/i915/i915_perf.c | 471 ++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 70 ++++- include/uapi/drm/i915_drm.h | 20 ++ 6 files changed, 597 insertions(+), 17 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 9c7ed3e3f1e9..46875c2bcc31 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -417,6 +417,10 @@ integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. :functions: i915_perf_open_ioctl .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c :functions: i915_perf_release +.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c + :functions: i915_perf_add_config_ioctl +.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c + :functions: i915_perf_remove_config_ioctl i915 Perf Stream ---------------- diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 214555e813f1..cc25115c2db7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2729,6 +2729,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), }; static struct drm_driver driver = { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 32749425d7bf..39ac2dd49ac9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1935,6 +1935,8 @@ struct i915_oa_config { struct attribute_group sysfs_metric; struct attribute *attrs[2]; struct device_attribute sysfs_metric_id; + + atomic_t ref_count; }; struct i915_perf_stream; @@ -2060,6 +2062,25 @@ struct i915_perf_stream { * struct i915_oa_ops - Gen specific implementation of an OA unit stream */ struct i915_oa_ops { + /** + * @is_valid_b_counter_reg: Validates register's address for + * programming boolean counters for a particular platform. + */ + bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, + u32 addr); + + /** + * @is_valid_mux_reg: Validates register's address for programming mux + * for a particular platform. + */ + bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); + + /** + * @is_valid_flex_reg: Validates register's address for programming + * flex EU filtering for a particular platform. + */ + bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); + /** * @init_oa_buffer: Resets the head and tail pointers of the * circular buffer for periodic OA reports. @@ -2444,10 +2465,32 @@ struct drm_i915_private { struct kobject *metrics_kobj; struct ctl_table_header *sysctl_header; + /* + * Lock associated with adding/modifying/removing OA configs + * in dev_priv->perf.metrics_idr. + */ + struct mutex metrics_lock; + + /* + * List of dynamic configurations, you need to hold + * dev_priv->perf.metrics_lock to access it. + */ + struct idr metrics_idr; + + /* + * Lock associated with anything below within this structure + * except exclusive_stream. + */ struct mutex lock; struct list_head streams; struct { + /* + * The stream currently using the OA unit. If accessed + * outside a syscall associated to its file + * descriptor, you need to hold + * dev_priv->drm.struct_mutex. + */ struct i915_perf_stream *exclusive_stream; u32 specific_ctx_id; @@ -3637,6 +3680,10 @@ i915_gem_context_lookup_timeline(struct i915_gem_context *ctx, int i915_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct i915_gem_context *ctx, uint32_t *reg_state); diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 06a5e1e83e6c..221a996f1985 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -193,6 +193,7 @@ #include #include +#include #include "i915_drv.h" #include "i915_oa_hsw.h" @@ -357,6 +358,54 @@ struct perf_open_properties { int oa_period_exponent; }; +static void free_oa_config(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + if (!PTR_ERR(oa_config->flex_regs)) + kfree(oa_config->flex_regs); + if (!PTR_ERR(oa_config->b_counter_regs)) + kfree(oa_config->b_counter_regs); + if (!PTR_ERR(oa_config->mux_regs)) + kfree(oa_config->mux_regs); + kfree(oa_config); +} + +static void put_oa_config(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + if (!atomic_dec_and_test(&oa_config->ref_count)) + return; + + free_oa_config(dev_priv, oa_config); +} + +static int get_oa_config(struct drm_i915_private *dev_priv, + int metrics_set, + struct i915_oa_config **out_config) +{ + int ret; + + if (metrics_set == 1) { + *out_config = &dev_priv->perf.oa.test_config; + atomic_inc(&dev_priv->perf.oa.test_config.ref_count); + return 0; + } + + ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (ret) + return ret; + + *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set); + if (!*out_config) + ret = -EINVAL; + else + atomic_inc(&(*out_config)->ref_count); + + mutex_unlock(&dev_priv->perf.metrics_lock); + + return ret; +} + static u32 gen8_oa_hw_tail_read(struct drm_i915_private *dev_priv) { return I915_READ(GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK; @@ -1246,8 +1295,8 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) BUG_ON(stream != dev_priv->perf.oa.exclusive_stream); /* - * Unset exclusive_stream first, it might be checked while - * disabling the metric set on gen8+. + * Unset exclusive_stream first, it will be checked while disabling + * the metric set on gen8+. */ mutex_lock(&dev_priv->drm.struct_mutex); dev_priv->perf.oa.exclusive_stream = NULL; @@ -1263,6 +1312,8 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) if (stream->ctx) oa_put_render_ctx_id(stream); + put_oa_config(dev_priv, stream->oa_config); + if (dev_priv->perf.oa.spurious_report_rs.missed) { DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n", dev_priv->perf.oa.spurious_report_rs.missed); @@ -1950,15 +2001,6 @@ static const struct i915_perf_stream_ops i915_oa_stream_ops = { .read = i915_oa_read, }; -static struct i915_oa_config *get_oa_config(struct drm_i915_private *dev_priv, - int metrics_set) -{ - if (metrics_set == 1) - return &dev_priv->perf.oa.test_config; - - return NULL; -} - /** * i915_oa_stream_init - validate combined props for OA stream and init * @stream: An i915 perf stream @@ -2062,9 +2104,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, return ret; } - stream->oa_config = get_oa_config(dev_priv, props->metrics_set); - if (!stream->oa_config) - return -EINVAL; + ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config); + if (ret) + goto err_config; /* PRM - observability performance counters: * @@ -2112,8 +2154,12 @@ err_enable: free_oa_buffer(dev_priv); err_oa_buf_alloc: + put_oa_config(dev_priv, stream->oa_config); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); intel_runtime_pm_put(dev_priv); + +err_config: if (stream->ctx) oa_put_render_ctx_id(stream); @@ -2127,6 +2173,8 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct drm_i915_private *dev_priv = engine->i915; struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream; + lockdep_assert_held(&dev_priv->drm.struct_mutex); + if (engine->id != RCS) return; @@ -2894,6 +2942,9 @@ void i915_perf_register(struct drm_i915_private *dev_priv) &dev_priv->perf.oa.test_config.sysfs_metric); if (ret) goto sysfs_error; + + atomic_set(&dev_priv->perf.oa.test_config.ref_count, 1); + goto exit; sysfs_error: @@ -2925,6 +2976,367 @@ void i915_perf_unregister(struct drm_i915_private *dev_priv) dev_priv->perf.metrics_kobj = NULL; } +static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + static const i915_reg_t flex_eu_regs[] = { + EU_PERF_CNTL0, + EU_PERF_CNTL1, + EU_PERF_CNTL2, + EU_PERF_CNTL3, + EU_PERF_CNTL4, + EU_PERF_CNTL5, + EU_PERF_CNTL6, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) { + if (flex_eu_regs[i].reg == addr) + return true; + } + return false; +} + +static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return (addr >= OASTARTTRIG1.reg && addr <= OASTARTTRIG8.reg) || + (addr >= OAREPORTTRIG1.reg && addr <= OAREPORTTRIG8.reg) || + (addr >= OACEC0_0.reg && addr <= OACEC7_1.reg); +} + +static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return addr == HALF_SLICE_CHICKEN2.reg || + (addr >= MICRO_BP0_0.reg && addr <= NOA_WRITE.reg) || + (addr >= OA_PERFCNT1_LO.reg && addr <= OA_PERFCNT2_HI.reg) || + (addr >= OA_PERFMATRIX_LO.reg && addr <= OA_PERFMATRIX_HI.reg); +} + +static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + addr == WAIT_FOR_RC6_EXIT.reg || + (addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg); +} + +static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + (addr >= 0x25100 && addr <= 0x2FF90) || + addr == 0x9ec0; +} + +static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + (addr >= 0x182300 && addr <= 0x1823A4); +} + +static uint32_t mask_reg_value(u32 reg, u32 val) +{ + /* HALF_SLICE_CHICKEN2 is programmed with a the + * WaDisableSTUnitPowerOptimization workaround. Make sure the value + * programmed by userspace doesn't change this. + */ + if (HALF_SLICE_CHICKEN2.reg == reg) + val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); + + /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function + * indicated by its name and a bunch of selection fields used by OA + * configs. + */ + if (WAIT_FOR_RC6_EXIT.reg == reg) + val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); + + return val; +} + +static struct i915_oa_reg *alloc_oa_regs(struct drm_i915_private *dev_priv, + bool (*is_valid)(struct drm_i915_private *dev_priv, u32 addr), + u32 __user *regs, + u32 n_regs) +{ + struct i915_oa_reg *oa_regs; + int err; + u32 i; + + if (!n_regs) + return NULL; + + if (!access_ok(VERIFY_READ, regs, n_regs * sizeof(u32) * 2)) + return ERR_PTR(-EFAULT); + + /* No is_valid function means we're not allowing any register to be programmed. */ + GEM_BUG_ON(!is_valid); + if (!is_valid) + return ERR_PTR(-EINVAL); + + oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL); + if (!oa_regs) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < n_regs; i++) { + u32 addr, value; + + err = get_user(addr, regs); + if (err) + goto addr_err; + + if (!is_valid(dev_priv, addr)) { + DRM_DEBUG("Invalid oa_reg address: %X\n", addr); + err = -EINVAL; + goto addr_err; + } + + err = get_user(value, regs + 1); + if (err) + goto addr_err; + + oa_regs[i].addr = _MMIO(addr); + oa_regs[i].value = mask_reg_value(addr, value); + + regs += 2; + } + + return oa_regs; + +addr_err: + kfree(oa_regs); + return ERR_PTR(err); +} + +static ssize_t show_dynamic_id(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i915_oa_config *oa_config = + container_of(attr, typeof(*oa_config), sysfs_metric_id); + + return sprintf(buf, "%d\n", oa_config->id); +} + +static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + oa_config->sysfs_metric_id.attr.name = "id"; + oa_config->sysfs_metric_id.attr.mode = S_IRUGO; + oa_config->sysfs_metric_id.show = show_dynamic_id; + oa_config->sysfs_metric_id.store = NULL; + + oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr; + oa_config->attrs[1] = NULL; + + oa_config->sysfs_metric.name = oa_config->uuid; + oa_config->sysfs_metric.attrs = oa_config->attrs; + + return sysfs_create_group(dev_priv->perf.metrics_kobj, + &oa_config->sysfs_metric); +} + +/** + * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config + * @dev: drm device + * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from + * userspace (unvalidated) + * @file: drm file + * + * Validates the submitted OA register to be saved into a new OA config that + * can then be used for programming the OA unit and its NOA network. + * + * Returns: A new allocated config number to be used with the perf open ioctl + * or a negative error code on failure. + */ +int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_perf_oa_config *args = data; + struct i915_oa_config *oa_config, *tmp; + int err, id; + + if (!dev_priv->perf.initialized) { + DRM_DEBUG("i915 perf interface not available for this system\n"); + return -ENOTSUPP; + } + + if (!dev_priv->perf.metrics_kobj) { + DRM_DEBUG("OA metrics weren't advertised via sysfs\n"); + return -EINVAL; + } + + if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { + DRM_DEBUG("Insufficient privileges to add i915 OA config\n"); + return -EACCES; + } + + if ((!args->mux_regs_ptr || !args->n_mux_regs) && + (!args->boolean_regs_ptr || !args->n_boolean_regs) && + (!args->flex_regs_ptr || !args->n_flex_regs)) { + DRM_DEBUG("No OA registers given\n"); + return -EINVAL; + } + + oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL); + if (!oa_config) { + DRM_DEBUG("Failed to allocate memory for the OA config\n"); + return -ENOMEM; + } + + atomic_set(&oa_config->ref_count, 1); + + if (!uuid_is_valid(args->uuid)) { + DRM_DEBUG("Invalid uuid format for OA config\n"); + err = -EINVAL; + goto reg_err; + } + + /* Last character in oa_config->uuid will be 0 because oa_config is + * kzalloc. + */ + memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid)); + + oa_config->mux_regs_len = args->n_mux_regs; + oa_config->mux_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_mux_reg, + u64_to_user_ptr(args->mux_regs_ptr), + args->n_mux_regs); + + if (IS_ERR(oa_config->mux_regs)) { + DRM_DEBUG("Failed to create OA config for mux_regs\n"); + err = PTR_ERR(oa_config->mux_regs); + goto reg_err; + } + + oa_config->b_counter_regs_len = args->n_boolean_regs; + oa_config->b_counter_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_b_counter_reg, + u64_to_user_ptr(args->boolean_regs_ptr), + args->n_boolean_regs); + + if (IS_ERR(oa_config->b_counter_regs)) { + DRM_DEBUG("Failed to create OA config for b_counter_regs\n"); + err = PTR_ERR(oa_config->b_counter_regs); + goto reg_err; + } + + if (INTEL_GEN(dev_priv) < 8) { + if (args->n_flex_regs != 0) { + err = -EINVAL; + goto reg_err; + } + } else { + oa_config->flex_regs_len = args->n_flex_regs; + oa_config->flex_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_flex_reg, + u64_to_user_ptr(args->flex_regs_ptr), + args->n_flex_regs); + + if (IS_ERR(oa_config->flex_regs)) { + DRM_DEBUG("Failed to create OA config for flex_regs\n"); + err = PTR_ERR(oa_config->flex_regs); + goto reg_err; + } + } + + err = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (err) + goto reg_err; + + /* We shouldn't have too many configs, so this iteration shouldn't be + * too costly. + */ + idr_for_each_entry(&dev_priv->perf.metrics_idr, tmp, id) { + if (!strcmp(tmp->uuid, oa_config->uuid)) { + DRM_DEBUG("OA config already exists with this uuid\n"); + err = -EADDRINUSE; + goto sysfs_err; + } + } + + err = create_dynamic_oa_sysfs_entry(dev_priv, oa_config); + if (err) { + DRM_DEBUG("Failed to create sysfs entry for OA config\n"); + goto sysfs_err; + } + + /* Config id 0 is invalid, id 1 for kernel stored test config. */ + oa_config->id = idr_alloc(&dev_priv->perf.metrics_idr, + oa_config, 2, + 0, GFP_KERNEL); + if (oa_config->id < 0) { + DRM_DEBUG("Failed to create sysfs entry for OA config\n"); + err = oa_config->id; + goto sysfs_err; + } + + mutex_unlock(&dev_priv->perf.metrics_lock); + + return oa_config->id; + +sysfs_err: + mutex_unlock(&dev_priv->perf.metrics_lock); +reg_err: + put_oa_config(dev_priv, oa_config); + DRM_DEBUG("Failed to add new OA config\n"); + return err; +} + +/** + * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config + * @dev: drm device + * @data: ioctl data (pointer to u64 integer) copied from userspace + * @file: drm file + * + * Configs can be removed while being used, the will stop appearing in sysfs + * and their content will be freed when the stream using the config is closed. + * + * Returns: 0 on success or a negative error code on failure. + */ +int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u64 *arg = data; + struct i915_oa_config *oa_config; + int ret; + + if (!dev_priv->perf.initialized) { + DRM_DEBUG("i915 perf interface not available for this system\n"); + return -ENOTSUPP; + } + + if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { + DRM_DEBUG("Insufficient privileges to remove i915 OA config\n"); + return -EACCES; + } + + ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (ret) + goto lock_err; + + oa_config = idr_find(&dev_priv->perf.metrics_idr, *arg); + if (!oa_config) { + DRM_DEBUG("Failed to remove unknown OA config\n"); + ret = -ENOENT; + goto config_err; + } + + GEM_BUG_ON(*arg != oa_config->id); + + sysfs_remove_group(dev_priv->perf.metrics_kobj, + &oa_config->sysfs_metric); + + idr_remove(&dev_priv->perf.metrics_idr, *arg); + put_oa_config(dev_priv, oa_config); + +config_err: + mutex_unlock(&dev_priv->perf.metrics_lock); +lock_err: + return ret; +} + static struct ctl_table oa_table[] = { { .procname = "perf_stream_paranoid", @@ -2981,6 +3393,11 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 0; if (IS_HASWELL(dev_priv)) { + dev_priv->perf.oa.ops.is_valid_b_counter_reg = + gen7_is_valid_b_counter_addr; + dev_priv->perf.oa.ops.is_valid_mux_reg = + hsw_is_valid_mux_addr; + dev_priv->perf.oa.ops.is_valid_flex_reg = NULL; dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer; dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set; dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set; @@ -3000,6 +3417,12 @@ void i915_perf_init(struct drm_i915_private *dev_priv) * worth the complexity to maintain now that BDW+ enable * execlist mode by default. */ + dev_priv->perf.oa.ops.is_valid_b_counter_reg = + gen7_is_valid_b_counter_addr; + dev_priv->perf.oa.ops.is_valid_mux_reg = + gen8_is_valid_mux_addr; + dev_priv->perf.oa.ops.is_valid_flex_reg = + gen8_is_valid_flex_addr; dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; @@ -3018,6 +3441,10 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 12500000; dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25); + if (IS_CHERRYVIEW(dev_priv)) { + dev_priv->perf.oa.ops.is_valid_mux_reg = + chv_is_valid_mux_addr; + } } else if (IS_GEN9(dev_priv)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; @@ -3056,10 +3483,23 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency / 2; dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); + mutex_init(&dev_priv->perf.metrics_lock); + idr_init(&dev_priv->perf.metrics_idr); + dev_priv->perf.initialized = true; } } +static int destroy_config(int id, void *p, void *data) +{ + struct drm_i915_private *dev_priv = data; + struct i915_oa_config *oa_config = p; + + put_oa_config(dev_priv, oa_config); + + return 0; +} + /** * i915_perf_fini - Counter part to i915_perf_init() * @dev_priv: i915 device instance @@ -3069,6 +3509,9 @@ void i915_perf_fini(struct drm_i915_private *dev_priv) if (!dev_priv->perf.initialized) return; + idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, dev_priv); + idr_destroy(&dev_priv->perf.metrics_idr); + unregister_sysctl_table(dev_priv->perf.sysctl_header); memset(&dev_priv->perf.oa.ops, 0, sizeof(dev_priv->perf.oa.ops)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0a42b6071ea1..b2546ade2c45 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -229,6 +229,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN8_RPCS_EU_MIN_SHIFT 0 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) +#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) +/* HSW only */ +#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 +#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) +#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) +/* HSW+ */ +#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) +#define HSW_RCS_CONTEXT_ENABLE (1 << 7) +#define HSW_RCS_INHIBIT (1 << 8) +/* Gen8 */ +#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) +#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) +#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) +#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 +#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) +#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 +#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) +#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) + #define GAM_ECOCHK _MMIO(0x4090) #define BDW_DISABLE_HDC_INVALIDATION (1<<25) #define ECOCHK_SNB_BIT (1<<10) @@ -729,9 +751,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define EU_PERF_CNTL5 _MMIO(0xe55c) #define EU_PERF_CNTL6 _MMIO(0xe65c) -#define GDT_CHICKEN_BITS _MMIO(0x9840) -#define GT_NOA_ENABLE 0x00000080 - /* * OA Boolean state */ @@ -994,6 +1013,51 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OACEC7_0 _MMIO(0x27a8) #define OACEC7_1 _MMIO(0x27ac) +/* OA perf counters */ +#define OA_PERFCNT1_LO _MMIO(0x91B8) +#define OA_PERFCNT1_HI _MMIO(0x91BC) +#define OA_PERFCNT2_LO _MMIO(0x91C0) +#define OA_PERFCNT2_HI _MMIO(0x91C4) + +#define OA_PERFMATRIX_LO _MMIO(0x91C8) +#define OA_PERFMATRIX_HI _MMIO(0x91CC) + +/* RPM unit config (Gen8+) */ +#define RPM_CONFIG0 _MMIO(0x0D00) +#define RPM_CONFIG1 _MMIO(0x0D04) + +/* RPC unit config (Gen8+) */ +#define RPM_CONFIG _MMIO(0x0D08) + +/* NOA (Gen8+) */ +#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) + +#define MICRO_BP0_0 _MMIO(0x9800) +#define MICRO_BP0_2 _MMIO(0x9804) +#define MICRO_BP0_1 _MMIO(0x9808) + +#define MICRO_BP1_0 _MMIO(0x980C) +#define MICRO_BP1_2 _MMIO(0x9810) +#define MICRO_BP1_1 _MMIO(0x9814) + +#define MICRO_BP2_0 _MMIO(0x9818) +#define MICRO_BP2_2 _MMIO(0x981C) +#define MICRO_BP2_1 _MMIO(0x9820) + +#define MICRO_BP3_0 _MMIO(0x9824) +#define MICRO_BP3_2 _MMIO(0x9828) +#define MICRO_BP3_1 _MMIO(0x982C) + +#define MICRO_BP_TRIGGER _MMIO(0x9830) +#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) +#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) +#define MICRO_BP_FIRED_ARMED _MMIO(0x983C) + +#define GDT_CHICKEN_BITS _MMIO(0x9840) +#define GT_NOA_ENABLE 0x00000080 + +#define NOA_DATA _MMIO(0x986C) +#define NOA_WRITE _MMIO(0x9888) #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7ccbd6a2bbe0..ce3833fa1e06 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -260,6 +260,8 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 #define DRM_I915_PERF_OPEN 0x36 +#define DRM_I915_PERF_ADD_CONFIG 0x37 +#define DRM_I915_PERF_REMOVE_CONFIG 0x38 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -315,6 +317,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) +#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) +#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -1467,6 +1471,22 @@ enum drm_i915_perf_record_type { DRM_I915_PERF_RECORD_MAX /* non-ABI */ }; +/** + * Structure to upload perf dynamic configuration into the kernel. + */ +struct drm_i915_perf_oa_config { + /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ + char uuid[36]; + + __u32 n_mux_regs; + __u32 n_boolean_regs; + __u32 n_flex_regs; + + __u64 __user mux_regs_ptr; + __u64 __user boolean_regs_ptr; + __u64 __user flex_regs_ptr; +}; + #if defined(__cplusplus) } #endif From 23247d715d3cf679cac24d1c4de2d76774a2a495 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Mon, 31 Jul 2017 11:52:20 -0700 Subject: [PATCH 097/179] drm/i915: Fix PCH names for KBP and CNP. No functional change. KBP was based on SPT and spec wasn't clear about the full name. There was the initial point of the "Point" confusion. Later the split with Coffee Lake and Cannon Lake both using CNP and also some uncertainty from the specs we had at that time made us to propagated the mistake along. So, let's fix this now and avoid propagating these wrong "points". Cc: Anusha Srivatsa Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Anusha Srivatsa Link: https://patchwork.freedesktop.org/patch/msgid/20170731185220.758-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 6 +++--- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index cc25115c2db7..ba15844cbafc 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -237,17 +237,17 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv) !IS_KABYLAKE(dev_priv)); } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_KBP; - DRM_DEBUG_KMS("Found KabyPoint PCH\n"); + DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n"); WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_CNP; - DRM_DEBUG_KMS("Found CannonPoint PCH\n"); + DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n"); WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_CNP; - DRM_DEBUG_KMS("Found CannonPoint LP PCH\n"); + DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n"); WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 39ac2dd49ac9..907603cba447 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1166,8 +1166,8 @@ enum intel_pch { PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ PCH_SPT, /* Sunrisepoint PCH */ - PCH_KBP, /* Kabypoint PCH */ - PCH_CNP, /* Cannonpoint PCH */ + PCH_KBP, /* Kaby Lake PCH */ + PCH_CNP, /* Cannon Lake PCH */ PCH_NOP, }; From 32087d1425887e2d51e8c77ff9849d73f6384457 Mon Sep 17 00:00:00 2001 From: Praveen Paneri Date: Thu, 3 Aug 2017 23:02:10 +0530 Subject: [PATCH 098/179] drm/i915: enable WaDisableDopClkGating for skl This WA is required when decoupled frequencies for slice and unslice are enabled. This disables DOP clock gating for skl. v2: enable the WA for all gen9 platforms (not just for SKL GT4 where the hang issue is originally reported) to avoid rare hangs (David) v3: as per WaDatabase, enable it only for SKL (Rodrigo) Cc: David Weinehall Reviewed-by: David Weinehall Signed-off-by: Praveen Paneri Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1501781530-8186-1-git-send-email-praveen.paneri@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8711c1f04079..6e393b217450 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | ILK_DPFC_DISABLE_DUMMY0); + + if (IS_SKYLAKE(dev_priv)) { + /* WaDisableDopClockGating */ + I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) + & ~GEN7_DOP_CLOCK_GATE_ENABLE); + } } static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) From 28152a238bb60d2577b9d4e7172a83bf4c1bf047 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 3 Aug 2017 23:37:00 +0100 Subject: [PATCH 099/179] drm/i915/perf: Initialise the dynamic sysfs attr Use sysfs_attr_init() to dynamically initialise the oa_config->sysfs_metric_id.attr as it has the important side-effect of setting the lockdep key. [ 4.971513] [drm] Initialized i915 1.6.0 20170731 for 0000:00:02.0 on minor 0 [ 4.973489] BUG: key ffff88026f6e7bb0 not in .data! [ 4.973506] DEBUG_LOCKS_WARN_ON(1) [ 4.973518] ------------[ cut here ]------------ [ 4.973547] WARNING: CPU: 1 PID: 258 at kernel/locking/lockdep.c:3156 lockdep_init_map+0x1b2/0x1c0 [ 4.973567] Modules linked in: i915(+) x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel snd_hda_intel snd_hda_codec snd_hwdep snd_hda_core snd_pcm r8169 mei_me mii mei lpc_ich prime_numbers i2c_hid pinctrl_broxton pinctrl_intel [ 4.973645] CPU: 1 PID: 258 Comm: systemd-udevd Not tainted 4.13.0-rc3-CI-CI_DRM_2915+ #1 [ 4.973664] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./J4205-ITX, BIOS P1.10 09/29/2016 [ 4.973686] task: ffff8802704c2740 task.stack: ffffc90000224000 [ 4.973700] RIP: 0010:lockdep_init_map+0x1b2/0x1c0 [ 4.973712] RSP: 0018:ffffc90000227a10 EFLAGS: 00010282 [ 4.973726] RAX: 0000000000000016 RBX: ffff880262aac010 RCX: 0000000000000000 [ 4.973741] RDX: 0000000080000001 RSI: 0000000000000001 RDI: ffffffff810ed1ab [ 4.973757] RBP: ffffc90000227a30 R08: 0000000000000001 R09: 0000000000000000 [ 4.973774] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88026f6e7bb0 [ 4.973789] R13: 0000000000000000 R14: ffff88026f6e7b98 R15: ffffffff81a24da0 [ 4.973805] FS: 00007f588d7f58c0(0000) GS:ffff88027fc80000(0000) knlGS:0000000000000000 [ 4.973823] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 4.973837] CR2: 00000082482e32a0 CR3: 0000000270531000 CR4: 00000000003406e0 [ 4.973852] Call Trace: [ 4.973864] __kernfs_create_file+0x71/0xe0 [ 4.973876] sysfs_add_file_mode_ns+0x85/0x1a0 [ 4.973890] internal_create_group+0xe5/0x2b0 [ 4.973903] sysfs_create_group+0xe/0x10 [ 4.973985] i915_perf_register+0xd9/0x220 [i915] [ 4.974044] i915_driver_load+0xa72/0x16b0 [i915] [ 4.974124] i915_pci_probe+0x32/0x90 [i915] Annoyingly detected by CI, but not reported due to it occurring during boot and disabling lockdep for later runs. Fixes: f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface") Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Lionel Landwerlin Cc: Andrzej Datczuk Link: https://patchwork.freedesktop.org/patch/msgid/20170803223700.10329-1-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 221a996f1985..e3e2663117e9 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3117,6 +3117,7 @@ static ssize_t show_dynamic_id(struct device *dev, static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv, struct i915_oa_config *oa_config) { + sysfs_attr_init(&oa_config->sysfs_metric_id.attr); oa_config->sysfs_metric_id.attr.name = "id"; oa_config->sysfs_metric_id.attr.mode = S_IRUGO; oa_config->sysfs_metric_id.show = show_dynamic_id; From 6cb0c6ad9e07f2c7971c4e8e0d9b7ceba151a925 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 4 Aug 2017 11:41:35 +0100 Subject: [PATCH 100/179] drm/i915/shrinker: Wrap need_resched() inside preempt-disable In order for us to successfully detect the end of a timeslice, preemption must be disabled. Otherwise, inside the loop we may be preempted many times without our noticing, and each time our timeslice will be reset, invalidating need_resched() Reported-by: Joonas Lahtinen Reported-by: Tomi Sarvela Fixes: 290271de34f6 ("drm/i915: Spin for struct_mutex inside shrinker") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: # v4.13-rc1+ Link: https://patchwork.freedesktop.org/patch/msgid/20170804104135.26805-1-chris@chris-wilson.co.uk Tested-by: Joonas Lahtinen Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_shrinker.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index 1032f98add11..77fb39808131 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -43,16 +43,21 @@ static bool shrinker_lock(struct drm_i915_private *dev_priv, bool *unlock) return true; case MUTEX_TRYLOCK_FAILED: + *unlock = false; + preempt_disable(); do { cpu_relax(); if (mutex_trylock(&dev_priv->drm.struct_mutex)) { - case MUTEX_TRYLOCK_SUCCESS: *unlock = true; - return true; + break; } } while (!need_resched()); + preempt_enable(); + return *unlock; - return false; + case MUTEX_TRYLOCK_SUCCESS: + *unlock = true; + return true; } BUG(); From e9d7486eac949f2a8d121657e536c8abdd4ea088 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 31 May 2017 11:33:55 +0300 Subject: [PATCH 101/179] drm/i915: fix backlight invert for non-zero minimum brightness When we started following the backlight minimum brightness in 6dda730e55f4 ("drm/i915: respect the VBT minimum backlight brightness") we overlooked the brightness invert quirk. Even if we invert the brightness, we need to take the min limit into account. We probably missed this because the invert has only been required on gen4 for proper operation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101127 Fixes: 6dda730e55f4 ("drm/i915: respect the VBT minimum backlight brightness") Cc: Daniel Vetter Reviewed-by: Daniel Vetter Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20170531083355.7898-1-jani.nikula@intel.com --- drivers/gpu/drm/i915/intel_panel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index fd2e0815f06a..88018fccdb9f 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -470,7 +470,7 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector, if (i915.invert_brightness > 0 || dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { - return panel->backlight.max - val; + return panel->backlight.max - val + panel->backlight.min; } return val; From 41533940a96296acb4595a1a58db70f8ea8f14da Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 28 Jul 2017 12:21:10 +0100 Subject: [PATCH 102/179] drm/i915/selftests: Retarget igt_render_engine_reset_fallback() The purpose of the test was to check per-engine resets would fallback to the global reset when required, but first we actually need a test for a basic i915_handle_error()! Cc: Mika Kuoppala Cc: Michel Thierry Signed-off-by: Chris Wilson Reviewed-by: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170728112110.6464-1-chris@chris-wilson.co.uk --- .../gpu/drm/i915/selftests/intel_hangcheck.c | 78 +++++-------------- 1 file changed, 19 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 7c55a4c7f4c9..208b34e864fb 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -770,22 +770,20 @@ unlock: return err; } -static int igt_render_engine_reset_fallback(void *arg) +static int igt_handle_error(void *arg) { struct drm_i915_private *i915 = arg; struct intel_engine_cs *engine = i915->engine[RCS]; struct hang h; struct drm_i915_gem_request *rq; - unsigned int reset_count, reset_engine_count; - int err = 0; + struct i915_gpu_state *error; + int err; /* Check that we can issue a global GPU and engine reset */ if (!intel_has_reset_engine(i915)) return 0; - global_reset_lock(i915); - mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); @@ -801,77 +799,39 @@ static int igt_render_engine_reset_fallback(void *arg) i915_gem_request_get(rq); __i915_add_request(rq, true); - /* make reset engine fail */ - rq->fence.error = -EIO; - if (!wait_for_hang(&h, rq)) { pr_err("Failed to start request %x\n", rq->fence.seqno); err = -EIO; goto err_request; } - reset_engine_count = i915_reset_engine_count(&i915->gpu_error, engine); - reset_count = fake_hangcheck(rq); - - /* unlock since we'll call handle_error */ mutex_unlock(&i915->drm.struct_mutex); - global_reset_unlock(i915); - i915_handle_error(i915, intel_engine_flag(engine), "live test"); + /* Temporarily disable error capture */ + error = xchg(&i915->gpu_error.first_error, (void *)-1); - if (i915_reset_engine_count(&i915->gpu_error, engine) != - reset_engine_count) { - pr_err("render engine reset recorded! (full reset expected)\n"); + engine->hangcheck.stalled = true; + engine->hangcheck.seqno = intel_engine_get_seqno(engine); + + i915_handle_error(i915, intel_engine_flag(engine), "%s", __func__); + + xchg(&i915->gpu_error.first_error, error); + + mutex_lock(&i915->drm.struct_mutex); + + if (rq->fence.error != -EIO) { + pr_err("Guilty request not identified!\n"); err = -EINVAL; - goto out_rq; + goto err_request; } - if (i915_reset_count(&i915->gpu_error) == reset_count) { - pr_err("No full GPU reset recorded!\n"); - err = -EINVAL; - goto out_rq; - } - - /* - * by using fence.error = -EIO, full reset sets the wedged flag, do one - * more full reset to re-enable the hw. - */ - if (i915_terminally_wedged(&i915->gpu_error)) { - global_reset_lock(i915); - rq->fence.error = 0; - - mutex_lock(&i915->drm.struct_mutex); - set_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags); - i915_reset(i915, I915_RESET_QUIET); - GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, - &i915->gpu_error.flags)); - mutex_unlock(&i915->drm.struct_mutex); - - if (i915_reset_count(&i915->gpu_error) == reset_count) { - pr_err("No full GPU reset recorded!\n"); - err = -EINVAL; - goto out_rq; - } - } - -out_rq: - i915_gem_request_put(rq); - hang_fini(&h); -out_backoff: - global_reset_unlock(i915); - - if (i915_terminally_wedged(&i915->gpu_error)) - return -EIO; - - return err; - err_request: i915_gem_request_put(rq); err_fini: hang_fini(&h); err_unlock: mutex_unlock(&i915->drm.struct_mutex); - goto out_backoff; + return err; } int intel_hangcheck_live_selftests(struct drm_i915_private *i915) @@ -883,7 +843,7 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) SUBTEST(igt_reset_active_engines), SUBTEST(igt_wait_reset), SUBTEST(igt_reset_queue), - SUBTEST(igt_render_engine_reset_fallback), + SUBTEST(igt_handle_error), }; if (!intel_has_gpu_reset(i915)) From fe29133df37ac31de9e657ad91bcf74cdfe8c4cd Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Fri, 4 Aug 2017 15:03:48 +0100 Subject: [PATCH 103/179] drm/i915: remove unused function declaration This function is not part of the driver anymore. Signed-off-by: Lionel Landwerlin Fixes: 90f4fcd56bda ("drm/i915: Remove forced stop ring on suspend/unload") Reviewed-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170804140348.24971-1-lionel.g.landwerlin@intel.com --- drivers/gpu/drm/i915/intel_lrc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 52b3a1fd4059..57ef5833c427 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -63,7 +63,6 @@ enum { }; /* Logical Rings */ -void intel_logical_ring_stop(struct intel_engine_cs *engine); void intel_logical_ring_cleanup(struct intel_engine_cs *engine); int logical_render_ring_init(struct intel_engine_cs *engine); int logical_xcs_ring_init(struct intel_engine_cs *engine); From 802673d66f8a6ded5d2689d597853c7bb3a70163 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 8 Aug 2017 14:19:04 +0100 Subject: [PATCH 104/179] drm/i915: Perform an invalidate prior to executing golden renderstate As we may have just bound the renderstate into the GGTT for execution, we need to ensure that the GTT TLB are also flushed. On snb-gt2, this would cause a random GPU hang at the start of a new context (e.g. boot) and on snb-gt1, it was causing the renderstate batch to take ~10s. It was the GPU hang that revealed the truth, as the CS gleefully executed beyond the end of the golden renderstate batch, a good indicator for a GTT TLB miss. Fixes: 20fe17aa52dc ("drm/i915: Remove redundant TLB invalidate on switching contexts") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: stable@vger.kernel.org Link: https://patchwork.freedesktop.org/patch/msgid/20170808131904.1385-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala Cc: # v4.12-rc1+ --- drivers/gpu/drm/i915/i915_gem_render_state.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 7032c542a9b1..4dd4c2159a92 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *req) goto err_unpin; } + ret = req->engine->emit_flush(req, EMIT_INVALIDATE); + if (ret) + goto err_unpin; + ret = req->engine->emit_bb_start(req, so->batch_offset, so->batch_size, I915_DISPATCH_SECURE); From ea46708f079d031f9e356b71a493940fd13fc2cf Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Tue, 8 Aug 2017 12:32:37 -0700 Subject: [PATCH 105/179] drm/i915/cnl: Removing missing DDI_E bits from CNL. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DDI_E is not supported on CNL-U and CNL-Y When adding the initial support we noticed DDI_E wasn't supported and removed it on v4 and v5 of that patch. However for some reason I missed or put back these 2 chunks. Time to clean it up to avoid later confusion. Fixes: 8bcd3dd41766 ("drm/i915/cnl: Add power wells for CNL") Cc: Clint Taylor Cc: Ville Syrjälä Cc: Imre Deak Cc: Daniel Vetter Cc: Jani Nikula Signed-off-by: Rodrigo Vivi Reviewed-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20170808193237.17410-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 347484ed6d2c..e77e84a6fd2f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1796,7 +1796,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ BIT_ULL(POWER_DOMAIN_AUX_D) | \ @@ -1805,7 +1804,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_INIT)) #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ BIT_ULL(POWER_DOMAIN_INIT)) #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ From 912d64123d354dd2e4ced479e1d93e74ea4c99a8 Mon Sep 17 00:00:00 2001 From: Jim Bride Date: Tue, 8 Aug 2017 14:51:34 -0700 Subject: [PATCH 106/179] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Bit 29 of SRD_CTL needs to have its value preserved according to the B-Spec, so right before we write out the register we go ahead and read the register and preserve the value of that bit before we write out the configured register value. v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo) Cc: Rodrigo Vivi Cc: Chris Wilson Cc: Jani Nikula Signed-off-by: Jim Bride Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1502229094-13392-1-git-send-email-jim.bride@linux.intel.com --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2546ade2c45..56df86ef5a4d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3872,6 +3872,7 @@ enum { #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) #define EDP_PSR_ENABLE (1<<31) #define BDW_PSR_SINGLE_FRAME (1<<30) +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */ #define EDP_PSR_LINK_STANDBY (1<<27) #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 559f1ab42bfc..1b31ab002dae 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TP2_SEL; + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; I915_WRITE(EDP_PSR_CTL, val); } From 4cf196eb1ecb8b74c05fcd89266a70506ed4c5a6 Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong Date: Tue, 13 Jun 2017 14:31:58 +0800 Subject: [PATCH 107/179] drm/i915/gvt: Use gvt_err to print the resource not enough error It is better to use gvt_err when the gvt resource is not enough so the user can be notified from the kernel dmesg. And this kind of error message is gvt related. Suggested-by: Bing Niu Signed-off-by: Chuanxiao Dong Cc: Bing Niu Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/aperture_gm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c index 325618d969fe..ca3d1925beda 100644 --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c @@ -285,8 +285,8 @@ static int alloc_resource(struct intel_vgpu *vgpu, return 0; no_enough_resource: - gvt_vgpu_err("fail to allocate resource %s\n", item); - gvt_vgpu_err("request %luMB avail %luMB max %luMB taken %luMB\n", + gvt_err("fail to allocate resource %s\n", item); + gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n", BYTES_TO_MB(request), BYTES_TO_MB(avail), BYTES_TO_MB(max), BYTES_TO_MB(taken)); return -ENOSPC; From f846c8de64ced9965e04cc9ae1922036175e395b Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Fri, 23 Jun 2017 15:45:31 +0800 Subject: [PATCH 108/179] drm/i915/gvt: Optimize ring siwtch 2x faster by removing unnecessary POSTING_READ There are lots of POSTING_READ alongside each mmio write Op. While actually this is not necessary. It just bring too much latency since PCIe read Op is very slow which is of non-posted transaction. For PCIe device, the mem transaction for strong ordering rules are: o PCIe mmio write sequence is FIFO. Posted request cannot pass previous posted request. o PCIe mmio read will not go ahead of previous write. Intel graphics doesn't support RO, so we can apply above rules. In our case, we only need one POSTING_READ at last. This can remove half of mmio read Op and then the average ring switch performance is nearly doubled. Before After cycles ~970000 ~550000 Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/render.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 504e57c3bc23..5a08bcd436a1 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -209,7 +209,6 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) for (i = 0; i < 64; i++) { gen9_render_mocs[ring_id][i] = I915_READ(offset); I915_WRITE(offset, vgpu_vreg(vgpu, offset)); - POSTING_READ(offset); offset.reg += 4; } @@ -218,7 +217,6 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) for (i = 0; i < 32; i++) { gen9_render_mocs_L3[i] = I915_READ(l3_offset); I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset)); - POSTING_READ(l3_offset); l3_offset.reg += 4; } } @@ -244,7 +242,6 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) for (i = 0; i < 64; i++) { vgpu_vreg(vgpu, offset) = I915_READ(offset); I915_WRITE(offset, gen9_render_mocs[ring_id][i]); - POSTING_READ(offset); offset.reg += 4; } @@ -253,7 +250,6 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) for (i = 0; i < 32; i++) { vgpu_vreg(vgpu, l3_offset) = I915_READ(l3_offset); I915_WRITE(l3_offset, gen9_render_mocs_L3[i]); - POSTING_READ(l3_offset); l3_offset.reg += 4; } } @@ -272,6 +268,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL]; u32 inhibit_mask = _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); + i915_reg_t last_reg = _MMIO(0); if (IS_SKYLAKE(vgpu->gvt->dev_priv) || IS_KABYLAKE(vgpu->gvt->dev_priv)) { @@ -305,12 +302,17 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) v = vgpu_vreg(vgpu, mmio->reg); I915_WRITE(mmio->reg, v); - POSTING_READ(mmio->reg); + last_reg = mmio->reg; trace_render_mmio(vgpu->id, "load", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } + + /* Make sure the swiched MMIOs has taken effect. */ + if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + POSTING_READ(last_reg); + handle_tlb_pending_event(vgpu, ring_id); } @@ -319,6 +321,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; struct render_mmio *mmio; + i915_reg_t last_reg = _MMIO(0); u32 v; int i, array_size; @@ -347,12 +350,16 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) continue; I915_WRITE(mmio->reg, v); - POSTING_READ(mmio->reg); + last_reg = mmio->reg; trace_render_mmio(vgpu->id, "restore", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } + + /* Make sure the swiched MMIOs has taken effect. */ + if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + POSTING_READ(last_reg); } /** From 4671ea204179dc705d4b0c31045e6acdfd6e59e8 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Fri, 23 Jun 2017 15:45:32 +0800 Subject: [PATCH 109/179] drm/i915/gvt: Optimize ring siwtch 2x faster again by light weight mmio access wrapper The I915_READ/WRITE is not only a mmio read/write, it also contains debug checking and Forcewake domain lookup. This is too heavy for GVT ring switch case which access batch of mmio registers on ring switch. We can handle Forcewake manually and use the raw i915_read/write instead. The benefit from this is 2x faster mmio switch performance. Before After cycles ~550000 ~250000 v2: Use existing I915_READ_FW/I915_WRITE_FW macro. (zhenyu) Signed-off-by: Changbin Du Reviewed-by: Zhenyu Wang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/render.c | 39 ++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 5a08bcd436a1..2ea542257f03 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -207,7 +207,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { - gen9_render_mocs[ring_id][i] = I915_READ(offset); + gen9_render_mocs[ring_id][i] = I915_READ_FW(offset); I915_WRITE(offset, vgpu_vreg(vgpu, offset)); offset.reg += 4; } @@ -215,8 +215,8 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) if (ring_id == RCS) { l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { - gen9_render_mocs_L3[i] = I915_READ(l3_offset); - I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset)); + gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset); + I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset)); l3_offset.reg += 4; } } @@ -240,16 +240,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { - vgpu_vreg(vgpu, offset) = I915_READ(offset); - I915_WRITE(offset, gen9_render_mocs[ring_id][i]); + vgpu_vreg(vgpu, offset) = I915_READ_FW(offset); + I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]); offset.reg += 4; } if (ring_id == RCS) { l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { - vgpu_vreg(vgpu, l3_offset) = I915_READ(l3_offset); - I915_WRITE(l3_offset, gen9_render_mocs_L3[i]); + vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset); + I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]); l3_offset.reg += 4; } } @@ -284,7 +284,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) if (mmio->ring_id != ring_id) continue; - mmio->value = I915_READ(mmio->reg); + mmio->value = I915_READ_FW(mmio->reg); /* * if it is an inhibit context, load in_context mmio @@ -301,7 +301,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) else v = vgpu_vreg(vgpu, mmio->reg); - I915_WRITE(mmio->reg, v); + I915_WRITE_FW(mmio->reg, v); last_reg = mmio->reg; trace_render_mmio(vgpu->id, "load", @@ -311,7 +311,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) /* Make sure the swiched MMIOs has taken effect. */ if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) - POSTING_READ(last_reg); + I915_READ_FW(last_reg); handle_tlb_pending_event(vgpu, ring_id); } @@ -338,7 +338,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) if (mmio->ring_id != ring_id) continue; - vgpu_vreg(vgpu, mmio->reg) = I915_READ(mmio->reg); + vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg); if (mmio->mask) { vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16); @@ -349,7 +349,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) if (mmio->in_context) continue; - I915_WRITE(mmio->reg, v); + I915_WRITE_FW(mmio->reg, v); last_reg = mmio->reg; trace_render_mmio(vgpu->id, "restore", @@ -359,7 +359,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) /* Make sure the swiched MMIOs has taken effect. */ if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) - POSTING_READ(last_reg); + I915_READ_FW(last_reg); } /** @@ -374,12 +374,23 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) void intel_gvt_switch_mmio(struct intel_vgpu *pre, struct intel_vgpu *next, int ring_id) { + struct drm_i915_private *dev_priv; + if (WARN_ON(!pre && !next)) return; gvt_dbg_render("switch ring %d from %s to %s\n", ring_id, pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); + dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; + + /** + * We are using raw mmio access wrapper to improve the + * performace for batch mmio read/write, so we need + * handle forcewake mannually. + */ + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + /** * TODO: Optimize for vGPU to vGPU switch by merging * switch_mmio_to_host() and switch_mmio_to_vgpu(). @@ -389,4 +400,6 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, if (next) switch_mmio_to_vgpu(next, ring_id); + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } From 89ea20b930cb7372095645acae8928a75f7d5be5 Mon Sep 17 00:00:00 2001 From: Ping Gao Date: Thu, 29 Jun 2017 12:22:42 +0800 Subject: [PATCH 110/179] drm/i915/gvt: Factor out scan and shadow from workload dispatch To perform the workload scan and shadow in ELSP writing stage for performance consideration, the workload scan and shadow stuffs should be factored out from dispatch_workload(). v2:Put context pin before i915_add_request; Refine the comments; Rename some APIs; v3:workload->status should set only when error happens. v4:i915_add_request is must to have after i915_gem_request_alloc. Signed-off-by: Ping Gao Reviewed-by: Zhi Wang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- drivers/gpu/drm/i915/gvt/cmd_parser.h | 2 +- drivers/gpu/drm/i915/gvt/gvt.h | 2 + drivers/gpu/drm/i915/gvt/scheduler.c | 83 ++++++++++++++++----------- 4 files changed, 54 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 713848c36349..7ed8c551a5a1 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -2647,7 +2647,7 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) return 0; } -int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) +int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) { int ret; struct intel_vgpu *vgpu = workload->vgpu; diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.h b/drivers/gpu/drm/i915/gvt/cmd_parser.h index bed33514103c..286703643002 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.h +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.h @@ -42,7 +42,7 @@ void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt); int intel_gvt_init_cmd_parser(struct intel_gvt *gvt); -int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); +int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload); int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx); diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 3a74e79eac2f..ba53ad17900b 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -470,6 +470,8 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); void populate_pvinfo_page(struct intel_vgpu *vgpu); +int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); + struct intel_gvt_ops { int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, unsigned int); diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 0e2e36ad6196..7929c0285d1d 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -184,42 +184,27 @@ static int shadow_context_status_change(struct notifier_block *nb, return NOTIFY_OK; } -static int dispatch_workload(struct intel_vgpu_workload *workload) +/** + * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and + * shadow it as well, include ringbuffer,wa_ctx and ctx. + * @workload: an abstract entity for each execlist submission. + * + * This function is called before the workload submitting to i915, to make + * sure the content of the workload is valid. + */ +int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) { int ring_id = workload->ring_id; struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; - struct intel_engine_cs *engine = dev_priv->engine[ring_id]; struct drm_i915_gem_request *rq; struct intel_vgpu *vgpu = workload->vgpu; - struct intel_ring *ring; int ret; - gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", - ring_id, workload); - shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; - mutex_lock(&dev_priv->drm.struct_mutex); - - /* pin shadow context by gvt even the shadow context will be pinned - * when i915 alloc request. That is because gvt will update the guest - * context from shadow context when workload is completed, and at that - * moment, i915 may already unpined the shadow context to make the - * shadow_ctx pages invalid. So gvt need to pin itself. After update - * the guest context, gvt can unpin the shadow_ctx safely. - */ - ring = engine->context_pin(engine, shadow_ctx); - if (IS_ERR(ring)) { - ret = PTR_ERR(ring); - gvt_vgpu_err("fail to pin shadow context\n"); - workload->status = ret; - mutex_unlock(&dev_priv->drm.struct_mutex); - return ret; - } - rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); if (IS_ERR(rq)) { gvt_vgpu_err("fail to allocate gem request\n"); @@ -231,7 +216,7 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) workload->req = i915_gem_request_get(rq); - ret = intel_gvt_scan_and_shadow_workload(workload); + ret = intel_gvt_scan_and_shadow_ringbuffer(workload); if (ret) goto out; @@ -243,6 +228,27 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) } ret = populate_shadow_context(workload); + +out: + return ret; +} + +static int dispatch_workload(struct intel_vgpu_workload *workload) +{ + int ring_id = workload->ring_id; + struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; + struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; + struct intel_engine_cs *engine = dev_priv->engine[ring_id]; + struct intel_vgpu *vgpu = workload->vgpu; + struct intel_ring *ring; + int ret = 0; + + gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", + ring_id, workload); + + mutex_lock(&dev_priv->drm.struct_mutex); + + ret = intel_gvt_scan_and_shadow_workload(workload); if (ret) goto out; @@ -252,19 +258,30 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) goto out; } - gvt_dbg_sched("ring id %d submit workload to i915 %p\n", - ring_id, workload->req); + /* pin shadow context by gvt even the shadow context will be pinned + * when i915 alloc request. That is because gvt will update the guest + * context from shadow context when workload is completed, and at that + * moment, i915 may already unpined the shadow context to make the + * shadow_ctx pages invalid. So gvt need to pin itself. After update + * the guest context, gvt can unpin the shadow_ctx safely. + */ + ring = engine->context_pin(engine, shadow_ctx); + if (IS_ERR(ring)) { + ret = PTR_ERR(ring); + gvt_vgpu_err("fail to pin shadow context\n"); + goto out; + } - ret = 0; - workload->dispatched = true; out: if (ret) workload->status = ret; - if (!IS_ERR_OR_NULL(rq)) - i915_add_request(rq); - else - engine->context_unpin(engine, shadow_ctx); + if (!IS_ERR_OR_NULL(workload->req)) { + gvt_dbg_sched("ring id %d submit workload to i915 %p\n", + ring_id, workload->req); + i915_add_request(workload->req); + workload->dispatched = true; + } mutex_unlock(&dev_priv->drm.struct_mutex); return ret; From d0302e74003bf1f0fc41c06948b745204c4704ea Mon Sep 17 00:00:00 2001 From: Ping Gao Date: Thu, 29 Jun 2017 12:22:43 +0800 Subject: [PATCH 111/179] drm/i915/gvt: Audit and shadow workload during ELSP writing Let the workload audit and shadow ahead of vGPU scheduling, that will eliminate GPU idle time and improve performance for multi-VM. The performance of Heaven running simultaneously in 3VMs has improved 20% after this patch. v2:Remove condition current->vgpu==vgpu when shadow during ELSP writing. Signed-off-by: Ping Gao Reviewed-by: Zhi Wang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/execlist.c | 11 +++++++++++ drivers/gpu/drm/i915/gvt/scheduler.c | 7 +++++++ drivers/gpu/drm/i915/gvt/scheduler.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index 700050556242..28a2c7e8bee1 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -605,6 +605,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, struct list_head *q = workload_q_head(vgpu, ring_id); struct intel_vgpu_workload *last_workload = get_last_workload(q); struct intel_vgpu_workload *workload = NULL; + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; u64 ring_context_gpa; u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; int ret; @@ -668,6 +669,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, workload->complete = complete_execlist_workload; workload->status = -EINPROGRESS; workload->emulate_schedule_in = emulate_schedule_in; + workload->shadowed = false; if (ring_id == RCS) { intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + @@ -701,6 +703,15 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, return ret; } + /* Only scan and shadow the first workload in the queue + * as there is only one pre-allocated buf-obj for shadow. + */ + if (list_empty(workload_q_head(vgpu, ring_id))) { + mutex_lock(&dev_priv->drm.struct_mutex); + intel_gvt_scan_and_shadow_workload(workload); + mutex_unlock(&dev_priv->drm.struct_mutex); + } + queue_workload(workload); return 0; } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 7929c0285d1d..bd59c6d09319 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -201,6 +201,9 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) struct intel_vgpu *vgpu = workload->vgpu; int ret; + if (workload->shadowed) + return 0; + shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; @@ -228,6 +231,10 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) } ret = populate_shadow_context(workload); + if (ret) + goto out; + + workload->shadowed = true; out: return ret; diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h index 9b6bf51e9b9b..0d431a968a32 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.h +++ b/drivers/gpu/drm/i915/gvt/scheduler.h @@ -82,6 +82,7 @@ struct intel_vgpu_workload { struct drm_i915_gem_request *req; /* if this workload has been dispatched to i915? */ bool dispatched; + bool shadowed; int status; struct intel_vgpu_mm *shadow_mm; From 87e919d741f9bf07f8aad6f096c6ebc3345a9856 Mon Sep 17 00:00:00 2001 From: Ping Gao Date: Tue, 4 Jul 2017 14:53:03 +0800 Subject: [PATCH 112/179] drm/i915/gvt: To check whether workload scan and shadow has mutex hold The function workload scan and shadow have to hold the drm.struct_mutex before called. To avoid misusing of this function, add a lockdep assert in it. Signed-off-by: Ping Gao Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/scheduler.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index bd59c6d09319..ca1926d564c9 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -201,6 +201,8 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) struct intel_vgpu *vgpu = workload->vgpu; int ret; + lockdep_assert_held(&dev_priv->drm.struct_mutex); + if (workload->shadowed) return 0; From 64d8bb83b61d3fcb0babaa88c4e8b423e7d2721e Mon Sep 17 00:00:00 2001 From: Ping Gao Date: Tue, 4 Jul 2017 16:11:16 +0800 Subject: [PATCH 113/179] drm/i915/gvt: Replace duplicated code with exist function Use the exist function intel_gvt_ggtt_validate_range to replace these duplicated code that do the same thing. Signed-off-by: Ping Gao Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 7ed8c551a5a1..72b97ce525e8 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1382,13 +1382,13 @@ static inline int cmd_address_audit(struct parser_exec_state *s, ret = -EINVAL; goto err; } - } else if ((!vgpu_gmadr_is_valid(s->vgpu, guest_gma)) || - (!vgpu_gmadr_is_valid(s->vgpu, - guest_gma + op_size - 1))) { + } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) { ret = -EINVAL; goto err; } + return 0; + err: gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", s->info->name, guest_gma, op_size); From 73821a53d081de30368262198793e891fbd7318d Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Mon, 10 Jul 2017 14:13:12 +0800 Subject: [PATCH 114/179] drm/i915/gvt: take runtime pm when do early scan and shadow Need to take runtime pm when do early scan/shadow of workload for request operations. Fixes: 7fa56bd159bc ("drm/i915/gvt: Audit and shadow workload during ELSP writing") Cc: Ping Gao Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/execlist.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index 28a2c7e8bee1..33808657988a 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -707,9 +707,11 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, * as there is only one pre-allocated buf-obj for shadow. */ if (list_empty(workload_q_head(vgpu, ring_id))) { + intel_runtime_pm_get(dev_priv); mutex_lock(&dev_priv->drm.struct_mutex); intel_gvt_scan_and_shadow_workload(workload); mutex_unlock(&dev_priv->drm.struct_mutex); + intel_runtime_pm_put(dev_priv); } queue_workload(workload); From 36ed7e97e260e9b7abf30121b3f58f2c83bf35c1 Mon Sep 17 00:00:00 2001 From: Jian Jun Chen Date: Wed, 19 Jul 2017 12:18:39 +0800 Subject: [PATCH 115/179] drm/i915/gvt: Remove duplicated MMIO entries Remove duplicated MMIO entries in the tracked MMIO list. -EEXIST is returned if duplicated MMIO entries are found when new MMIO entry is added. v2: - Use WARN(1, ...) for more verbose message. (Zhenyu) Signed-off-by: Jian Jun Chen Cc: Zhi Wang Cc: Changbin Du Cc: Zhenyu Wang Reviewed-by: Yulei Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/handlers.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index aeecf315c5db..d85264d48585 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -113,9 +113,17 @@ static int new_mmio_info(struct intel_gvt *gvt, info->offset = i; p = find_mmio_info(gvt, info->offset); - if (p) - gvt_err("dup mmio definition offset %x\n", + if (p) { + WARN(1, "dup mmio definition offset %x\n", info->offset); + kfree(info); + + /* We return -EEXIST here to make GVT-g load fail. + * So duplicated MMIO can be found as soon as + * possible. + */ + return -EEXIST; + } info->ro_mask = ro_mask; info->device = device; @@ -2583,7 +2591,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, force_nonpriv_write); - MMIO_D(0x22040, D_BDW_PLUS); MMIO_D(0x44484, D_BDW_PLUS); MMIO_D(0x4448c, D_BDW_PLUS); @@ -2641,7 +2648,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS); MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL, skl_power_well_ctl_write); - MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write); MMIO_D(0xa210, D_SKL_PLUS); MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); @@ -2833,7 +2839,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(0x320f0, D_SKL | D_KBL); MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); - MMIO_DFH(_REG_VECS_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); MMIO_D(0x70034, D_SKL_PLUS); MMIO_D(0x71034, D_SKL_PLUS); MMIO_D(0x72034, D_SKL_PLUS); @@ -2851,10 +2856,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) NULL, NULL); MMIO_D(0x4ab8, D_KBL); - MMIO_D(0x940c, D_SKL_PLUS); MMIO_D(0x2248, D_SKL_PLUS | D_KBL); - MMIO_D(0x4ab0, D_SKL | D_KBL); - MMIO_D(0x20d4, D_SKL | D_KBL); return 0; } From 4b2dbbc22541e44e10e22836149050ab6dbd879e Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Wed, 2 Aug 2017 15:06:37 +0800 Subject: [PATCH 116/179] drm/i915/gvt: Add carefully checking in GTT walker paths When debugging the gtt code, found the intel_vgpu_gma_to_gpa() can translate any given GMA though the GMA is not valid. This because the GTT ops suppress the possible errors, which may result in an invalid PT entry is retrieved by upper caller. This patch changed the prototype of pte ops to propagate status to callers. Then we make sure the GTT walker stop as early as when a error is detected to prevent undefined behavior. Signed-off-by: Changbin Du Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/gtt.c | 77 ++++++++++++++++++++++------------ drivers/gpu/drm/i915/gvt/gtt.h | 24 ++++++----- 2 files changed, 64 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 6166e34d892b..e397f5e0722f 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -259,7 +259,7 @@ static void write_pte64(struct drm_i915_private *dev_priv, writeq(pte, addr); } -static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt, +static inline int gtt_get_entry64(void *pt, struct intel_gvt_gtt_entry *e, unsigned long index, bool hypervisor_access, unsigned long gpa, struct intel_vgpu *vgpu) @@ -268,22 +268,23 @@ static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt, int ret; if (WARN_ON(info->gtt_entry_size != 8)) - return e; + return -EINVAL; if (hypervisor_access) { ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa + (index << info->gtt_entry_size_shift), &e->val64, 8); - WARN_ON(ret); + if (WARN_ON(ret)) + return ret; } else if (!pt) { e->val64 = read_pte64(vgpu->gvt->dev_priv, index); } else { e->val64 = *((u64 *)pt + index); } - return e; + return 0; } -static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt, +static inline int gtt_set_entry64(void *pt, struct intel_gvt_gtt_entry *e, unsigned long index, bool hypervisor_access, unsigned long gpa, struct intel_vgpu *vgpu) @@ -292,19 +293,20 @@ static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt, int ret; if (WARN_ON(info->gtt_entry_size != 8)) - return e; + return -EINVAL; if (hypervisor_access) { ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa + (index << info->gtt_entry_size_shift), &e->val64, 8); - WARN_ON(ret); + if (WARN_ON(ret)) + return ret; } else if (!pt) { write_pte64(vgpu->gvt->dev_priv, index, e->val64); } else { *((u64 *)pt + index) = e->val64; } - return e; + return 0; } #define GTT_HAW 46 @@ -445,21 +447,25 @@ static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p, /* * MM helpers. */ -struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm, +int intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index) { struct intel_gvt *gvt = mm->vgpu->gvt; struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; + int ret; e->type = mm->page_table_entry_type; - ops->get_entry(page_table, e, index, false, 0, mm->vgpu); + ret = ops->get_entry(page_table, e, index, false, 0, mm->vgpu); + if (ret) + return ret; + ops->test_pse(e); - return e; + return 0; } -struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, +int intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index) { @@ -472,7 +478,7 @@ struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, /* * PPGTT shadow page table helpers. */ -static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry( +static inline int ppgtt_spt_get_entry( struct intel_vgpu_ppgtt_spt *spt, void *page_table, int type, struct intel_gvt_gtt_entry *e, unsigned long index, @@ -480,20 +486,24 @@ static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry( { struct intel_gvt *gvt = spt->vgpu->gvt; struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; + int ret; e->type = get_entry_type(type); if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) - return e; + return -EINVAL; - ops->get_entry(page_table, e, index, guest, + ret = ops->get_entry(page_table, e, index, guest, spt->guest_page.gfn << GTT_PAGE_SHIFT, spt->vgpu); + if (ret) + return ret; + ops->test_pse(e); - return e; + return 0; } -static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry( +static inline int ppgtt_spt_set_entry( struct intel_vgpu_ppgtt_spt *spt, void *page_table, int type, struct intel_gvt_gtt_entry *e, unsigned long index, @@ -503,7 +513,7 @@ static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry( struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) - return e; + return -EINVAL; return ops->set_entry(page_table, e, index, guest, spt->guest_page.gfn << GTT_PAGE_SHIFT, @@ -792,13 +802,13 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page( #define for_each_present_guest_entry(spt, e, i) \ for (i = 0; i < pt_entries(spt); i++) \ - if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ - ppgtt_get_guest_entry(spt, e, i))) + if (!ppgtt_get_guest_entry(spt, e, i) && \ + spt->vgpu->gvt->gtt.pte_ops->test_present(e)) #define for_each_present_shadow_entry(spt, e, i) \ for (i = 0; i < pt_entries(spt); i++) \ - if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ - ppgtt_get_shadow_entry(spt, e, i))) + if (!ppgtt_get_shadow_entry(spt, e, i) && \ + spt->vgpu->gvt->gtt.pte_ops->test_present(e)) static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt *spt) { @@ -1713,8 +1723,10 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) if (!vgpu_gmadr_is_valid(vgpu, gma)) goto err; - ggtt_get_guest_entry(mm, &e, - gma_ops->gma_to_ggtt_pte_index(gma)); + ret = ggtt_get_guest_entry(mm, &e, + gma_ops->gma_to_ggtt_pte_index(gma)); + if (ret) + goto err; gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) + (gma & ~GTT_PAGE_MASK); @@ -1724,7 +1736,9 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) switch (mm->page_table_level) { case 4: - ppgtt_get_shadow_root_entry(mm, &e, 0); + ret = ppgtt_get_shadow_root_entry(mm, &e, 0); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pml4_index(gma); gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma); gma_index[2] = gma_ops->gma_to_pde_index(gma); @@ -1732,15 +1746,19 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) index = 4; break; case 3: - ppgtt_get_shadow_root_entry(mm, &e, + ret = ppgtt_get_shadow_root_entry(mm, &e, gma_ops->gma_to_l3_pdp_index(gma)); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pde_index(gma); gma_index[1] = gma_ops->gma_to_pte_index(gma); index = 2; break; case 2: - ppgtt_get_shadow_root_entry(mm, &e, + ret = ppgtt_get_shadow_root_entry(mm, &e, gma_ops->gma_to_pde_index(gma)); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pte_index(gma); index = 1; break; @@ -1755,6 +1773,11 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) (i == index - 1)); if (ret) goto err; + + if (!pte_ops->test_present(&e)) { + gvt_dbg_core("GMA 0x%lx is not present\n", gma); + goto err; + } } gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index f88eb5e89bea..abb41ee1409b 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -49,14 +49,18 @@ struct intel_gvt_gtt_entry { }; struct intel_gvt_gtt_pte_ops { - struct intel_gvt_gtt_entry *(*get_entry)(void *pt, - struct intel_gvt_gtt_entry *e, - unsigned long index, bool hypervisor_access, unsigned long gpa, - struct intel_vgpu *vgpu); - struct intel_gvt_gtt_entry *(*set_entry)(void *pt, - struct intel_gvt_gtt_entry *e, - unsigned long index, bool hypervisor_access, unsigned long gpa, - struct intel_vgpu *vgpu); + int (*get_entry)(void *pt, + struct intel_gvt_gtt_entry *e, + unsigned long index, + bool hypervisor_access, + unsigned long gpa, + struct intel_vgpu *vgpu); + int (*set_entry)(void *pt, + struct intel_gvt_gtt_entry *e, + unsigned long index, + bool hypervisor_access, + unsigned long gpa, + struct intel_vgpu *vgpu); bool (*test_present)(struct intel_gvt_gtt_entry *e); void (*clear_present)(struct intel_gvt_gtt_entry *e); bool (*test_pse)(struct intel_gvt_gtt_entry *e); @@ -143,12 +147,12 @@ struct intel_vgpu_mm { struct intel_vgpu *vgpu; }; -extern struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry( +extern int intel_vgpu_mm_get_entry( struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index); -extern struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry( +extern int intel_vgpu_mm_set_entry( struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index); From 4d3e67bb6fa26e50eb087799d98ec232acfb630d Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong Date: Fri, 4 Aug 2017 13:08:59 +0800 Subject: [PATCH 117/179] drm/i915/gvt: Refine the intel_vgpu_reset_gtt reset function When doing the VGPU reset, we don't need to do the gtt/ppgtt reset. This will make the GVT to do the ppgtt shadow every time for a workload and caused really bad performance after a VGPU reset. This patch will make sure ppgtt clean only happen at device module level reset to fix this. Signed-off-by: Chuanxiao Dong Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/gtt.c | 6 +----- drivers/gpu/drm/i915/gvt/gtt.h | 2 +- drivers/gpu/drm/i915/gvt/vgpu.c | 6 +++--- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index e397f5e0722f..f862681c70d1 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -2352,13 +2352,12 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) /** * intel_vgpu_reset_gtt - reset the all GTT related status * @vgpu: a vGPU - * @dmlr: true for vGPU Device Model Level Reset, false for GT Reset * * This function is called from vfio core to reset reset all * GTT related status, including GGTT, PPGTT, scratch page. * */ -void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) +void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu) { int i; @@ -2370,9 +2369,6 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) */ intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_PPGTT); - if (!dmlr) - return; - intel_vgpu_reset_ggtt(vgpu); /* clear scratch page for security */ diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index abb41ee1409b..30a4c8d16026 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -212,7 +212,7 @@ extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu); extern int intel_gvt_init_gtt(struct intel_gvt *gvt); -extern void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr); +void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); extern void intel_gvt_clean_gtt(struct intel_gvt *gvt); extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 90c14e6e3ea0..5b44d123bf24 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -502,11 +502,11 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, /* full GPU reset or device model level reset */ if (engine_mask == ALL_ENGINES || dmlr) { - intel_vgpu_reset_gtt(vgpu, dmlr); - /*fence will not be reset during virtual reset */ - if (dmlr) + if (dmlr) { + intel_vgpu_reset_gtt(vgpu); intel_vgpu_reset_resource(vgpu); + } intel_vgpu_reset_mmio(vgpu, dmlr); populate_pvinfo_page(vgpu); From a45050d718f629104cfdfde0345dae617bdef3fc Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Tue, 1 Aug 2017 13:09:47 +0800 Subject: [PATCH 118/179] drm/i915/gvt: expose vGPU context hw id This exposes vGPU context hw id in mdev sysfs which is used to do vGPU based profiling. Retrieved vGPU context hw id can be set through i915 perf ioctl to set profiling for target vGPU. Cc: Jiao Pengyuan Cc: Niu Bing Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/kvmgt.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index fd0c85f9ef3c..83e88c70272a 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -1170,10 +1170,27 @@ vgpu_id_show(struct device *dev, struct device_attribute *attr, return sprintf(buf, "\n"); } +static ssize_t +hw_id_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mdev_device *mdev = mdev_from_dev(dev); + + if (mdev) { + struct intel_vgpu *vgpu = (struct intel_vgpu *) + mdev_get_drvdata(mdev); + return sprintf(buf, "%u\n", + vgpu->shadow_ctx->hw_id); + } + return sprintf(buf, "\n"); +} + static DEVICE_ATTR_RO(vgpu_id); +static DEVICE_ATTR_RO(hw_id); static struct attribute *intel_vgpu_attrs[] = { &dev_attr_vgpu_id.attr, + &dev_attr_hw_id.attr, NULL }; From 9dfb8e5b9112483530429c96d463e6d45e0106ed Mon Sep 17 00:00:00 2001 From: Kechen Lu Date: Thu, 10 Aug 2017 07:41:36 +0800 Subject: [PATCH 119/179] drm/i915/gvt: Add shadow context descriptor updating The current context logic only updates the descriptor of context when it's being pinned to graphics memory space. But this cannot satisfy the requirement of shadow context. The addressing mode of the pinned shadow context descriptor may be changed according to the guest addressing mode. And this won't be updated, as the already pinned shadow context has no chance to update its descriptor. And this will lead to GPU hang issue, as shadow context is used with wrong descriptor. This patch fixes this issue by letting the pinned shadow context descriptor update its addressing mode on demand. This patch fixes GPU HANG issue which happends after changing the grub parameter i915.enable_ppgtt form 0x01 to 0x03 or vice versa and then rebooting the guest. Signed-off-by: Tina Zhang Signed-off-by: Kechen Lu Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/execlist.c | 2 ++ drivers/gpu/drm/i915/gvt/gvt.h | 1 + drivers/gpu/drm/i915/gvt/scheduler.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index 33808657988a..df11f69edc05 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -796,6 +796,8 @@ static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask) list_del_init(&pos->list); free_workload(pos); } + + clear_bit(engine->id, vgpu->shadow_ctx_desc_updated); } } diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index ba53ad17900b..ea736717e051 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -167,6 +167,7 @@ struct intel_vgpu { atomic_t running_workload_num; DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); struct i915_gem_context *shadow_ctx; + DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) struct { diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index ca1926d564c9..025aba8a72e0 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -184,6 +184,23 @@ static int shadow_context_status_change(struct notifier_block *nb, return NOTIFY_OK; } +static void shadow_context_descriptor_update(struct i915_gem_context *ctx, + struct intel_engine_cs *engine) +{ + struct intel_context *ce = &ctx->engine[engine->id]; + u64 desc = 0; + + desc = ce->lrc_desc; + + /* Update bits 0-11 of the context descriptor which includes flags + * like GEN8_CTX_* cached in desc_template + */ + desc &= U64_MAX << 12; + desc |= ctx->desc_template & ((1ULL << 12) - 1); + + ce->lrc_desc = desc; +} + /** * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and * shadow it as well, include ringbuffer,wa_ctx and ctx. @@ -210,6 +227,10 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; + if (!test_and_set_bit(ring_id, vgpu->shadow_ctx_desc_updated)) + shadow_context_descriptor_update(shadow_ctx, + dev_priv->engine[ring_id]); + rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); if (IS_ERR(rq)) { gvt_vgpu_err("fail to allocate gem request\n"); @@ -656,5 +677,7 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu) vgpu->shadow_ctx->engine[RCS].initialised = true; + bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES); + return 0; } From 3ec0af7f223bab9503c4ed57d00ed34b137df476 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 9 Aug 2017 17:39:30 +0100 Subject: [PATCH 120/179] drm/i915: Supply the engine-id for our mock_engine() In the original selftest, we didn't care what the engine->id was, just that it could uniquely identify it. Later though, we started tracking the mock engines in the fixed size arrays around the drm_i915_private and so we now require their indices to be correct. This becomes an issue when using the standalone harness which runs all available tests at module load, and so we quickly assign an out-of-bounds index to an engine as we reallocate the mock GEM device between tests. It doesn't show up in igt/drv_selftest as that runs each subtest individually. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102045 Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170809163930.26470-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/selftests/mock_engine.c | 8 +++++--- drivers/gpu/drm/i915/selftests/mock_engine.h | 3 ++- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c index 5b18a2dc19a8..fc0fd7498689 100644 --- a/drivers/gpu/drm/i915/selftests/mock_engine.c +++ b/drivers/gpu/drm/i915/selftests/mock_engine.c @@ -123,10 +123,12 @@ static struct intel_ring *mock_ring(struct intel_engine_cs *engine) } struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, - const char *name) + const char *name, + int id) { struct mock_engine *engine; - static int id; + + GEM_BUG_ON(id >= I915_NUM_ENGINES); engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL); if (!engine) @@ -141,7 +143,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, /* minimal engine setup for requests */ engine->base.i915 = i915; snprintf(engine->base.name, sizeof(engine->base.name), "%s", name); - engine->base.id = id++; + engine->base.id = id; engine->base.status_page.page_addr = (void *)(engine + 1); engine->base.context_pin = mock_context_pin; diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.h b/drivers/gpu/drm/i915/selftests/mock_engine.h index e5e240216ba3..133d0c21790d 100644 --- a/drivers/gpu/drm/i915/selftests/mock_engine.h +++ b/drivers/gpu/drm/i915/selftests/mock_engine.h @@ -40,7 +40,8 @@ struct mock_engine { }; struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, - const char *name); + const char *name, + int id); void mock_engine_flush(struct intel_engine_cs *engine); void mock_engine_reset(struct intel_engine_cs *engine); void mock_engine_free(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index ec92b6569b50..678723430d78 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -226,7 +226,7 @@ struct drm_i915_private *mock_gem_device(void) mutex_unlock(&i915->drm.struct_mutex); mkwrite_device_info(i915)->ring_mask = BIT(0); - i915->engine[RCS] = mock_engine(i915, "mock"); + i915->engine[RCS] = mock_engine(i915, "mock", RCS); if (!i915->engine[RCS]) goto err_priorities; From bbfb6ce86c9889a5d434e2e603d41e0ce5b552e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Aug 2017 09:58:12 -0700 Subject: [PATCH 121/179] drm/i915: Implement .get_format_info() hook for CCS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are compressed and which are not. The location of CCS is provided by userspace as just another plane with its own offset. By providing our own format information for the CCS formats, we should be able to make framebuffer_check() do the right thing for the CCS surface as well. Note that we'll return the same format info for both Y and Yf tiled format as that's what happens with the non-CCS Y vs. Yf as well. If desired, we could potentially return a unique pointer for each pixel_format+tiling+ccs combination, in which case we immediately be able to tell if any of that stuff changed by just comparing the pointers. But that does sound a bit wasteful space wise. v2: Drop the 'dev' argument from the hook v3: Include the description of the CCS surface layout v4: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason) v5: Re-drop 'dev', fix commit message, add missing drm_fourcc.h description of CCS layout. (daniels) Cc: Daniel Vetter Cc: Ben Widawsky Cc: Jason Ekstrand Acked-by: Jason Ekstrand Reviewed-by: Ben Widawsky (v3) Reviewed-by: Daniel Stone Signed-off-by: Ville Syrjä Signed-off-by: Ben Widawsky Signed-off-by: Daniel Stone --- drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 20 ++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e4af56b5ff27..51035ec1fe62 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2428,6 +2428,41 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) } } +static const struct drm_format_info ccs_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, +}; + +static const struct drm_format_info * +lookup_format_info(const struct drm_format_info formats[], + int num_formats, u32 format) +{ + int i; + + for (i = 0; i < num_formats; i++) { + if (formats[i].format == format) + return &formats[i]; + } + + return NULL; +} + +static const struct drm_format_info * +intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + switch (cmd->modifier[0]) { + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + return lookup_format_info(ccs_formats, + ARRAY_SIZE(ccs_formats), + cmd->pixel_format); + default: + return NULL; + } +} + static int intel_fill_fb_info(struct drm_i915_private *dev_priv, struct drm_framebuffer *fb) @@ -13673,6 +13708,7 @@ static void intel_atomic_state_free(struct drm_atomic_state *state) static const struct drm_mode_config_funcs intel_mode_funcs = { .fb_create = intel_user_framebuffer_create, + .get_format_info = intel_get_format_info, .output_poll_changed = intel_fbdev_output_poll_changed, .atomic_check = intel_atomic_check, .atomic_commit = intel_atomic_commit, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 76c9101a7fc6..3ad838d3f93f 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -263,6 +263,26 @@ extern "C" { */ #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) +/* + * Intel color control surface (CCS) for render compression + * + * The framebuffer format must be one of the 8:8:8:8 RGB formats. + * The main surface will be plane index 0 and must be Y/Yf-tiled, + * the CCS will be plane index 1. + * + * Each CCS tile matches a 1024x512 pixel area of the main surface. + * To match certain aspects of the 3D hardware the CCS is + * considered to be made up of normal 128Bx32 Y tiles, Thus + * the CCS pitch must be specified in multiples of 128 bytes. + * + * In reality the CCS tile appears to be a 64Bx64 Y tile, composed + * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. + * But that fact is not relevant unless the memory is accessed + * directly. + */ +#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) +#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * From 2e2adb05736c3101a0b301e39bf5adabb8b5fb22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Aug 2017 09:58:13 -0700 Subject: [PATCH 122/179] drm/i915: Add render decompression support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are compressed and which are not. The location of CCS is provided by userspace as just another plane with its own offset. Add the required stuff to validate the user provided AUX plane metadata and convert the user provided linear offset into something the hardware can consume. Due to hardware limitations we require that the main surface and the AUX surface (CCS) be part of the same bo. The hardware also makes life hard by not allowing you to provide separate x/y offsets for the main and AUX surfaces (excpet with NV12), so finding suitable offsets for both requires a bit of work. Assuming we still want keep playing tricks with the offsets. I've just gone with a dumb "search backward for suitable offsets" approach, which is far from optimal, but it works. Also not all planes will be capable of scanning out compressed surfaces, and eg. 90/270 degree rotation is not supported in combination with decompression either. This patch may contain work from at least the following people: * Vandana Kannan * Daniel Vetter * Ben Widawsky v2: Deal with display workarounds 0390, 0531, 1125 (Paulo) v3: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason) Put the AUX register defines to the correct place Fix up the slightly bogus rotation check v4: Use I915_WRITE_FW() due to plane update locking changes s/return -EINVAL/goto err/ in intel_framebuffer_init() Eliminate a bunch hardcoded numbers in CCS code v5: (By Ben) conflict resolution + - res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum); + res_blocks += fixed16_to_u32_round_up(y_tile_minimum); v6: (daniels) Fix botched commit message. Cc: Paulo Zanoni Cc: Daniel Vetter Cc: Ben Widawsky Cc: Jason Ekstrand Signed-off-by: Ville Syrjä Reviewed-by: Ben Widawsky (v1) Reviewed-by: Daniel Stone Signed-off-by: Ben Widawsky Signed-off-by: Daniel Stone Link: http://patchwork.freedesktop.org/patch/msgid/20170801165817.7063-1-ben@bwidawsk.net --- drivers/gpu/drm/i915/i915_reg.h | 23 +++ drivers/gpu/drm/i915/intel_display.c | 233 +++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_pm.c | 29 +++- drivers/gpu/drm/i915/intel_sprite.c | 5 + 4 files changed, 272 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 56df86ef5a4d..067f8f30c0b8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6199,6 +6199,10 @@ enum { #define _PLANE_KEYMSK_2_A 0x70298 #define _PLANE_KEYMAX_1_A 0x701a0 #define _PLANE_KEYMAX_2_A 0x702a0 +#define _PLANE_AUX_DIST_1_A 0x701c0 +#define _PLANE_AUX_DIST_2_A 0x702c0 +#define _PLANE_AUX_OFFSET_1_A 0x701c4 +#define _PLANE_AUX_OFFSET_2_A 0x702c4 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ @@ -6305,6 +6309,24 @@ enum { #define PLANE_NV12_BUF_CFG(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +#define _PLANE_AUX_DIST_1_B 0x711c0 +#define _PLANE_AUX_DIST_2_B 0x712c0 +#define _PLANE_AUX_DIST_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) +#define _PLANE_AUX_DIST_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) +#define PLANE_AUX_DIST(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) + +#define _PLANE_AUX_OFFSET_1_B 0x711c4 +#define _PLANE_AUX_OFFSET_2_B 0x712c4 +#define _PLANE_AUX_OFFSET_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) +#define _PLANE_AUX_OFFSET_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) +#define PLANE_AUX_OFFSET(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) + #define _PLANE_COLOR_CTL_1_B 0x711CC #define _PLANE_COLOR_CTL_2_B 0x712CC #define _PLANE_COLOR_CTL_3_B 0x713CC @@ -6788,6 +6810,7 @@ enum { # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) #define CHICKEN_PAR1_1 _MMIO(0x42080) +#define SKL_RC_HASH_OUTSIDE (1 << 15) #define DPA_MASK_VBLANK_SRD (1 << 15) #define FORCE_ARB_IDLE_PLANES (1 << 14) #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 51035ec1fe62..0e334a2e9d4b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1994,11 +1994,19 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) return 128; else return 512; + case I915_FORMAT_MOD_Y_TILED_CCS: + if (plane == 1) + return 128; + /* fall through */ case I915_FORMAT_MOD_Y_TILED: if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) return 128; else return 512; + case I915_FORMAT_MOD_Yf_TILED_CCS: + if (plane == 1) + return 128; + /* fall through */ case I915_FORMAT_MOD_Yf_TILED: switch (cpp) { case 1: @@ -2105,7 +2113,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, struct drm_i915_private *dev_priv = to_i915(fb->dev); /* AUX_DIST needs only 4K alignment */ - if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) + if (plane == 1) return 4096; switch (fb->modifier) { @@ -2115,6 +2123,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, if (INTEL_GEN(dev_priv) >= 9) return 256 * 1024; return 0; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: return 1 * 1024 * 1024; @@ -2422,6 +2432,7 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) case I915_FORMAT_MOD_X_TILED: return I915_TILING_X; case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: return I915_TILING_Y; default: return I915_TILING_NONE; @@ -2486,6 +2497,36 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, intel_fb_offset_to_xy(&x, &y, fb, i); + if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int tile_width, tile_height; + int main_x, main_y; + int ccs_x, ccs_y; + + intel_tile_dims(fb, i, &tile_width, &tile_height); + + ccs_x = (x * hsub) % (tile_width * hsub); + ccs_y = (y * vsub) % (tile_height * vsub); + main_x = intel_fb->normal[0].x % (tile_width * hsub); + main_y = intel_fb->normal[0].y % (tile_height * vsub); + + /* + * CCS doesn't have its own x/y offset register, so the intra CCS tile + * x/y offsets must match between CCS and the main surface. + */ + if (main_x != ccs_x || main_y != ccs_y) { + DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", + main_x, main_y, + ccs_x, ccs_y, + intel_fb->normal[0].x, + intel_fb->normal[0].y, + x, y); + return -EINVAL; + } + } + /* * The fence (if used) is aligned to the start of the object * so having the framebuffer wrap around across the edge of the @@ -2846,6 +2887,9 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, break; } break; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + /* FIXME AUX plane? */ case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: switch (cpp) { @@ -2868,6 +2912,44 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, return 2048; } +static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, + int main_x, int main_y, u32 main_offset) +{ + const struct drm_framebuffer *fb = plane_state->base.fb; + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int aux_x = plane_state->aux.x; + int aux_y = plane_state->aux.y; + u32 aux_offset = plane_state->aux.offset; + u32 alignment = intel_surf_alignment(fb, 1); + + while (aux_offset >= main_offset && aux_y <= main_y) { + int x, y; + + if (aux_x == main_x && aux_y == main_y) + break; + + if (aux_offset == 0) + break; + + x = aux_x / hsub; + y = aux_y / vsub; + aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, + aux_offset, aux_offset - alignment); + aux_x = x * hsub + aux_x % hsub; + aux_y = y * vsub + aux_y % vsub; + } + + if (aux_x != main_x || aux_y != main_y) + return false; + + plane_state->aux.offset = aux_offset; + plane_state->aux.x = aux_x; + plane_state->aux.y = aux_y; + + return true; +} + static int skl_check_main_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->base.fb; @@ -2910,7 +2992,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) while ((x + w) * cpp > fb->pitches[0]) { if (offset == 0) { - DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); return -EINVAL; } @@ -2919,6 +3001,26 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) } } + /* + * CCS AUX surface doesn't have its own x/y offsets, we must make sure + * they match with the main surface x/y offsets. + */ + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { + while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { + if (offset == 0) + break; + + offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, + offset, offset - alignment); + } + + if (x != plane_state->aux.x || y != plane_state->aux.y) { + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); + return -EINVAL; + } + } + plane_state->main.offset = offset; plane_state->main.x = x; plane_state->main.y = y; @@ -2955,6 +3057,49 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) return 0; } +static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->base.plane); + struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); + const struct drm_framebuffer *fb = plane_state->base.fb; + int src_x = plane_state->base.src.x1 >> 16; + int src_y = plane_state->base.src.y1 >> 16; + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int x = src_x / hsub; + int y = src_y / vsub; + u32 offset; + + switch (plane->id) { + case PLANE_PRIMARY: + case PLANE_SPRITE0: + break; + default: + DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); + return -EINVAL; + } + + if (crtc->pipe == PIPE_C) { + DRM_DEBUG_KMS("No RC support on pipe C\n"); + return -EINVAL; + } + + if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { + DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", + plane_state->base.rotation); + return -EINVAL; + } + + intel_add_fb_offsets(&x, &y, plane_state, 1); + offset = intel_compute_tile_offset(&x, &y, plane_state, 1); + + plane_state->aux.offset = offset; + plane_state->aux.x = x * hsub + src_x % hsub; + plane_state->aux.y = y * vsub + src_y % vsub; + + return 0; +} + int skl_check_plane_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->base.fb; @@ -2978,6 +3123,11 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) ret = skl_check_nv12_aux_surface(plane_state); if (ret) return ret; + } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { + ret = skl_check_ccs_aux_surface(plane_state); + if (ret) + return ret; } else { plane_state->aux.offset = ~0xfff; plane_state->aux.x = 0; @@ -3284,8 +3434,12 @@ static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) return PLANE_CTL_TILED_X; case I915_FORMAT_MOD_Y_TILED: return PLANE_CTL_TILED_Y; + case I915_FORMAT_MOD_Y_TILED_CCS: + return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; case I915_FORMAT_MOD_Yf_TILED: return PLANE_CTL_TILED_YF; + case I915_FORMAT_MOD_Yf_TILED_CCS: + return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; default: MISSING_CASE(fb_modifier); } @@ -3358,6 +3512,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane, u32 plane_ctl = plane_state->ctl; unsigned int rotation = plane_state->base.rotation; u32 stride = skl_plane_stride(fb, 0, rotation); + u32 aux_stride = skl_plane_stride(fb, 1, rotation); u32 surf_addr = plane_state->main.offset; int scaler_id = plane_state->scaler_id; int src_x = plane_state->main.x; @@ -3394,6 +3549,10 @@ static void skylake_update_primary_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), + (plane_state->aux.offset - surf_addr) | aux_stride); + I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->aux.y << 16) | plane_state->aux.x); if (scaler_id >= 0) { uint32_t ps_ctrl = 0; @@ -8337,10 +8496,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, fb->modifier = I915_FORMAT_MOD_X_TILED; break; case PLANE_CTL_TILED_Y: - fb->modifier = I915_FORMAT_MOD_Y_TILED; + if (val & PLANE_CTL_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; + else + fb->modifier = I915_FORMAT_MOD_Y_TILED; break; case PLANE_CTL_TILED_YF: - fb->modifier = I915_FORMAT_MOD_Yf_TILED; + if (val & PLANE_CTL_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; + else + fb->modifier = I915_FORMAT_MOD_Yf_TILED; break; default: MISSING_CASE(tiling); @@ -13506,10 +13671,12 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + struct drm_framebuffer *fb = &intel_fb->base; struct drm_format_name_buf format_name; - u32 pitch_limit, stride_alignment; + u32 pitch_limit; unsigned int tiling, stride; int ret = -EINVAL; + int i; i915_gem_object_lock(obj); obj->framebuffer_references++; @@ -13538,6 +13705,19 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, /* Passed in modifier sanity checking. */ switch (mode_cmd->modifier[0]) { + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + switch (mode_cmd->pixel_format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + break; + default: + DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); + goto err; + } + /* fall through */ case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: if (INTEL_GEN(dev_priv) < 9) { @@ -13642,25 +13822,46 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, if (mode_cmd->offsets[0] != 0) goto err; - drm_helper_mode_fill_fb_struct(&dev_priv->drm, - &intel_fb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); - stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0); - if (mode_cmd->pitches[0] & (stride_alignment - 1)) { - DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n", - mode_cmd->pitches[0], stride_alignment); - goto err; + for (i = 0; i < fb->format->num_planes; i++) { + u32 stride_alignment; + + if (mode_cmd->handles[i] != mode_cmd->handles[0]) { + DRM_DEBUG_KMS("bad plane %d handle\n", i); + return -EINVAL; + } + + stride_alignment = intel_fb_stride_alignment(fb, i); + + /* + * Display WA #0531: skl,bxt,kbl,glk + * + * Render decompression and plane width > 3840 + * combined with horizontal panning requires the + * plane stride to be a multiple of 4. We'll just + * require the entire fb to accommodate that to avoid + * potential runtime errors at plane configuration time. + */ + if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) + stride_alignment *= 4; + + if (fb->pitches[i] & (stride_alignment - 1)) { + DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", + i, fb->pitches[i], stride_alignment); + goto err; + } } intel_fb->obj = obj; - ret = intel_fill_fb_info(dev_priv, &intel_fb->base); + ret = intel_fill_fb_info(dev_priv, fb); if (ret) goto err; - ret = drm_framebuffer_init(obj->base.dev, - &intel_fb->base, - &intel_fb_funcs); + ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); if (ret) { DRM_ERROR("framebuffer init failed %d\n", ret); goto err; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6e393b217450..4a75b673b85f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -62,6 +62,20 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(CHICKEN_PAR1_1, I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); + /* + * Display WA#0390: skl,bxt,kbl,glk + * + * Must match Sampler, Pixel Back End, and Media + * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31). + * + * Including bits outside the page in the hash would + * require 2 (or 4?) MiB alignment of resources. Just + * assume the defaul hashing mode which only uses bits + * within the page. + */ + I915_WRITE(CHICKEN_PAR1_1, + I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE); + I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); @@ -4077,7 +4091,9 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, /* For Non Y-tile return 8-blocks */ if (fb->modifier != I915_FORMAT_MOD_Y_TILED && - fb->modifier != I915_FORMAT_MOD_Yf_TILED) + fb->modifier != I915_FORMAT_MOD_Yf_TILED && + fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS && + fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS) return 8; /* @@ -4383,7 +4399,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, } y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED || - fb->modifier == I915_FORMAT_MOD_Yf_TILED; + fb->modifier == I915_FORMAT_MOD_Yf_TILED || + fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS; x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; /* Display WA #1141: kbl,cfl */ @@ -4478,6 +4496,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, res_lines = div_round_up_fixed16(selected_result, plane_blocks_per_line); + /* Display WA #1125: skl,bxt,kbl,glk */ + if (level == 0 && + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) + res_blocks += fixed16_to_u32_round_up(y_tile_minimum); + + /* Display WA #1126: skl,bxt,kbl,glk */ if (level >= 1 && level <= 7) { if (y_tiled) { res_blocks += fixed16_to_u32_round_up(y_tile_minimum); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 048a4cab5589..4bf0d3e4ad91 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -238,6 +238,7 @@ skl_update_plane(struct intel_plane *plane, u32 surf_addr = plane_state->main.offset; unsigned int rotation = plane_state->base.rotation; u32 stride = skl_plane_stride(fb, 0, rotation); + u32 aux_stride = skl_plane_stride(fb, 1, rotation); int crtc_x = plane_state->base.dst.x1; int crtc_y = plane_state->base.dst.y1; uint32_t crtc_w = drm_rect_width(&plane_state->base.dst); @@ -272,6 +273,10 @@ skl_update_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), + (plane_state->aux.offset - surf_addr) | aux_stride); + I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->aux.y << 16) | plane_state->aux.x); /* program plane scaler */ if (plane_state->scaler_id >= 0) { From 714244e280de0e4ec00ff18b641f48be3936d920 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Tue, 1 Aug 2017 09:58:16 -0700 Subject: [PATCH 123/179] drm/i915: Add format modifiers for Intel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was based on a patch originally by Kristian. It has been modified pretty heavily to use the new callbacks from the previous patch. v2: - Add LINEAR and Yf modifiers to list (Ville) - Combine i8xx and i965 into one list of formats (Ville) - Allow 1010102 formats for Y/Yf tiled (Ville) v3: - Handle cursor formats (Ville) - Put handling for LINEAR in the mod_support functions (Ville) v4: - List each modifier explicitly in supported modifiers (Ville) - Handle the CURSOR plane (Ville) v5: - Split out cursor and sprite handling (Ville) v6: - Actually use the sprite funcs (Emil) - Use unreachable (Emil) v7: - Only allow Intel modifiers and LINEAR (Ben) v8 - Fix spite assert introduced in v6 (Daniel) v9 - Change vendor check logic to avoid magic 56 (Emil) - Reorder skl_mod_support (Ville) - make intel_plane_funcs static, could be done as of v5 (Ville) - rename local variable intel_format_modifiers to modifiers (Ville) - actually use sprite modifiers - split out modifier/formats by platform (Ville) v10: - Undo vendor check from v9 v11: - Squash CCS advertisement into this patch (daniels) - Don't advertise CCS on higher sprite planes (daniels) v12: - Don't advertise Y-tiled or CCS on any sprite planes, since we don't allocate enough DDB space for it to work. (daniels) Cc: Ville Syrjälä Reviewed-by: Emil Velikov (v8) Signed-off-by: Ben Widawsky Signed-off-by: Daniel Stone --- drivers/gpu/drm/i915/intel_display.c | 153 +++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_drv.h | 1 - drivers/gpu/drm/i915/intel_sprite.c | 150 +++++++++++++++++++++++++- 3 files changed, 292 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0e334a2e9d4b..beff138e9b92 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -67,6 +67,12 @@ static const uint32_t i965_primary_formats[] = { DRM_FORMAT_XBGR2101010, }; +static const uint64_t i9xx_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint32_t skl_primary_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, @@ -82,11 +88,34 @@ static const uint32_t skl_primary_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_format_modifiers_noccs[] = { + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + +static const uint64_t skl_format_modifiers_ccs[] = { + I915_FORMAT_MOD_Yf_TILED_CCS, + I915_FORMAT_MOD_Y_TILED_CCS, + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + /* Cursor formats */ static const uint32_t intel_cursor_formats[] = { DRM_FORMAT_ARGB8888, }; +static const uint64_t cursor_format_modifiers[] = { + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static void i9xx_crtc_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); static void ironlake_pch_clock_get(struct intel_crtc *crtc, @@ -12839,7 +12868,102 @@ void intel_plane_destroy(struct drm_plane *plane) kfree(to_intel_plane(plane)); } -const struct drm_plane_funcs intel_plane_funcs = { +static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_C8: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_XRGB8888: + return modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED; + default: + return false; + } +} + +static bool i965_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_C8: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + return modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED; + default: + return false; + } +} + +static bool skl_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_CCS) + return true; + /* fall through */ + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == I915_FORMAT_MOD_Yf_TILED) + return true; + /* fall through */ + case DRM_FORMAT_C8: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED || + modifier == I915_FORMAT_MOD_Y_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && + modifier != DRM_FORMAT_MOD_LINEAR) + return false; + + if (INTEL_GEN(dev_priv) >= 9) + return skl_mod_supported(format, modifier); + else if (INTEL_GEN(dev_priv) >= 4) + return i965_mod_supported(format, modifier); + else + return i8xx_mod_supported(format, modifier); + + unreachable(); +} + +static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; +} + +static struct drm_plane_funcs intel_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = intel_plane_destroy, @@ -12847,6 +12971,7 @@ const struct drm_plane_funcs intel_plane_funcs = { .atomic_set_property = intel_plane_atomic_set_property, .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_primary_plane_format_mod_supported, }; static int @@ -12980,6 +13105,7 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = { .atomic_set_property = intel_plane_atomic_set_property, .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_cursor_plane_format_mod_supported, }; static struct intel_plane * @@ -12990,6 +13116,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) const uint32_t *intel_primary_formats; unsigned int supported_rotations; unsigned int num_formats; + const uint64_t *modifiers; int ret; primary = kzalloc(sizeof(*primary), GFP_KERNEL); @@ -13025,21 +13152,34 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); primary->check_plane = intel_check_primary_plane; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { intel_primary_formats = skl_primary_formats; num_formats = ARRAY_SIZE(skl_primary_formats); + modifiers = skl_format_modifiers_ccs; + + primary->update_plane = skylake_update_primary_plane; + primary->disable_plane = skylake_disable_primary_plane; + } else if (INTEL_GEN(dev_priv) >= 9) { + intel_primary_formats = skl_primary_formats; + num_formats = ARRAY_SIZE(skl_primary_formats); + if (pipe < PIPE_C) + modifiers = skl_format_modifiers_ccs; + else + modifiers = skl_format_modifiers_noccs; primary->update_plane = skylake_update_primary_plane; primary->disable_plane = skylake_disable_primary_plane; } else if (INTEL_GEN(dev_priv) >= 4) { intel_primary_formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); + modifiers = i9xx_format_modifiers; primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; } else { intel_primary_formats = i8xx_primary_formats; num_formats = ARRAY_SIZE(i8xx_primary_formats); + modifiers = i9xx_format_modifiers; primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; @@ -13049,21 +13189,21 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "plane 1%c", pipe_name(pipe)); else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "primary %c", pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "plane %c", plane_name(primary->plane)); if (ret) @@ -13149,7 +13289,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, 0, &intel_cursor_plane_funcs, intel_cursor_formats, ARRAY_SIZE(intel_cursor_formats), - NULL, DRM_PLANE_TYPE_CURSOR, + cursor_format_modifiers, + DRM_PLANE_TYPE_CURSOR, "cursor %c", pipe_name(pipe)); if (ret) goto fail; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f91de9cb9697..b1dd5d6ed0f3 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1316,7 +1316,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, const char *name, u32 reg); void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); void lpt_disable_iclkip(struct drm_i915_private *dev_priv); -extern const struct drm_plane_funcs intel_plane_funcs; void intel_init_display_hooks(struct drm_i915_private *dev_priv); unsigned int intel_fb_xy_to_linear(int x, int y, const struct intel_plane_state *state, diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 4bf0d3e4ad91..e11f8782c9eb 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -30,6 +30,7 @@ * support. */ #include +#include #include #include #include @@ -1037,6 +1038,12 @@ static const uint32_t g4x_plane_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t i9xx_plane_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint32_t snb_plane_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, @@ -1072,6 +1079,122 @@ static uint32_t skl_plane_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_plane_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + +static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + /* This is the same as primary plane since SKL has universal planes */ + switch (format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == I915_FORMAT_MOD_Yf_TILED) + return true; + /* fall through */ + case DRM_FORMAT_C8: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED || + modifier == I915_FORMAT_MOD_Y_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && + modifier != DRM_FORMAT_MOD_LINEAR) + return false; + + if (INTEL_GEN(dev_priv) >= 9) + return skl_sprite_plane_format_mod_supported(plane, format, modifier); + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + return vlv_sprite_plane_format_mod_supported(plane, format, modifier); + else + return g4x_sprite_plane_format_mod_supported(plane, format, modifier); + + unreachable(); +} + +const struct drm_plane_funcs intel_sprite_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = intel_plane_destroy, + .atomic_get_property = intel_plane_atomic_get_property, + .atomic_set_property = intel_plane_atomic_set_property, + .atomic_duplicate_state = intel_plane_duplicate_state, + .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_sprite_plane_format_mod_supported, +}; + struct intel_plane * intel_sprite_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, int plane) @@ -1080,6 +1203,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, struct intel_plane_state *state = NULL; unsigned long possible_crtcs; const uint32_t *plane_formats; + const uint64_t *modifiers; unsigned int supported_rotations; int num_plane_formats; int ret; @@ -1097,7 +1221,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } intel_plane->base.state = &state->base; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10) { intel_plane->can_scale = true; state->scaler_id = -1; @@ -1106,6 +1230,17 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); + modifiers = skl_plane_format_modifiers; + } else if (INTEL_GEN(dev_priv) >= 9) { + intel_plane->can_scale = true; + state->scaler_id = -1; + + intel_plane->update_plane = skl_update_plane; + intel_plane->disable_plane = skl_disable_plane; + + plane_formats = skl_plane_formats; + num_plane_formats = ARRAY_SIZE(skl_plane_formats); + modifiers = skl_plane_format_modifiers; } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { intel_plane->can_scale = false; intel_plane->max_downscale = 1; @@ -1115,6 +1250,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = vlv_plane_formats; num_plane_formats = ARRAY_SIZE(vlv_plane_formats); + modifiers = i9xx_plane_format_modifiers; } else if (INTEL_GEN(dev_priv) >= 7) { if (IS_IVYBRIDGE(dev_priv)) { intel_plane->can_scale = true; @@ -1129,6 +1265,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = snb_plane_formats; num_plane_formats = ARRAY_SIZE(snb_plane_formats); + modifiers = i9xx_plane_format_modifiers; } else { intel_plane->can_scale = true; intel_plane->max_downscale = 16; @@ -1136,6 +1273,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = g4x_update_plane; intel_plane->disable_plane = g4x_disable_plane; + modifiers = i9xx_plane_format_modifiers; if (IS_GEN6(dev_priv)) { plane_formats = snb_plane_formats; num_plane_formats = ARRAY_SIZE(snb_plane_formats); @@ -1168,15 +1306,17 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 9) ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, - possible_crtcs, &intel_plane_funcs, + possible_crtcs, &intel_sprite_plane_funcs, plane_formats, num_plane_formats, - NULL, DRM_PLANE_TYPE_OVERLAY, + modifiers, + DRM_PLANE_TYPE_OVERLAY, "plane %d%c", plane + 2, pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, - possible_crtcs, &intel_plane_funcs, + possible_crtcs, &intel_sprite_plane_funcs, plane_formats, num_plane_formats, - NULL, DRM_PLANE_TYPE_OVERLAY, + modifiers, + DRM_PLANE_TYPE_OVERLAY, "sprite %c", sprite_name(pipe, plane)); if (ret) goto fail; From 83e92c218db2e4b99e52b9a6b19b098cdefcbaba Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 10 Aug 2017 15:29:42 +0300 Subject: [PATCH 124/179] Documentation/i915: remove sphinx conversion artefact Remove old warning about docproc directive that's not supported in the Sphinx toolchain. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/7fc8a110b78a9dc9a585dce643b68b4200b7e793.1502368010.git.jani.nikula@intel.com --- Documentation/gpu/i915.rst | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 46875c2bcc31..32c32b89e2e5 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -480,5 +480,3 @@ specific details than found in the more high-level sections. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c :internal: - -.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/drm/i915/i915_irq.c From c3fdb9d8fc0a92a5eb158c1cf91c6c6bae36bb77 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 10 Aug 2017 15:29:43 +0300 Subject: [PATCH 125/179] drm/i915: enum i915_power_well_id is not proper kernel-doc Revert to a normal comment, as the enum isn't properly documented anyway. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/f2c44a0aa00ea7d9b71e7a3183a7507f98811146.1502368010.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 067f8f30c0b8..7296e0cff275 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1127,7 +1127,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) -/** +/* * i915_power_well_id: * * Platform specific IDs used to look up power wells and - except for custom From 1aa920ea0e85d8417c7aa404f50244481e82f0c3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 10 Aug 2017 15:29:44 +0300 Subject: [PATCH 126/179] drm/i915: add register macro definition style guide This is not to try to force a new style; this is my interpretation of what the most common existing style is. With hopes I don't need to answer so many questions about style going forward. Start a new style section in the i915 document to bolt the register style guide into. v2: vertical alignment, incorporate to kernel-doc, and more Cc: Daniel Vetter Reviewed-by: Rodrigo Vivi Reviewed-by: Daniel Vetter Reviewed-by: Dhinakaran Pandiyan Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/9de4a5b1bea4e76461c70a1dd66751581de0124f.1502368010.git.jani.nikula@intel.com --- Documentation/gpu/i915.rst | 14 +++++ drivers/gpu/drm/i915/i915_reg.h | 91 +++++++++++++++++++++++++++++++++ 2 files changed, 105 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 32c32b89e2e5..2e7ee0313c1c 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -480,3 +480,17 @@ specific details than found in the more high-level sections. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c :internal: + +Style +===== + +The drm/i915 driver codebase has some style rules in addition to (and, in some +cases, deviating from) the kernel coding style. + +Register macro definition style +------------------------------- + +The style guide for ``i915_reg.h``. + +.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h + :doc: The i915 register macro definition style guide diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7296e0cff275..44b8da19a2a0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -25,6 +25,97 @@ #ifndef _I915_REG_H_ #define _I915_REG_H_ +/** + * DOC: The i915 register macro definition style guide + * + * Follow the style described here for new macros, and while changing existing + * macros. Do **not** mass change existing definitions just to update the style. + * + * Layout + * '''''' + * + * Keep helper macros near the top. For example, _PIPE() and friends. + * + * Prefix macros that generally should not be used outside of this file with + * underscore '_'. For example, _PIPE() and friends, single instances of + * registers that are defined solely for the use by function-like macros. + * + * Avoid using the underscore prefixed macros outside of this file. There are + * exceptions, but keep them to a minimum. + * + * There are two basic types of register definitions: Single registers and + * register groups. Register groups are registers which have two or more + * instances, for example one per pipe, port, transcoder, etc. Register groups + * should be defined using function-like macros. + * + * For single registers, define the register offset first, followed by register + * contents. + * + * For register groups, define the register instance offsets first, prefixed + * with underscore, followed by a function-like macro choosing the right + * instance based on the parameter, followed by register contents. + * + * Define the register contents (i.e. bit and bit field macros) from most + * significant to least significant bit. Indent the register content macros + * using two extra spaces between ``#define`` and the macro name. + * + * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field + * contents so that they are already shifted in place, and can be directly + * OR'd. For convenience, function-like macros may be used to define bit fields, + * but do note that the macros may be needed to read as well as write the + * register contents. + * + * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in + * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix + * to the name. + * + * Group the register and its contents together without blank lines, separate + * from other registers and their contents with one blank line. + * + * Indent macro values from macro names using TABs. Align values vertically. Use + * braces in macro values as needed to avoid unintended precedence after macro + * substitution. Use spaces in macro values according to kernel coding + * style. Use lower case in hexadecimal values. + * + * Naming + * '''''' + * + * Try to name registers according to the specs. If the register name changes in + * the specs from platform to another, stick to the original name. + * + * Try to re-use existing register macro definitions. Only add new macros for + * new register offsets, or when the register contents have changed enough to + * warrant a full redefinition. + * + * When a register macro changes for a new platform, prefix the new macro using + * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The + * prefix signifies the start platform/generation using the register. + * + * When a bit (field) macro changes or gets added for a new platform, while + * retaining the existing register macro, add a platform acronym or generation + * suffix to the name. For example, ``_SKL`` or ``_GEN8``. + * + * Examples + * '''''''' + * + * (Note that the values in the example are indented using spaces instead of + * TABs to avoid misalignment in generated documentation. Use TABs in the + * definitions.):: + * + * #define _FOO_A 0xf000 + * #define _FOO_B 0xf001 + * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) + * #define FOO_ENABLE (1 << 31) + * #define FOO_MODE_MASK (0xf << 16) + * #define FOO_MODE_SHIFT 16 + * #define FOO_MODE_BAR (0 << 16) + * #define FOO_MODE_BAZ (1 << 16) + * #define FOO_MODE_QUX_SNB (2 << 16) + * + * #define BAR _MMIO(0xb000) + * #define GEN8_BAR _MMIO(0xb888) + */ + typedef struct { uint32_t reg; } i915_reg_t; From 40f75ea466b424ff7a8a24e626b97da52387d210 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 10 Aug 2017 18:57:41 +0100 Subject: [PATCH 127/179] drm/i915/perf: Initialise dynamic sysfs group before creation Another case where we need to call sysfs_attr_init() to setup the internal lockdep class prior to use: [ 9.325229] BUG: key ffff880168bc7bb0 not in .data! [ 9.325240] DEBUG_LOCKS_WARN_ON(1) [ 9.325250] ------------[ cut here ]------------ [ 9.325280] WARNING: CPU: 1 PID: 275 at kernel/locking/lockdep.c:3156 lockdep_init_map+0x1b2/0x1c0 [ 9.325301] Modules linked in: intel_powerclamp(+) coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel i915(+) snd_hda_intel snd_hda_codec snd_hwdep r8169 mii snd_hda_core snd_pcm prime_numbers i2c_hid pinctrl_geminilake pinctrl_intel [ 9.325375] CPU: 1 PID: 275 Comm: modprobe Not tainted 4.13.0-rc4-CI-Trybot_1040+ #1 [ 9.325395] Hardware name: Intel Corp. Geminilake/GLK RVP2 LP4SD (07), BIOS GELKRVPA.X64.0045.B51.1704281422 04/28/2017 [ 9.325422] task: ffff8801721a4ec0 task.stack: ffffc900001dc000 [ 9.325440] RIP: 0010:lockdep_init_map+0x1b2/0x1c0 [ 9.325456] RSP: 0018:ffffc900001dfa10 EFLAGS: 00010282 [ 9.325473] RAX: 0000000000000016 RBX: ffff880168d54b80 RCX: 0000000000000000 [ 9.325488] RDX: 0000000080000001 RSI: 0000000000000001 RDI: ffffffff810f0800 [ 9.325505] RBP: ffffc900001dfa30 R08: 0000000000000001 R09: 0000000000000000 [ 9.325521] R10: 0000000000000000 R11: 0000000000000000 R12: ffff880168bc7bb0 [ 9.325537] R13: 0000000000000000 R14: ffff880168bc7b98 R15: ffffffff81a263a0 [ 9.325554] FS: 00007fb60c3fd700(0000) GS:ffff88017fc80000(0000) knlGS:0000000000000000 [ 9.325574] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 9.325588] CR2: 0000006582777d80 CR3: 000000016d818000 CR4: 00000000003406e0 [ 9.325604] Call Trace: [ 9.325618] __kernfs_create_file+0x76/0xe0 [ 9.325632] sysfs_add_file_mode_ns+0x8a/0x1a0 [ 9.325646] internal_create_group+0xea/0x2c0 [ 9.325660] sysfs_create_group+0x13/0x20 [ 9.325737] i915_perf_register+0xde/0x220 [i915] [ 9.325800] i915_driver_load+0xa77/0x16c0 [i915] [ 9.325863] i915_pci_probe+0x37/0x90 [i915] [ 9.325880] pci_device_probe+0xa8/0x130 [ 9.325894] driver_probe_device+0x29c/0x450 [ 9.325908] __driver_attach+0xe3/0xf0 [ 9.325922] ? driver_probe_device+0x450/0x450 [ 9.325935] bus_for_each_dev+0x62/0xa0 [ 9.325948] driver_attach+0x1e/0x20 [ 9.325960] bus_add_driver+0x173/0x270 [ 9.325974] driver_register+0x60/0xe0 [ 9.325986] __pci_register_driver+0x60/0x70 [ 9.326044] i915_init+0x6f/0x78 [i915] [ 9.326066] ? 0xffffffffa024e000 [ 9.326079] do_one_initcall+0x43/0x170 [ 9.326094] ? rcu_read_lock_sched_held+0x7a/0x90 [ 9.326109] ? kmem_cache_alloc_trace+0x261/0x2d0 [ 9.326124] do_init_module+0x5f/0x206 [ 9.326137] load_module+0x2561/0x2da0 [ 9.326150] ? show_coresize+0x30/0x30 [ 9.326165] ? kernel_read_file+0x105/0x190 [ 9.326180] SyS_finit_module+0xc1/0x100 [ 9.326192] ? SyS_finit_module+0xc1/0x100 [ 9.326210] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 9.326223] RIP: 0033:0x7fb60bf359f9 [ 9.326234] RSP: 002b:00007fff92b47c48 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 [ 9.326255] RAX: ffffffffffffffda RBX: ffffffff814898a3 RCX: 00007fb60bf359f9 [ 9.326271] RDX: 0000000000000000 RSI: 00000028a9ceef8b RDI: 0000000000000000 [ 9.326287] RBP: ffffc900001dff88 R08: 0000000000000000 R09: 0000000000000000 [ 9.326303] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000040000 [ 9.326319] R13: 00000028aaef2a70 R14: 0000000000000000 R15: 00000028aaeee5d0 [ 9.326339] ? __this_cpu_preempt_check+0x13/0x20 [ 9.326353] Code: f1 39 00 85 c0 0f 84 38 ff ff ff 83 3d 9f 44 ce 01 00 0f 85 2b ff ff ff 48 c7 c6 b2 a2 c7 81 48 c7 c7 53 40 c5 81 e8 3f 82 01 00 <0f> ff e9 11 ff ff ff 0f 1f 80 00 00 00 00 55 31 c9 31 d2 31 f6 Fixes: 701f8231a2fe ("drm/i915/perf: prune OA configs") Signed-off-by: Chris Wilson Cc: Lionel Landwerlin Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170810175743.25401-1-chris@chris-wilson.co.uk Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index e3e2663117e9..1be355d14e8a 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2908,8 +2908,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv) if (!dev_priv->perf.metrics_kobj) goto exit; - memset(&dev_priv->perf.oa.test_config, 0, - sizeof(dev_priv->perf.oa.test_config)); + sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr); if (IS_HASWELL(dev_priv)) { i915_perf_load_test_config_hsw(dev_priv); From 84a095e41398efdb245e99cb811bcc0bc24fa504 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 10 Aug 2017 18:57:42 +0100 Subject: [PATCH 128/179] drm/i915/perf: Drop lockdep assert for i915_oa_init_reg_state() This is called from execlist context init which we need to be unlocked. Commit f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface") added a lockdep assert to this path for unclear reasons, remove it again! Fixes: f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface") Signed-off-by: Chris Wilson Cc: Lionel Landwerlin Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170810175743.25401-2-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_perf.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 1be355d14e8a..3bdf53faae24 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2173,8 +2173,6 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct drm_i915_private *dev_priv = engine->i915; struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream; - lockdep_assert_held(&dev_priv->drm.struct_mutex); - if (engine->id != RCS) return; From 28b6cb08206fe19585f57c3f5c683aff9b2e2fdf Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 10 Aug 2017 18:57:43 +0100 Subject: [PATCH 129/179] drm/i915/perf: Drop redundant check for perf.initialised on reset As we cannot have an exclusive stream set if the perf has not been initialized, we only need to check for that exclusive stream. Signed-off-by: Chris Wilson Cc: Lionel Landwerlin Cc: Matthew Auld Link: https://patchwork.freedesktop.org/patch/msgid/20170810175743.25401-3-chris@chris-wilson.co.uk Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_perf.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 3bdf53faae24..94185d610673 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2170,15 +2170,12 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct i915_gem_context *ctx, u32 *reg_state) { - struct drm_i915_private *dev_priv = engine->i915; - struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream; + struct i915_perf_stream *stream; if (engine->id != RCS) return; - if (!dev_priv->perf.initialized) - return; - + stream = engine->i915->perf.oa.exclusive_stream; if (stream) gen8_update_reg_state_unlocked(ctx, reg_state, stream->oa_config); } From 06bfe5b0d892f8120172380694eb66eeb23baf90 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 10 Aug 2017 07:50:43 -0700 Subject: [PATCH 130/179] drm/i915: Avoid null dereference if mst_port is unset. I'm not sure if this is really the case and I don't believe this is the real fix for the bug mentioned here, but since I don't see a reliable path when mst_port is set and when mode_valid is requested I believe it is worth to have this protection here. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102022 Cc: Elizabeth Cc: Stefan Assmann Cc: Dhinakaran Pandiyan Signed-off-by: Rodrigo Vivi Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170810145043.24047-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 58568559711a..93fc8ab9bb31 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -370,6 +370,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, int bpp = 24; /* MST uses fixed bpp */ int max_rate, mode_rate, max_lanes, max_link_clock; + if (!intel_dp) + return MODE_ERROR; + max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); From 50682ee63fa3480b0541d0a311239189634b68ab Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 9 Aug 2017 13:52:43 -0700 Subject: [PATCH 131/179] drm/i915/gen10+: use the SKL code for reading WM latencies Gen 10 should use the exact same code as Gen 9, so change the check to take this into consideration, and also assume that future platforms will run this code. Also add a MISSING_CASE(), just in case we do something wrong, instead of silently failing. Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4a75b673b85f..04697faee4e6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2778,7 +2778,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) static void intel_read_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[8]) { - if (IS_GEN9(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 9) { uint32_t val; int ret, i; int level, max_level = ilk_wm_max_level(dev_priv); @@ -2838,7 +2838,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, } /* - * WaWmMemoryReadLatency:skl,glk + * WaWmMemoryReadLatency:skl+,glk * * punit doesn't take into account the read latency so we need * to add 2us to the various latency levels we retrieve from the @@ -2877,6 +2877,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, wm[0] = 7; wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; + } else { + MISSING_CASE(INTEL_DEVID(dev_priv)); } } From 019718196c594d2e33cc371cbbcccb84735e6ada Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Wed, 9 Aug 2017 13:52:44 -0700 Subject: [PATCH 132/179] drm/i915/cnl: Enable SAGV for Cannonlake. For now inherit from previous platforms. v2: Rebase on top of CFL. Cc: Mahesh Kumar Cc: Maarten Lankhorst Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-2-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 04697faee4e6..52bf62b6e38c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3571,7 +3571,8 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) static bool intel_has_sagv(struct drm_i915_private *dev_priv) { - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || + IS_CANNONLAKE(dev_priv)) return true; if (IS_SKYLAKE(dev_priv) && From fdd11c2bfce22e57145e861905b2753c0451df85 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 9 Aug 2017 13:52:45 -0700 Subject: [PATCH 133/179] drm/i915/gen10: fix the gen 10 SAGV block time A previous commit added CNL to intel_has_sagv(), but forgot to adjust the SAGV block time to gen 10 platforms. Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-3-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 52bf62b6e38c..f64fdae88b7d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3552,8 +3552,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev) return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); } -#define SKL_SAGV_BLOCK_TIME 30 /* µs */ - /* * FIXME: We still don't have the proper code detect if we need to apply the WA, * so assume we'll always need it in order to avoid underruns. @@ -3678,12 +3676,13 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) struct intel_crtc_state *cstate; enum pipe pipe; int level, latency; + int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20; if (!intel_has_sagv(dev_priv)) return false; /* - * SKL workaround: bspec recommends we disable the SAGV when we have + * SKL+ workaround: bspec recommends we disable the SAGV when we have * more then one pipe enabled * * If there are no active CRTCs, no additional checks need be performed @@ -3722,11 +3721,11 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) latency += 15; /* - * If any of the planes on this pipe don't enable wm levels - * that incur memory latencies higher then 30µs we can't enable - * the SAGV + * If any of the planes on this pipe don't enable wm levels that + * incur memory latencies higher than sagv_block_time_us we + * can't enable the SAGV. */ - if (latency < SKL_SAGV_BLOCK_TIME) + if (latency < sagv_block_time_us) return false; } From dfc267ab5acb2ce73078097875f24985942765af Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 9 Aug 2017 13:52:46 -0700 Subject: [PATCH 134/179] drm/i915/gen10: fix WM latency printing Gen 10 is just like Gen 9, so let's consider that all the future platforms are going to be like gen 9 instead of being like gen8-. Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-4-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f64fdae88b7d..66495ad36973 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2934,7 +2934,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, * - latencies are in us on gen9. * - before then, WM1+ latency values are in 0.5us units */ - if (IS_GEN9(dev_priv)) + if (INTEL_GEN(dev_priv) >= 9) latency *= 10; else if (level > 0) latency *= 5; From 7ea1adf30f82a4c0910524ac06f8f1f26281bb23 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Wed, 9 Aug 2017 13:07:02 -0700 Subject: [PATCH 135/179] drm/i915/cnl: Add slice and subslice information to debugfs. A missing part to EU slice power gating is the debugfs interface. This patch actually should have been squashed to the initial EU slice power gating one. v2: Initial patch was merged without this part. Fixes: c7ae7e9ab207 ("drm/i915/cnl: Configure EU slice power gating.") Cc: Joonas Lahtinen Signed-off-by: Rodrigo Vivi Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20170809200702.11236-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 6480897bcaf4..329fb3649dc3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4560,7 +4560,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); - if (IS_GEN9_BC(dev_priv)) + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; From 2ae9e3653f09121c224a1fbff617921d08b839ae Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 11 Aug 2017 09:23:27 +0200 Subject: [PATCH 136/179] drm/i915/fbc: only update no_fbc_reason when active In our snb farm in CI we have plenty of underruns, but not enough stolen memory to enable fbc. Which means every time there's an underrun the no_fbc_reason swichtes to something that makes kms_frontbuffer_tracking fail instead of skip, adding massive amounts of additional noise to igt test runs. Make sure we don't try to disable fbc when it's off already. v2: Squash in additional WARN_ON suggestion from Chris. Cc: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170811072327.4335-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_fbc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 860b8c26d29b..3fca9fa39a8e 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -461,6 +461,8 @@ static void intel_fbc_schedule_activation(struct intel_crtc *crtc) struct intel_fbc_work *work = &fbc->work; WARN_ON(!mutex_is_locked(&fbc->lock)); + if (WARN_ON(!fbc->enabled)) + return; if (drm_crtc_vblank_get(&crtc->base)) { DRM_ERROR("vblank not available for FBC on pipe %c\n", @@ -1216,7 +1218,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work) mutex_lock(&fbc->lock); /* Maybe we were scheduled twice. */ - if (fbc->underrun_detected) + if (fbc->underrun_detected || !fbc->enabled) goto out; DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n"); From 2d56758557bc465a44879b471c84bd09ce8a2aac Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 11 Aug 2017 14:49:38 +0100 Subject: [PATCH 137/179] drm/i915: make structure intel_sprite_plane_funcs static The structure intel_sprite_plane_funcs is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'intel_sprite_plane_funcs' was not declared. Should it be static? Signed-off-by: Colin Ian King Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170811134938.4183-1-colin.king@canonical.com --- drivers/gpu/drm/i915/intel_sprite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index e11f8782c9eb..524933b01483 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1184,7 +1184,7 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, unreachable(); } -const struct drm_plane_funcs intel_sprite_plane_funcs = { +static const struct drm_plane_funcs intel_sprite_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = intel_plane_destroy, From 50946c89850db13bd672c664aec6cf4551f71fe9 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 17 Jul 2017 12:58:54 -0700 Subject: [PATCH 138/179] drm/i915: Return correct EDP voltage swing table for 0.85V For 0.85V cnl_get_buf_trans_edp() returns the DP table, instead of EDP. Use the correct table. The error was pointed out by this clang warning: drivers/gpu/drm/i915/intel_ddi.c:392:39: warning: variable 'cnl_ddi_translations_edp_0_85V' is not needed and will not be emitted [-Wunneeded-internal-declaration] static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") Signed-off-by: Matthias Kaehlcke Reviewed-by: Manasi Navare Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20170717195854.192139-1-mka@chromium.org --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 494fbe0a7678..4b4fd1f8110b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1876,7 +1876,7 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, if (dev_priv->vbt.edp.low_vswing) { if (voltage == VOLTAGE_INFO_0_85V) { *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); - return cnl_ddi_translations_dp_0_85V; + return cnl_ddi_translations_edp_0_85V; } else if (voltage == VOLTAGE_INFO_0_95V) { *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); return cnl_ddi_translations_edp_0_95V; From d907b6658a7b51c82efcefca1aa4d0962dba4801 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 10 Aug 2017 15:40:08 -0700 Subject: [PATCH 139/179] drm/i915/cnl: Add allowed DP rates for Cannonlake. "Frequencies over 5.4 GHz only supported on certain DDI ports and SKUs, and requires Vccio >= 0.95V." More specifically, for current CNL SKUs available (CNL-U and CNL-Y) we have: DDI A - 5.4G eDP DDI B - 8.1G DP DDI C - 8.1G DP DDI D - 5.4G DP v2: Rebase on top of source_rates changes. v3: Address the max 5.4 x 8.1 per DDI and also consider vccio. Cc: Mika Kahola Signed-off-by: Rodrigo Vivi Reviewed-by: Manasi Navare Link: https://patchwork.freedesktop.org/patch/msgid/20170810224008.15571-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 76c8a0bd17f9..ead37c449019 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -97,6 +97,9 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000, 324000, 432000, 540000 }; static const int skl_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; +static const int cnl_rates[] = { 162000, 216000, 270000, + 324000, 432000, 540000, + 648000, 810000 }; static const int default_rates[] = { 162000, 270000, 540000 }; /** @@ -229,8 +232,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->port; const int *source_rates; int size; + u32 voltage; /* This should only be done once */ WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); @@ -238,6 +243,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) if (IS_GEN9_LP(dev_priv)) { source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); + } else if (IS_CANNONLAKE(dev_priv)) { + source_rates = cnl_rates; + size = ARRAY_SIZE(cnl_rates); + voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + if (port == PORT_A || port == PORT_D || + voltage == VOLTAGE_INFO_0_85V) + size -= 2; } else if (IS_GEN9_BC(dev_priv)) { source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); From c1b56c52aa3c38982b801a36f9b7de96077579f4 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 10 Aug 2017 15:45:25 -0700 Subject: [PATCH 140/179] drm/i915/cnl: Dump the right pll registers when dumping pipe config. Different from SKL we don't need ctrl1 and cfgcr2, but we need to dump cfgcr0 and cfgcr1 instead. v2: rebase and commit message Cc: Clint Taylor Cc: Mika Kahola Signed-off-by: Rodrigo Vivi Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20170810224525.18278-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 2f7b0e64f628..a2a3d93d67bd 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2379,6 +2379,15 @@ cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, return pll; } +static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, + struct intel_dpll_hw_state *hw_state) +{ + DRM_DEBUG_KMS("dpll_hw_state: " + "cfgcr0: 0x%x, cfgcr1: 0x%x\n", + hw_state->cfgcr0, + hw_state->cfgcr1); +} + static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { .enable = cnl_ddi_pll_enable, .disable = cnl_ddi_pll_disable, @@ -2395,7 +2404,7 @@ static const struct dpll_info cnl_plls[] = { static const struct intel_dpll_mgr cnl_pll_mgr = { .dpll_info = cnl_plls, .get_dpll = cnl_get_dpll, - .dump_hw_state = skl_dump_hw_state, + .dump_hw_state = cnl_dump_hw_state, }; /** From 256cfdde42c0f8f74d417875f71ea864e686917b Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 11 Aug 2017 11:26:49 -0700 Subject: [PATCH 141/179] drm/i915: Simplify hpd pin to port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We will soon need to make that pin port association per platform, so let's try to simplify it beforehand. Also we are moving the backwards port to pin here as well so let's use a standardized way. One extra possibility here would be to add a MISSING_CASE along with PORT_NONE, but I don't want to change this behaviour for now. Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Link: https://patchwork.freedesktop.org/patch/msgid/20170811182650.14327-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_irq.c | 3 ++- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_hotplug.c | 31 +++++++++++++++------------- 4 files changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 907603cba447..68ec47b378ac 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3194,7 +3194,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, void intel_hpd_init(struct drm_i915_private *dev_priv); void intel_hpd_init_work(struct drm_i915_private *dev_priv); void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); -bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); +enum port intel_hpd_pin_to_port(enum hpd_pin pin); bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 196caa463edf..58262380dcb8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1501,7 +1501,8 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, *pin_mask |= BIT(i); - if (!intel_hpd_pin_to_port(i, &port)) + port = intel_hpd_pin_to_port(i); + if (port == PORT_NONE) continue; if (long_pulse_detect(port, dig_hotplug_reg)) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ead37c449019..e94f6fcfa53a 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4578,7 +4578,7 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, enum port port; u32 bit; - intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); + port = intel_hpd_pin_to_port(intel_encoder->hpd_pin); switch (port) { case PORT_A: bit = BXT_DE_PORT_HP_DDIA; diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index f1200272a699..d442d9f012d6 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -76,26 +76,28 @@ * it will use i915_hotplug_work_func where this logic is handled. */ -bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port) +/** + * intel_hpd_port - return port hard associated with certain pin. + * @pin: the hpd pin to get associated port + * + * Return port that is associatade with @pin and PORT_NONE if no port is + * hard associated with that @pin. + */ +enum port intel_hpd_pin_to_port(enum hpd_pin pin) { switch (pin) { case HPD_PORT_A: - *port = PORT_A; - return true; + return PORT_A; case HPD_PORT_B: - *port = PORT_B; - return true; + return PORT_B; case HPD_PORT_C: - *port = PORT_C; - return true; + return PORT_C; case HPD_PORT_D: - *port = PORT_D; - return true; + return PORT_D; case HPD_PORT_E: - *port = PORT_E; - return true; + return PORT_E; default: - return false; /* no hpd */ + return PORT_NONE; /* no port for this pin */ } } @@ -389,8 +391,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, if (!(BIT(i) & pin_mask)) continue; - is_dig_port = intel_hpd_pin_to_port(i, &port) && - dev_priv->hotplug.irq_port[port]; + port = intel_hpd_pin_to_port(i); + is_dig_port = port != PORT_NONE && + dev_priv->hotplug.irq_port[port]; if (is_dig_port) { bool long_hpd = long_mask & BIT(i); From f761bef2f341015eb1ad8a8840187a989c4893f2 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 11 Aug 2017 11:26:50 -0700 Subject: [PATCH 142/179] drm/i915: Introduce intel_hpd_pin function. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The idea is to have an unique place to decide the pin-port per platform. So let's create this function now without any functional change. Just adding together code from hdmi and dp together. v2: Add missing pin for port A. v3: Fix typo on subject. Avoid behaviour change so add WARN_ON and return if port A on HDMI. (by DK). Cc: Dhinakaran Pandiyan Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Link: https://patchwork.freedesktop.org/patch/msgid/20170811182650.14327-2-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 8 ++------ drivers/gpu/drm/i915/intel_hdmi.c | 18 ++---------------- drivers/gpu/drm/i915/intel_hotplug.c | 26 ++++++++++++++++++++++++++ 4 files changed, 31 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 68ec47b378ac..ba59e64eb378 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3195,6 +3195,7 @@ void intel_hpd_init(struct drm_i915_private *dev_priv); void intel_hpd_init_work(struct drm_i915_private *dev_priv); void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); enum port intel_hpd_pin_to_port(enum hpd_pin pin); +enum hpd_pin intel_hpd_pin(enum port port); bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index e94f6fcfa53a..5ba8366ff1e5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5916,26 +5916,22 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port) struct intel_encoder *encoder = &intel_dig_port->base; struct intel_dp *intel_dp = &intel_dig_port->dp; + encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port); + switch (intel_dig_port->port) { case PORT_A: - encoder->hpd_pin = HPD_PORT_A; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A; break; case PORT_B: - encoder->hpd_pin = HPD_PORT_B; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B; break; case PORT_C: - encoder->hpd_pin = HPD_PORT_C; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C; break; case PORT_D: - encoder->hpd_pin = HPD_PORT_D; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; break; case PORT_E: - encoder->hpd_pin = HPD_PORT_E; - /* FIXME: Check VBT for actual wiring of PORT E */ intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; break; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 2ef1ee85129d..e30c27acb94f 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1920,23 +1920,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); - switch (port) { - case PORT_B: - intel_encoder->hpd_pin = HPD_PORT_B; - break; - case PORT_C: - intel_encoder->hpd_pin = HPD_PORT_C; - break; - case PORT_D: - intel_encoder->hpd_pin = HPD_PORT_D; - break; - case PORT_E: - intel_encoder->hpd_pin = HPD_PORT_E; - break; - default: - MISSING_CASE(port); + if (WARN_ON(port == PORT_A)) return; - } + intel_encoder->hpd_pin = intel_hpd_pin(port); if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { intel_hdmi->write_infoframe = vlv_write_infoframe; diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index d442d9f012d6..875d5d218d5c 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -101,6 +101,32 @@ enum port intel_hpd_pin_to_port(enum hpd_pin pin) } } +/** + * intel_hpd_pin - return pin hard associated with certain port. + * @port: the hpd port to get associated pin + * + * Return pin that is associatade with @port and HDP_NONE if no pin is + * hard associated with that @port. + */ +enum hpd_pin intel_hpd_pin(enum port port) +{ + switch (port) { + case PORT_A: + return HPD_PORT_A; + case PORT_B: + return HPD_PORT_B; + case PORT_C: + return HPD_PORT_C; + case PORT_D: + return HPD_PORT_D; + case PORT_E: + return HPD_PORT_E; + default: + MISSING_CASE(port); + return HPD_NONE; + } +} + #define HPD_STORM_DETECT_PERIOD 1000 #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000) From d90cb7f852034e5bf50158b34047effa453a9836 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 10 Aug 2017 10:40:36 +0100 Subject: [PATCH 143/179] drm/i915: Add SW_SYNC to our recommend testing Kconfig Since we do use the SW_SYNC in igt for validating dma-fence and sync_file, and wish to expand usage to cover driver independent portions of syncobj interaction, ensure SW_SYNC is included in our testing Kconfig. Signed-off-by: Chris Wilson Cc: Jason Ekstrand Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20170810094036.4307-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 78c5c049a347..aed7d207ea84 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -25,6 +25,7 @@ config DRM_I915_DEBUG select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks) select DRM_DEBUG_MM if DRM=y select DRM_DEBUG_MM_SELFTEST + select SW_SYNC # signaling validation framework (igt/syncobj*) select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST default n From 12124bea5b82dc1e917304aed703c27292270051 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 12 Aug 2017 16:27:24 +0100 Subject: [PATCH 144/179] drm/i915: Suppress switch_mm emission between the same aliasing_ppgtt When switching between contexts using the aliasing_ppgtt, the VM is shared. We don't need to reload the PD registers unless they are dirty. Martin Peres reported an issue that looks like corruption between Haswell context switches, bisecting to commit f9326be5f1d3 ("drm/i915: Rearrange switch_context to load the aliasing ppgtt on first use"). Switching between the same mm (the aliasing_ppgtt is used for all contexts in this case) should be a nop, but appears to trigger some side-effects in the context switch. However, as we know the switch is redundant in this case, we can skip it and continue to ignore the issue until somebody feels strong enough to investigate full-ppgtt on gen7 again! Except.. Martin was using full-ppgtt which is not supported as it doesn't work correctly yet. So whilst the bisect did yield valuable information about the failures, the fix should not have any user impact under default settings, with the exception of a slightly lower throughput on xcs as the VM would always be reloaded. v2: Also remember to set the legacy_active_context following the switch on xcs (commit e8a9c58fcd9a ("drm/i915: Unify active context tracking between legacy/execlists/guc")) Fixes: f9326be5f1d3 ("drm/i915: Rearrange switch_context to load the aliasing ppgtt on first use") Fixes: e8a9c58fcd9a ("drm/i915: Unify active context tracking between legacy/execlists/guc") Reported-by: Martin Peres Signed-off-by: Chris Wilson Cc: Martin Peres Reviewed-by: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20170812152724.6883-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_context.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index ed91ac8ca832..86ac74a8a5b2 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -741,19 +741,19 @@ static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, } static bool -needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, - struct intel_engine_cs *engine, - struct i915_gem_context *to) +needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine) { + struct i915_gem_context *from = engine->legacy_active_context; + if (!ppgtt) return false; /* Always load the ppgtt on first use */ - if (!engine->legacy_active_context) + if (!from) return true; /* Same context without new entries, skip */ - if (engine->legacy_active_context == to && + if ((!from->ppgtt || from->ppgtt == ppgtt) && !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) return false; @@ -797,7 +797,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) if (skip_rcs_switch(ppgtt, engine, to)) return 0; - if (needs_pd_load_pre(ppgtt, engine, to)) { + if (needs_pd_load_pre(ppgtt, engine)) { /* Older GENs and non render rings still want the load first, * "PP_DCLV followed by PP_DIR_BASE register through Load * Register Immediate commands in Ring Buffer before submitting @@ -894,7 +894,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; - if (needs_pd_load_pre(ppgtt, engine, to)) { + if (needs_pd_load_pre(ppgtt, engine)) { int ret; trace_switch_mm(engine, to); @@ -905,6 +905,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); } + engine->legacy_active_context = to; return 0; } From ccba59197a430ee4c295ee8f4b127c6dea954501 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Wed, 9 Aug 2017 21:26:03 +0000 Subject: [PATCH 145/179] drm/i915/guc: Rename GuC irq trigger function We should emphasize that irq raising function depends on Gen. v2: use yet another better name (Chris) Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170809212603.28780-1-michal.wajdeczko@intel.com Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_uc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 27e072cc96eb..0178ba42a0e5 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -94,7 +94,7 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv); } -static void guc_write_irq_trigger(struct intel_guc *guc) +static void gen8_guc_raise_irq(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); @@ -109,7 +109,7 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv) mutex_init(&guc->send_mutex); guc->send = intel_guc_send_nop; - guc->notify = guc_write_irq_trigger; + guc->notify = gen8_guc_raise_irq; } static void fetch_uc_fw(struct drm_i915_private *dev_priv, From 27437890809d1d67b1661853954040c99af4fb53 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Thu, 10 Aug 2017 14:04:51 +0300 Subject: [PATCH 146/179] drm/i915/gen9: Send all components in VF state Update gen9 renderstate to account the, long overdue, changes for igt commit 5c07135b7bd2 ("tools/null_state/gen9: Send all components in VF state"). Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170810110451.31635-1-mika.kuoppala@intel.com --- drivers/gpu/drm/i915/intel_renderstate_gen9.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_renderstate_gen9.c b/drivers/gpu/drm/i915/intel_renderstate_gen9.c index 16a7ec273bd9..7d3ac02f0177 100644 --- a/drivers/gpu/drm/i915/intel_renderstate_gen9.c +++ b/drivers/gpu/drm/i915/intel_renderstate_gen9.c @@ -20,7 +20,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * - * Generated by: intel-gpu-tools-1.8-220-g01153e7 + * Generated by: intel-gpu-tools-1.19-177-g68e2eab2 */ #include "intel_renderstate.h" @@ -873,7 +873,7 @@ static const u32 gen9_null_state_batch[] = { 0x00000000, 0x00000000, 0x78550003, - 0x00000000, + 0x0000000f, 0x00000000, 0x00000000, 0x00000000, From 97154ec242c14f646a3ab3b4da8f838d197f300d Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 8 Aug 2017 10:08:26 +0200 Subject: [PATCH 147/179] drm/i915: Avoid the gpu reset vs. modeset deadlock ... using the biggest hammer we have. This is essentially a weaponized version of the timeout-based wedging Chris added in commit 36703e79a982c8ce5a8e43833291f2719e92d0d1 Author: Chris Wilson Date: Thu Jun 22 11:56:25 2017 +0100 drm/i915: Break modeset deadlocks on reset Because defense-in-depth is good it's good to still have both. Also note that with the locking change we can now restrict this a lot (old gpus and special testing only), so this doesn't kill the TDR benefits on at least anything remotely modern. And futuremore with a few tricks it should be possible to make a much more educated guess about whether an atomic commit is stuck waiting on the gpu (atomic_t counting the pending i915_sw_fence used by the atomic modeset code should do it), so we can improve this. But for now just start with something that is guaranteed to recover faster, for much better CI througput. This defacto reverts TDR on these platforms, but there's not really a single commit to specify as the sole offender. v2: Add a debug message to explain what's going on. We can't DRM_ERROR because that spams CI. And the timeout based fallback still prints a DRM_ERROR, in case something goes wrong. v3: Fix comment layout (Michel) Fixes: 4680816be336 ("drm/i915: Wait first for submission, before waiting for request completion") Fixes: 221fe7994554 ("drm/i915: Perform a direct reset of the GPU from the waiter") Cc: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: Tvrtko Ursulin (v2) Cc: Michel Thierry Reviewed-by: Tvrtko Ursulin (v2) Reviewed-by: Michel Thierry Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170808080828.23650-1-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index beff138e9b92..ee6d3121890e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3681,6 +3681,13 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) !gpu_reset_clobbers_display(dev_priv)) return; + /* We have a modeset vs reset deadlock, defensively unbreak it. + * + * FIXME: We can do a _lot_ better, this is just a first iteration. + */ + i915_gem_set_wedged(dev_priv); + DRM_DEBUG_DRIVER("Wedging GPU to avoid deadlocks with pending modeset updates\n"); + /* * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. From 42b062b0d9463557966766940791548313df6b55 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 8 Aug 2017 10:08:27 +0200 Subject: [PATCH 148/179] drm/i915: Push i915_sw_fence_wait into the nonblocking atomic commit Blocking in a worker is ok, that's what the unbound_wq is for. And it unifies the paths between the blocking and nonblocking commit, giving me just one path where I have to implement the deadlock avoidance trickery in the next patch. I first tried to implement the following patch without this rework, but force-completing i915_sw_fence creates some serious challenges around properly cleaning things up. So wasn't a feasible short-term approach. Another approach would be to simple keep track of all pending atomic commit work items and manually queue them from the reset code. With the caveat that double-queue in case we race with the i915_sw_fence must be avoided. Given all that, taking the cost of a double schedule in atomic for the short-term fix is the best approach, but can be changed in the future of course. v2: Amend commit message (Chris). v3: Add comment explaining why we do nothing in the sw_fence complete callback (Michel). Reviewed-by: Maarten Lankhorst Cc: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: Tvrtko Ursulin (v2) Cc: Michel Thierry Reviewed-by: Michel Thierry Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170808080828.23650-2-daniel.vetter@ffwll.ch --- drivers/gpu/drm/i915/intel_display.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ee6d3121890e..519aa240cc4c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12311,6 +12311,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) unsigned crtc_vblank_mask = 0; int i; + i915_sw_fence_wait(&intel_state->commit_ready); + drm_atomic_helper_wait_for_dependencies(state); if (intel_state->modeset) @@ -12476,10 +12478,8 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence, switch (notify) { case FENCE_COMPLETE: - if (state->base.commit_work.func) - queue_work(system_unbound_wq, &state->base.commit_work); + /* we do blocking waits in the worker, nothing to do here */ break; - case FENCE_FREE: { struct intel_atomic_helper *helper = @@ -12581,14 +12581,14 @@ static int intel_atomic_commit(struct drm_device *dev, } drm_atomic_state_get(state); - INIT_WORK(&state->commit_work, - nonblock ? intel_atomic_commit_work : NULL); + INIT_WORK(&state->commit_work, intel_atomic_commit_work); i915_sw_fence_commit(&intel_state->commit_ready); - if (!nonblock) { - i915_sw_fence_wait(&intel_state->commit_ready); + if (nonblock) + queue_work(system_unbound_wq, &state->commit_work); + else intel_atomic_commit_tail(state); - } + return 0; } From 9db529aac9381e746f31f8109fdb186b69157661 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 8 Aug 2017 10:08:28 +0200 Subject: [PATCH 149/179] drm/i915: More surgically unbreak the modeset vs reset deadlock There's no reason to entirely wedge the gpu, for the minimal deadlock bugfix we only need to unbreak/decouple the atomic commit from the gpu reset. The simplest way to fix that is by replacing the unconditional fence wait a the top of commit_tail by a wait which completes either when the fences are done (normal case, or when a reset doesn't need to touch the display state). Or when the gpu reset needs to force-unblock all pending modeset states. The lesser source of deadlocks is when we try to pin a new framebuffer and run into a stall. There's a bunch of places this can happen, like eviction, changing the caching mode, acquiring a fence on older platforms. And we can't just break the depency loop and keep going, the only way would be to break out and restart. But the problem with that approach is that we must stall for the reset to complete before we grab any locks, and with the atomic infrastructure that's a bit tricky. The only place is the ioctl code, and we don't want to insert code into e.g. the BUSY ioctl. Hence for that problem just create a critical section, and if any code is in there, wedge the GPU. For the steady-state this should never be a problem. Note that in both cases TDR itself keeps working, so from a userspace pov this trickery isn't observable. Users themselvs might spot a short glitch while the rendering is catching up again, but that's still better than pre-TDR where we've thrown away all the rendering, including innocent batches. Also, this fixes the regression TDR introduced of making gpu resets deadlock-prone when we do need to touch the display. One thing I noticed is that gpu_error.flags seems to use both our own wait-queue in gpu_error.wait_queue, and the generic wait_on_bit facilities. Not entirely sure why this inconsistency exists, I just picked one style. A possible future avenue could be to insert the gpu reset in-between ongoing modeset changes, which would avoid the momentary glitch. But that's a lot more work to implement in the atomic commit machinery, and given that we only need this for pre-g4x hw, of questionable utility just for the sake of polishing gpu reset even more on those old boxes. It might be useful for other features though. v2: Rebase onto 4.13 with a s/wait_queue_t/struct wait_queue_entry/. v3: Really emabarrassing fixup, I checked the wrong bit and broke the unbreak/wakeup logic. v4: Also handle deadlocks in pin_to_display. v5: Review from Michel: - Fixup the BUILD_BUG_ON - Don't forget about the overlay Cc: Michel Thierry Cc: Chris Wilson Cc: Mika Kuoppala Cc: Joonas Lahtinen Cc: Tvrtko Ursulin (v2) Cc: Michel Thierry Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170808080828.23650-3-daniel.vetter@ffwll.ch Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_overlay.c | 11 +++++-- 4 files changed, 52 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ba59e64eb378..ef5af697732d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1528,6 +1528,8 @@ struct i915_gpu_error { /* Protected by the above dev->gpu_error.lock. */ struct i915_gpu_state *first_error; + atomic_t pending_fb_pin; + unsigned long missed_irq_rings; /** @@ -1587,6 +1589,7 @@ struct i915_gpu_error { unsigned long flags; #define I915_RESET_BACKOFF 0 #define I915_RESET_HANDOFF 1 +#define I915_RESET_MODESET 2 #define I915_WEDGED (BITS_PER_LONG - 1) #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 58262380dcb8..e21ce9c18b6e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2709,7 +2709,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv, */ if (intel_has_reset_engine(dev_priv)) { for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { - BUILD_BUG_ON(I915_RESET_HANDOFF >= I915_RESET_ENGINE); + BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE); if (test_and_set_bit(I915_RESET_ENGINE + engine->id, &dev_priv->gpu_error.flags)) continue; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 519aa240cc4c..decf5da63950 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2196,6 +2196,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) */ intel_runtime_pm_get(dev_priv); + atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); if (IS_ERR(vma)) goto err; @@ -2223,6 +2225,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) i915_vma_get(vma); err: + atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + intel_runtime_pm_put(dev_priv); return vma; } @@ -3681,12 +3685,14 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) !gpu_reset_clobbers_display(dev_priv)) return; - /* We have a modeset vs reset deadlock, defensively unbreak it. - * - * FIXME: We can do a _lot_ better, this is just a first iteration. - */ - i915_gem_set_wedged(dev_priv); - DRM_DEBUG_DRIVER("Wedging GPU to avoid deadlocks with pending modeset updates\n"); + /* We have a modeset vs reset deadlock, defensively unbreak it. */ + set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); + wake_up_all(&dev_priv->gpu_error.wait_queue); + + if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { + DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n"); + i915_gem_set_wedged(dev_priv); + } /* * Need mode_config.mutex so that we don't @@ -3774,6 +3780,8 @@ unlock: drm_modeset_drop_locks(ctx); drm_modeset_acquire_fini(ctx); mutex_unlock(&dev->mode_config.mutex); + + clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); } static void intel_update_pipe_config(struct intel_crtc *crtc, @@ -12298,6 +12306,30 @@ static void intel_atomic_helper_free_state_worker(struct work_struct *work) intel_atomic_helper_free_state(dev_priv); } +static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) +{ + struct wait_queue_entry wait_fence, wait_reset; + struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); + + init_wait_entry(&wait_fence, 0); + init_wait_entry(&wait_reset, 0); + for (;;) { + prepare_to_wait(&intel_state->commit_ready.wait, + &wait_fence, TASK_UNINTERRUPTIBLE); + prepare_to_wait(&dev_priv->gpu_error.wait_queue, + &wait_reset, TASK_UNINTERRUPTIBLE); + + + if (i915_sw_fence_done(&intel_state->commit_ready) + || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags)) + break; + + schedule(); + } + finish_wait(&intel_state->commit_ready.wait, &wait_fence); + finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset); +} + static void intel_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; @@ -12311,7 +12343,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) unsigned crtc_vblank_mask = 0; int i; - i915_sw_fence_wait(&intel_state->commit_ready); + intel_atomic_commit_fence_wait(intel_state); drm_atomic_helper_wait_for_dependencies(state); diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index b96aed941b97..aace22e7ccac 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -799,9 +799,13 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, if (ret != 0) return ret; + atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); + goto out_pin_section; + } ret = i915_vma_put_fence(vma); if (ret) @@ -886,6 +890,9 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, out_unpin: i915_gem_object_unpin_from_display_plane(vma); +out_pin_section: + atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + return ret; } From 4fc05063519cb7699142909e63807e55e03bde34 Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Fri, 11 Aug 2017 12:51:26 +0300 Subject: [PATCH 150/179] drm/i915: Disconnect 32 and 48 bit ppGTT support Configurations like virtualized environments may support only 48 bit ppGTT without supporting 32 bit ppGTT. Support this by disconnecting the relationship of the two feature bits. Cc: Tina Zhang Cc: Chris Wilson Cc: Zhi Wang Reviewed-by: Chris Wilson Signed-off-by: Joonas Lahtinen Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 10aa7762d9a6..a5eada1b93c5 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, return 0; } - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) - return has_full_48bit_ppgtt ? 3 : 2; - else - return has_aliasing_ppgtt ? 1 : 0; + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { + if (has_full_48bit_ppgtt) + return 3; + + if (has_full_ppgtt) + return 2; + } + + return has_aliasing_ppgtt ? 1 : 0; } static int ppgtt_bind_vma(struct i915_vma *vma, From 8a4ab66f3849c68aec0afb9ec09c671ef5549284 Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Mon, 14 Aug 2017 15:20:46 +0800 Subject: [PATCH 151/179] drm/i915: Enable guest i915 full ppgtt functionality Enable the guest i915 full ppgtt functionality when host can provide this capability. vgt_caps is introduced to guest i915 driver to get the vgpu capabilities from the device model. VGT_CPAS_FULL_PPGTT is one of the capabilities type to let guest i915 dirver know that the guest i915 full ppgtt is supported by device model. Notice that the minor version of pvinfo isn't bumped because of this vgt_caps introduction, due to older guest would be broken by simply increasing the pvinfo version. Although the pvinfo minor version doesn't increase, the compatibility won't be blocked. The compatibility is ensured by checking the value of caps field in pvinfo. Zero means no full ppgtt support and BIT(2) means this feature is provided. Changes since v1: - Use u32 instead of uint32_t (Joonas) - Move VGT_CAPS_FULL_PPGTT introduction to this patch and use #define instead of enum (Joonas) - Rewrite the vgpu full ppgtt capability checking logic. (Joonas) - Some coding style refine. (Joonas) Changes since v2: - Divide the whole patch set into two separate patch series, with one patch in i915 side to check guest i915 full ppgtt capability and enable it when this capability is supported by the device model, and the other one in gvt side which fixs the blocking issue and enables the device model to provide the capability to guest. And this patch focuses on guest i915 side. (Joonas) - Change the title from "introduce vgt_caps to pvinfo" to "Enable guest i915 full ppgtt functionality". (Tina) Change since v3: - Add some comments about pvinfo caps and version. (Joonas) Change since v4: - Tested by Tina Zhang. Change since v5: - Add limitation about supporting 32bit full ppgtt. Change since v6: - Change the fallback to 48bit full ppgtt if i915.ppgtt_enable=2. (Zhenyu) Change in v9: - Remove the fixme comment due to no plan for 32bit full ppgtt support. (Zhenyu) - Reorder the patch-set to fix compiling issue with git-bisect. (Zhenyu) - Add print log when forcing guest 48bit full ppgtt. (Zhenyu) v10: - Update against Joonas's has_full_ppgtt and has_full_48bit_ppgtt disconnect change. (Zhenyu) Reviewed-by: Joonas Lahtinen # in v2 Cc: Joonas Lahtinen Cc: Tina Zhang Signed-off-by: Tina Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- drivers/gpu/drm/i915/i915_pvinfo.h | 8 +++++++- drivers/gpu/drm/i915/i915_vgpu.c | 7 +++++++ drivers/gpu/drm/i915/i915_vgpu.h | 3 +++ 5 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d63645a521c4..c38f46fd1fba 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1902,6 +1902,7 @@ struct i915_workarounds { struct i915_virtual_gpu { bool active; + u32 caps; }; /* used in computing the new watermarks state */ diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a5eada1b93c5..ef1881e256f4 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -144,9 +144,9 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; if (intel_vgpu_active(dev_priv)) { - /* emulation is too hard */ + /* GVT-g has no support for 32bit ppgtt */ has_full_ppgtt = false; - has_full_48bit_ppgtt = false; + has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv); } if (!has_aliasing_ppgtt) diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h index 2cfe96d3e5d1..0679a58cdbae 100644 --- a/drivers/gpu/drm/i915/i915_pvinfo.h +++ b/drivers/gpu/drm/i915/i915_pvinfo.h @@ -49,12 +49,18 @@ enum vgt_g2v_type { VGT_G2V_MAX, }; +/* + * VGT capabilities type + */ +#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2) + struct vgt_if { u64 magic; /* VGT_MAGIC */ u16 version_major; u16 version_minor; u32 vgt_id; /* ID of vGT instance */ - u32 rsv1[12]; /* pad to offset 0x40 */ + u32 vgt_caps; /* VGT capabilities */ + u32 rsv1[11]; /* pad to offset 0x40 */ /* * Data structure to describe the balooning info of resources. * Each VM can only have one portion of continuous area for now. diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index cf7a958e4d3c..5fe9f3f39467 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -75,10 +75,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv) return; } + dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps)); + dev_priv->vgpu.active = true; DRM_INFO("Virtual GPU for Intel GVT-g detected.\n"); } +bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv) +{ + return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT; +} + struct _balloon_info_ { /* * There are up to 2 regions per mappable/unmappable graphic diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h index 3c3b2d24e830..b72bd2956b70 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.h +++ b/drivers/gpu/drm/i915/i915_vgpu.h @@ -27,6 +27,9 @@ #include "i915_pvinfo.h" void i915_check_vgpu(struct drm_i915_private *dev_priv); + +bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv); + int intel_vgt_balloon(struct drm_i915_private *dev_priv); void intel_vgt_deballoon(struct drm_i915_private *dev_priv); From 6b3816d69628becb7ff35978aa0751798b4a940a Mon Sep 17 00:00:00 2001 From: Tina Zhang Date: Mon, 14 Aug 2017 15:24:14 +0800 Subject: [PATCH 152/179] drm/i915/gvt: Fix guest i915 full ppgtt blocking issue Guest i915 full ppgtt functionality was blocking by an issue, which would lead to gpu hardware hang. Guest i915 driver may update the ppgtt table just before this workload is going to be submitted to the hardware by device model. This case wasn't handled well by device model before, due to the small time window between removing old ppgtt entry and adding the new one. Errors occur when the workload is executed by hardware during that small time window. This patch is to remove this time window by adding the new ppgtt entry first and then remove the old one. Changes in v2: - Move VGT_CAPS_FULL_PPGTT introduction to patch 2/4. (Joonas) Changes since v2: - Divide the whole patch set into two separate patch series, with one patch in i915 side to check guest i915 full ppgtt capability and enable it when this capability is supported by the device model, and the other one in gvt side which fixs the blocking issue and enables the device model to provide the capability to guest. And this patch focuses on gvt side. (Joonas) - Change the title from "reorder the shadow ppgtt update process by adding entry first" to "Fix guest i915 full ppgtt blocking issue". (Tina) Changes since v3: - Rebase to the latest branch. Changes since v4: - Tested by Tina Zhang. Changes since v5: - Rebase to the latest branch. v6: - Update full 48bit ppgtt definition Cc: Tina Zhang Signed-off-by: Tina Zhang Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/gtt.c | 45 ++++++++++++++++++++------------- drivers/gpu/drm/i915/gvt/vgpu.c | 1 + 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index f862681c70d1..e6dfc3331f4b 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -989,29 +989,26 @@ fail: } static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, - unsigned long index) + struct intel_gvt_gtt_entry *se, unsigned long index) { struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu_shadow_page *sp = &spt->shadow_page; struct intel_vgpu *vgpu = spt->vgpu; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; - struct intel_gvt_gtt_entry e; int ret; - ppgtt_get_shadow_entry(spt, &e, index); - - trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, e.val64, + trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, se->val64, index); - if (!ops->test_present(&e)) + if (!ops->test_present(se)) return 0; - if (ops->get_pfn(&e) == vgpu->gtt.scratch_pt[sp->type].page_mfn) + if (ops->get_pfn(se) == vgpu->gtt.scratch_pt[sp->type].page_mfn) return 0; - if (gtt_type_is_pt(get_next_pt_type(e.type))) { + if (gtt_type_is_pt(get_next_pt_type(se->type))) { struct intel_vgpu_ppgtt_spt *s = - ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e)); + ppgtt_find_shadow_page(vgpu, ops->get_pfn(se)); if (!s) { gvt_vgpu_err("fail to find guest page\n"); ret = -ENXIO; @@ -1021,12 +1018,10 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, if (ret) goto fail; } - ops->set_pfn(&e, vgpu->gtt.scratch_pt[sp->type].page_mfn); - ppgtt_set_shadow_entry(spt, &e, index); return 0; fail: gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", - spt, e.val64, e.type); + spt, se->val64, se->type); return ret; } @@ -1246,22 +1241,37 @@ static int ppgtt_handle_guest_write_page_table( { struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu *vgpu = spt->vgpu; + int type = spt->shadow_page.type; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; + struct intel_gvt_gtt_entry se; int ret; int new_present; new_present = ops->test_present(we); - ret = ppgtt_handle_guest_entry_removal(gpt, index); - if (ret) - goto fail; + /* + * Adding the new entry first and then removing the old one, that can + * guarantee the ppgtt table is validated during the window between + * adding and removal. + */ + ppgtt_get_shadow_entry(spt, &se, index); if (new_present) { ret = ppgtt_handle_guest_entry_add(gpt, we, index); if (ret) goto fail; } + + ret = ppgtt_handle_guest_entry_removal(gpt, &se, index); + if (ret) + goto fail; + + if (!new_present) { + ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn); + ppgtt_set_shadow_entry(spt, &se, index); + } + return 0; fail: gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n", @@ -1333,7 +1343,7 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, struct intel_vgpu *vgpu = spt->vgpu; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; - struct intel_gvt_gtt_entry we; + struct intel_gvt_gtt_entry we, se; unsigned long index; int ret; @@ -1349,7 +1359,8 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, return ret; } else { if (!test_bit(index, spt->post_shadow_bitmap)) { - ret = ppgtt_handle_guest_entry_removal(gpt, index); + ppgtt_get_shadow_entry(spt, &se, index); + ret = ppgtt_handle_guest_entry_removal(gpt, &se, index); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 5b44d123bf24..5896ead8529e 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -43,6 +43,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0; vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0; vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id; + vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT; vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = vgpu_aperture_gmadr_base(vgpu); vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = From 1a92c70ed8053855811d5e8c62e6a14e1d06e4ab Mon Sep 17 00:00:00 2001 From: Manasi Navare Date: Thu, 8 Jun 2017 13:41:02 -0700 Subject: [PATCH 153/179] drm/i915/dp: Generalize intel_dp_link_params function to accept arguments to be validated This function now takes the link rate and lane ocunt to be validated as an argument so that this can be used for validating even the compliance test link parameters. Signed-off-by: Manasi Navare Cc: Ville Syrjala Cc: Jani Nikula Reviewed-by: Jani Nikula Tested-by: Nathan Ciobanu Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/1496954463-18038-1-git-send-email-manasi.d.navare@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5ba8366ff1e5..de2aaad19714 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -334,19 +334,20 @@ static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp, return 0; } -static bool intel_dp_link_params_valid(struct intel_dp *intel_dp) +static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, + uint8_t lane_count) { /* * FIXME: we need to synchronize the current link parameters with * hardware readout. Currently fast link training doesn't work on * boot-up. */ - if (intel_dp->link_rate == 0 || - intel_dp->link_rate > intel_dp->max_link_rate) + if (link_rate == 0 || + link_rate > intel_dp->max_link_rate) return false; - if (intel_dp->lane_count == 0 || - intel_dp->lane_count > intel_dp_max_lane_count(intel_dp)) + if (lane_count == 0 || + lane_count > intel_dp_max_lane_count(intel_dp)) return false; return true; @@ -4275,7 +4276,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) * Validate the cached values of intel_dp->link_rate and * intel_dp->lane_count before attempting to retrain. */ - if (!intel_dp_link_params_valid(intel_dp)) + if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, + intel_dp->lane_count)) return; /* Retrain if Channel EQ or CR not ok */ From 140ef138db07285b9eecf14ae3ee7c0a407ab93a Mon Sep 17 00:00:00 2001 From: Manasi Navare Date: Thu, 8 Jun 2017 13:41:03 -0700 Subject: [PATCH 154/179] drm/i915/dp: Validate the compliance test link parameters Validate the compliance test link parameters when the compliance test dpcd registers are read. Also validate them in compute_config before using them since the max values might have been reduced due to link training fallback. If either the link rate or lane count is invalid, we still bail from using the test parameters since the combination would not work and instead use the fallback values. v2: * Added commit message to explain why we still bail when either of of the params is invalid (Ville Syrjala) * Add reason for validating in the comment (Jani Nikula) * Also check if index >= 0 after validating (Jani Nikula) Signed-off-by: Manasi Navare Cc: Jani Nikula Cc: Ville Syrjala Reviewed-by: Jani Nikula Tested-by: Nathan Ciobanu Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/1496954463-18038-2-git-send-email-manasi.d.navare@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 34 ++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index de2aaad19714..e5f787319725 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1690,12 +1690,18 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { int index; - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - intel_dp->compliance.test_link_rate); - if (index >= 0) - min_clock = max_clock = index; - min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; + /* Validate the compliance test data since max values + * might have changed due to link train fallback. + */ + if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, + intel_dp->compliance.test_lane_count)) { + index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + intel_dp->compliance.test_link_rate); + if (index >= 0) + min_clock = max_clock = index; + min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; + } } DRM_DEBUG_KMS("DP link computation with max lane count %i " "max bw %d pixel clock %iKHz\n", @@ -3976,8 +3982,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { int status = 0; - int min_lane_count = 1; - int link_rate_index, test_link_rate; + int test_link_rate; uint8_t test_lane_count, test_link_bw; /* (DP CTS 1.2) * 4.3.1.11 @@ -3991,10 +3996,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) return DP_TEST_NAK; } test_lane_count &= DP_MAX_LANE_COUNT_MASK; - /* Validate the requested lane count */ - if (test_lane_count < min_lane_count || - test_lane_count > intel_dp->max_link_lane_count) - return DP_TEST_NAK; status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, &test_link_bw); @@ -4002,12 +4003,11 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Link Rate read failed\n"); return DP_TEST_NAK; } - /* Validate the requested link rate */ test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); - link_rate_index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - test_link_rate); - if (link_rate_index < 0) + + /* Validate the requested link rate and lane count */ + if (!intel_dp_link_params_valid(intel_dp, test_link_rate, + test_lane_count)) return DP_TEST_NAK; intel_dp->compliance.test_lane_count = test_lane_count; From d59814a5b4852442e1d03c569a4542f8b08356a7 Mon Sep 17 00:00:00 2001 From: "Balasubramaniam, Hari Chand" Date: Tue, 15 Aug 2017 10:05:46 +0800 Subject: [PATCH 155/179] drm/i915: Initialize 'data' in intel_dsi_dcs_backlight.c variable 'data' may be used uninitialized in this function. thus, 'function dcs_get_backlight' will return unwanted value/fail. Thus, adding NULL initialized to 'data' variable will solve the return failure happening. v2: Change commit message to reflect upstream with proper message Fixes: 90198355b83c ("drm/i915/dsi: Add DCS control for Panel PWM") Cc: Jani Nikula Cc: Daniel Vetter Cc: Yetunde Adebisi Cc: Deepak M Cc: Jani Nikula Signed-off-by: Balasubramaniam, Hari Chand Reviewed-by: Jani Nikula Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/1502762746-191826-1-git-send-email-hari.chand.balasubramaniam@intel.com --- drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c index 6e09ceb71500..150a156f3b1e 100644 --- a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c +++ b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c @@ -46,7 +46,7 @@ static u32 dcs_get_backlight(struct intel_connector *connector) struct intel_encoder *encoder = connector->encoder; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct mipi_dsi_device *dsi_device; - u8 data; + u8 data = 0; enum port port; /* FIXME: Need to take care of 16 bit brightness level */ From 0a445945be6d10c5e6fd5599a27e43b6a7fdf14d Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 14 Aug 2017 18:15:29 +0300 Subject: [PATCH 156/179] drm/i915: Work around GCC anonymous union initialization bug GCC 4.4 can't cope with anonymous union initializers which seems to be a bug in that version (see the Reference) and is fixed since GCC version 4.6. A workaround which is also used elsewhere in the kernel for the same purpose is to wrap the initialization in curly braces, so do the same here. Fixes: b5565a2efc12 ("drm/i915/bxt, glk: Give a proper name to the power well struct phy field") Reference: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10676 Reported-by: Fengguang Wu Cc: Arkadiusz Hiler Signed-off-by: Imre Deak Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170814151530.24154-1-imre.deak@intel.com --- drivers/gpu/drm/i915/intel_runtime_pm.c | 78 +++++++++++++++++-------- 1 file changed, 54 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index e77e84a6fd2f..6e0c9d99bf0a 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1920,7 +1920,9 @@ static struct i915_power_well hsw_power_wells[] = { .domains = HSW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = HSW_DISP_PW_GLOBAL, - .hsw.has_vga = true, + { + .hsw.has_vga = true, + }, }, }; @@ -1937,8 +1939,10 @@ static struct i915_power_well bdw_power_wells[] = { .domains = BDW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = HSW_DISP_PW_GLOBAL, - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), - .hsw.has_vga = true, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + }, }, }; @@ -2080,7 +2084,9 @@ static struct i915_power_well skl_power_wells[] = { .domains = 0, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, - .hsw.has_fuses = true, + { + .hsw.has_fuses = true, + }, }, { .name = "MISC IO power well", @@ -2100,9 +2106,11 @@ static struct i915_power_well skl_power_wells[] = { .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), - .hsw.has_vga = true, - .hsw.has_fuses = true, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "DDI A/E IO power well", @@ -2143,7 +2151,9 @@ static struct i915_power_well bxt_power_wells[] = { .domains = 0, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, - .hsw.has_fuses = true, + { + .hsw.has_fuses = true, + }, }, { .name = "DC off", @@ -2156,23 +2166,29 @@ static struct i915_power_well bxt_power_wells[] = { .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), - .hsw.has_vga = true, - .hsw.has_fuses = true, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "dpio-common-a", .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .bxt.phy = DPIO_PHY1, + { + .bxt.phy = DPIO_PHY1, + }, }, { .name = "dpio-common-bc", .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .bxt.phy = DPIO_PHY0, + { + .bxt.phy = DPIO_PHY0, + }, }, }; @@ -2190,7 +2206,9 @@ static struct i915_power_well glk_power_wells[] = { .domains = 0, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, - .hsw.has_fuses = true, + { + .hsw.has_fuses = true, + }, }, { .name = "DC off", @@ -2203,30 +2221,38 @@ static struct i915_power_well glk_power_wells[] = { .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), - .hsw.has_vga = true, - .hsw.has_fuses = true, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "dpio-common-a", .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .bxt.phy = DPIO_PHY1, + { + .bxt.phy = DPIO_PHY1, + }, }, { .name = "dpio-common-b", .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .bxt.phy = DPIO_PHY0, + { + .bxt.phy = DPIO_PHY0, + }, }, { .name = "dpio-common-c", .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = GLK_DPIO_CMN_C, - .bxt.phy = DPIO_PHY2, + { + .bxt.phy = DPIO_PHY2, + }, }, { .name = "AUX A", @@ -2280,7 +2306,9 @@ static struct i915_power_well cnl_power_wells[] = { .domains = 0, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, - .hsw.has_fuses = true, + { + .hsw.has_fuses = true, + }, }, { .name = "AUX A", @@ -2317,9 +2345,11 @@ static struct i915_power_well cnl_power_wells[] = { .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), - .hsw.has_vga = true, - .hsw.has_fuses = true, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "DDI A IO power well", From 9c3a16c887f0f8f62813d841f028eabc153581f3 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 14 Aug 2017 18:15:30 +0300 Subject: [PATCH 157/179] drm/i915/hsw+: Add support for multiple power well regs Future platforms increase the number of power wells which require additional control registers. A convenient way to select the correct register is to use the high bits of the power well ID as index. This patch only prepares for this, while upcoming platform enabling patches will add the actual new power well IDs and corresponding power well control registers. Cc: Paulo Zanoni Cc: Animesh Manna Cc: Rakshmi Bhatia Signed-off-by: Imre Deak Reviewed-by: Animesh Manna Reviewed-by: Rakshmi Bhatia Link: https://patchwork.freedesktop.org/patch/msgid/20170814151530.24154-2-imre.deak@intel.com --- drivers/gpu/drm/i915/gvt/handlers.c | 26 ++++++++++++----- drivers/gpu/drm/i915/i915_reg.h | 32 ++++++++++++++++----- drivers/gpu/drm/i915/intel_display.c | 6 ++-- drivers/gpu/drm/i915/intel_runtime_pm.c | 37 +++++++++++++------------ 4 files changed, 68 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index d85264d48585..9220a756ecfc 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2252,10 +2252,17 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); MMIO_D(GEN6_PMINTRMSK, D_ALL); - MMIO_DH(HSW_PWR_WELL_BIOS, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_DRIVER, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_DEBUG, D_BDW, NULL, power_well_ctl_mmio_write); + /* + * Use an arbitrary power well controlled by the PWR_WELL_CTL + * register. + */ + MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); @@ -2645,9 +2652,14 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, dp_aux_ch_ctl_mmio_write); - MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS); - MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL, - skl_power_well_ctl_write); + /* + * Use an arbitrary power well controlled by the PWR_WELL_CTL + * register. + */ + MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); + MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, + skl_power_well_ctl_write); + MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write); MMIO_D(0xa210, D_SKL_PLUS); MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 44b8da19a2a0..b2d785969d17 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1254,13 +1254,13 @@ enum i915_power_well_id { /* * HSW/BDW - * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) */ HSW_DISP_PW_GLOBAL = 15, /* * GEN9+ - * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) */ SKL_DISP_PW_MISC_IO = 0, SKL_DISP_PW_DDI_A_E, @@ -8189,11 +8189,29 @@ enum { #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) /* HSW Power Wells */ -#define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ -#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ -#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ -#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ -#define _HSW_PW_SHIFT(pw) ((pw) * 2) +#define _HSW_PWR_WELL_CTL1 0x45400 +#define _HSW_PWR_WELL_CTL2 0x45404 +#define _HSW_PWR_WELL_CTL3 0x45408 +#define _HSW_PWR_WELL_CTL4 0x4540C + +/* + * Each power well control register contains up to 16 (request, status) HW + * flag tuples. The register index and HW flag shift is determined by the + * power well ID (see i915_power_well_id). There are 4 possible sources of + * power well requests each source having its own set of control registers: + * BIOS, DRIVER, KVMR, DEBUG. + */ +#define _HSW_PW_REG_IDX(pw) ((pw) >> 4) +#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2) +/* TODO: Add all PWR_WELL_CTL registers below for new platforms */ +#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL1)) +#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL2)) +#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3) +#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL4)) + #define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) #define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index decf5da63950..29926244f4f2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8783,7 +8783,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", pipe_name(crtc->pipe)); - I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); + I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), + "Display power well on\n"); I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); @@ -15348,7 +15349,8 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) return NULL; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); + error->power_well_driver = + I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)); for_each_pipe(dev_priv, i) { error->pipe[i].power_domain_on = diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 6e0c9d99bf0a..b66d8e136aa3 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -307,7 +307,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ WARN_ON(intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, + HSW_PWR_WELL_CTL_DRIVER(id), HSW_PWR_WELL_CTL_STATE(id), HSW_PWR_WELL_CTL_STATE(id), 1)); @@ -319,10 +319,10 @@ static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); u32 ret; - ret = I915_READ(HSW_PWR_WELL_BIOS) & req_mask ? 1 : 0; - ret |= I915_READ(HSW_PWR_WELL_DRIVER) & req_mask ? 2 : 0; - ret |= I915_READ(HSW_PWR_WELL_KVMR) & req_mask ? 4 : 0; - ret |= I915_READ(HSW_PWR_WELL_DEBUG) & req_mask ? 8 : 0; + ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; return ret; } @@ -343,7 +343,7 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, * Skip the wait in case any of the request bits are set and print a * diagnostic message. */ - wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) & + wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & HSW_PWR_WELL_CTL_STATE(id))) || (reqs = hsw_power_well_requesters(dev_priv, id)), 1); if (disabled) @@ -384,8 +384,8 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); } - val = I915_READ(HSW_PWR_WELL_DRIVER); - I915_WRITE(HSW_PWR_WELL_DRIVER, val | HSW_PWR_WELL_CTL_REQ(id)); + val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); hsw_wait_for_power_well_enable(dev_priv, power_well); if (wait_fuses) @@ -403,8 +403,9 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); - val = I915_READ(HSW_PWR_WELL_DRIVER); - I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id)); + val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), + val & ~HSW_PWR_WELL_CTL_REQ(id)); hsw_wait_for_power_well_disable(dev_priv, power_well); } @@ -419,17 +420,19 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, enum i915_power_well_id id = power_well->id; u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); - return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; + return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; } static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) { + enum i915_power_well_id id = SKL_DISP_PW_2; + WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), "DC9 already programmed to be enabled.\n"); WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, "DC5 still not disabled to enable DC9.\n"); - WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER) & - HSW_PWR_WELL_CTL_REQ(SKL_DISP_PW_2), + WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & + HSW_PWR_WELL_CTL_REQ(id), "Power well 2 on.\n"); WARN_ONCE(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); @@ -630,15 +633,15 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, { enum i915_power_well_id id = power_well->id; u32 mask = HSW_PWR_WELL_CTL_REQ(id); - u32 bios_req = I915_READ(HSW_PWR_WELL_BIOS); + u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); /* Take over the request bit if set by BIOS. */ if (bios_req & mask) { - u32 drv_req = I915_READ(HSW_PWR_WELL_DRIVER); + u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); if (!(drv_req & mask)) - I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask); - I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); + I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); } } From b8f55be64453ea77fc51bff6cd0d906d18ce1cd2 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 11 Aug 2017 12:11:16 +0100 Subject: [PATCH 158/179] drm/i915: Split obj->cache_coherent to track r/w Another month, another story in the cache coherency saga. This time, we come to the realisation that i915_gem_object_is_coherent() has been reporting whether we can read from the target without requiring a cache invalidate; but we were using it in places for testing whether we could write into the object without requiring a cache flush. So split the tracking into two, one to decide before reads, one after writes. See commit e27ab73d17ef ("drm/i915: Mark CPU cache as dirty on every transition for CPU writes") for the previous entry in this saga. v2: Be verbose v3: Remove unused function (i915_gem_object_is_coherent) v4: Fix inverted coherency check prior to execbuf (from v2) v5: Add comment for nasty code where we are optimising on gcc's behalf. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101109 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101555 Testcase: igt/kms_mmap_write_crc Testcase: igt/kms_pwrite_crc Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Cc: Dongwon Kim Cc: Matt Roper Cc: Joonas Lahtinen Cc: Mika Kuoppala Tested-by: Maarten Lankhorst Acked-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170811111116.10373-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 --- drivers/gpu/drm/i915/i915_gem.c | 25 +++++----- drivers/gpu/drm/i915/i915_gem_clflush.c | 3 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 +++++- drivers/gpu/drm/i915/i915_gem_internal.c | 7 +-- drivers/gpu/drm/i915/i915_gem_object.c | 48 +++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_object.h | 9 +++- drivers/gpu/drm/i915/i915_gem_stolen.c | 5 +- drivers/gpu/drm/i915/i915_gem_userptr.c | 4 +- .../gpu/drm/i915/selftests/huge_gem_object.c | 6 +-- 11 files changed, 96 insertions(+), 32 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gem_object.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f8227318dcaf..892f52b53060 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -39,6 +39,7 @@ i915-y += i915_cmd_parser.o \ i915_gem_gtt.o \ i915_gem_internal.o \ i915_gem.o \ + i915_gem_object.o \ i915_gem_render_state.o \ i915_gem_request.o \ i915_gem_shrinker.o \ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5aa214a05c51..9e5e3ca722cd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4322,10 +4322,4 @@ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, struct io_mapping *iomap); -static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj) -{ - return (obj->cache_level != I915_CACHE_NONE || - HAS_LLC(to_i915(obj->base.dev))); -} - #endif diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 000a764ee8d9..887fff281f4e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -52,7 +52,7 @@ static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) if (obj->cache_dirty) return false; - if (!obj->cache_coherent) + if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) return true; return obj->pin_display; @@ -253,7 +253,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, if (needs_clflush && (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && - !obj->cache_coherent) + !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) drm_clflush_sg(pages); __start_cpu_write(obj); @@ -800,7 +800,8 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, if (ret) return ret; - if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { + if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || + !static_cpu_has(X86_FEATURE_CLFLUSH)) { ret = i915_gem_object_set_to_cpu_domain(obj, false); if (ret) goto err_unpin; @@ -852,7 +853,8 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, if (ret) return ret; - if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { + if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || + !static_cpu_has(X86_FEATURE_CLFLUSH)) { ret = i915_gem_object_set_to_cpu_domain(obj, true); if (ret) goto err_unpin; @@ -3673,8 +3675,7 @@ restart: list_for_each_entry(vma, &obj->vma_list, obj_link) vma->node.color = cache_level; - obj->cache_level = cache_level; - obj->cache_coherent = i915_gem_object_is_coherent(obj); + i915_gem_object_set_cache_coherency(obj, cache_level); obj->cache_dirty = true; /* Always invalidate stale cachelines */ return 0; @@ -4279,6 +4280,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) { struct drm_i915_gem_object *obj; struct address_space *mapping; + unsigned int cache_level; gfp_t mask; int ret; @@ -4317,7 +4319,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(dev_priv)) { + if (HAS_LLC(dev_priv)) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than @@ -4330,12 +4332,11 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) * However, we maintain the display planes as UC, and so * need to rebind when first used as such. */ - obj->cache_level = I915_CACHE_LLC; - } else - obj->cache_level = I915_CACHE_NONE; + cache_level = I915_CACHE_LLC; + else + cache_level = I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + i915_gem_object_set_cache_coherency(obj, cache_level); trace_i915_gem_object_create(obj); diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c index 348b29a845c9..8a04d33055be 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c @@ -139,7 +139,8 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, * snooping behaviour occurs naturally as the result of our domain * tracking. */ - if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent) + if (!(flags & I915_CLFLUSH_FORCE) && + obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) return false; trace_i915_gem_object_clflush(obj); diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 5fa44767c29e..99520b2fac7c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1842,7 +1842,19 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) eb->request->capture_list = capture; } - if (unlikely(obj->cache_dirty && !obj->cache_coherent)) { + /* + * If the GPU is not _reading_ through the CPU cache, we need + * to make sure that any writes (both previous GPU writes from + * before a change in snooping levels and normal CPU writes) + * caught in that cache are flushed to main memory. + * + * We want to say + * obj->cache_dirty && + * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) + * but gcc's optimiser doesn't handle that as well and emits + * two jumps instead of one. Maybe one day... + */ + if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) { if (i915_gem_clflush_object(obj, 0)) entry->flags &= ~EXEC_OBJECT_ASYNC; } diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c b/drivers/gpu/drm/i915/i915_gem_internal.c index 568bf83af1f5..c1f64ddaf8aa 100644 --- a/drivers/gpu/drm/i915/i915_gem_internal.c +++ b/drivers/gpu/drm/i915/i915_gem_internal.c @@ -174,6 +174,7 @@ i915_gem_object_create_internal(struct drm_i915_private *i915, phys_addr_t size) { struct drm_i915_gem_object *obj; + unsigned int cache_level; GEM_BUG_ON(!size); GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE)); @@ -190,9 +191,9 @@ i915_gem_object_create_internal(struct drm_i915_private *i915, obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); return obj; } diff --git a/drivers/gpu/drm/i915/i915_gem_object.c b/drivers/gpu/drm/i915/i915_gem_object.c new file mode 100644 index 000000000000..aab8cdd80e6d --- /dev/null +++ b/drivers/gpu/drm/i915/i915_gem_object.c @@ -0,0 +1,48 @@ +/* + * Copyright © 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include "i915_drv.h" +#include "i915_gem_object.h" + +/** + * Mark up the object's coherency levels for a given cache_level + * @obj: #drm_i915_gem_object + * @cache_level: cache level + */ +void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, + unsigned int cache_level) +{ + obj->cache_level = cache_level; + + if (cache_level != I915_CACHE_NONE) + obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ | + I915_BO_CACHE_COHERENT_FOR_WRITE); + else if (HAS_LLC(to_i915(obj->base.dev))) + obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ; + else + obj->cache_coherent = 0; + + obj->cache_dirty = + !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE); +} diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h index 5b19a4916a4d..3baa341432db 100644 --- a/drivers/gpu/drm/i915/i915_gem_object.h +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -33,8 +33,11 @@ #include +#include "i915_gem_request.h" #include "i915_selftest.h" +struct drm_i915_gem_object; + struct drm_i915_gem_object_ops { unsigned int flags; #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0) @@ -118,8 +121,10 @@ struct drm_i915_gem_object { */ unsigned long gt_ro:1; unsigned int cache_level:3; + unsigned int cache_coherent:2; +#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) +#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) unsigned int cache_dirty:1; - unsigned int cache_coherent:1; atomic_t frontbuffer_bits; unsigned int frontbuffer_ggtt_origin; /* write once */ @@ -391,6 +396,8 @@ i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) return engine; } +void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, + unsigned int cache_level); void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj); #endif diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index c11c915382e7..507c9f0d8df1 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -580,6 +580,7 @@ _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, struct drm_mm_node *stolen) { struct drm_i915_gem_object *obj; + unsigned int cache_level; obj = i915_gem_object_alloc(dev_priv); if (obj == NULL) @@ -590,8 +591,8 @@ _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, obj->stolen = stolen; obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT; - obj->cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = true; /* assumptions! more like cache_oblivious */ + cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); if (i915_gem_object_pin_pages(obj)) goto cleanup; diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c index ccd09e8419f5..f152a38d7079 100644 --- a/drivers/gpu/drm/i915/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c @@ -804,9 +804,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file i915_gem_object_init(obj, &i915_gem_userptr_ops); obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = I915_CACHE_LLC; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); obj->userptr.ptr = args->user_ptr; obj->userptr.read_only = !!(args->flags & I915_USERPTR_READ_ONLY); diff --git a/drivers/gpu/drm/i915/selftests/huge_gem_object.c b/drivers/gpu/drm/i915/selftests/huge_gem_object.c index caf76af36aba..c5c7e8efbdd3 100644 --- a/drivers/gpu/drm/i915/selftests/huge_gem_object.c +++ b/drivers/gpu/drm/i915/selftests/huge_gem_object.c @@ -111,6 +111,7 @@ huge_gem_object(struct drm_i915_private *i915, dma_addr_t dma_size) { struct drm_i915_gem_object *obj; + unsigned int cache_level; GEM_BUG_ON(!phys_size || phys_size > dma_size); GEM_BUG_ON(!IS_ALIGNED(phys_size, PAGE_SIZE)); @@ -128,9 +129,8 @@ huge_gem_object(struct drm_i915_private *i915, obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); obj->scratch = phys_size; return obj; From b805014897fd2d9e59f2a79ebe8c65a254234816 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 11 Aug 2017 11:57:31 +0100 Subject: [PATCH 159/179] drm/i915: Handle full s64 precision for wait-ioctl The wait-ioctl is optionally supplied a timeout with nanosecond precision in a s64 field. We use nsecs_to_jiffies64() to convert that into the jiffies consumed by the scheduler, but internally nsecs_to_jiffies64() does not guard against overflow (as it's purpose is for use by the scheduler and not drivers!). So we must guard against the overflow ourselves, and in the process note that we may then return much earlier than the timeout selected by the user, so don't report ETIME unless we do hit the timeout. (Woe betold us though if the user waits for a year (32bit) and the request is still not complete!) v2: Refine overflow detection (to not include an overffow itself) Reported-by: Jason Ekstrand Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170811105731.9482-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 5 +++++ drivers/gpu/drm/i915/i915_gem.c | 6 +++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9e5e3ca722cd..6c25c8520c87 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4176,6 +4176,11 @@ static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) { + /* nsecs_to_jiffies64() does not guard against overflow */ + if (NSEC_PER_SEC % HZ && + div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) + return MAX_JIFFY_OFFSET; + return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); } diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 887fff281f4e..5a3f3bb3f21d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3286,7 +3286,7 @@ static unsigned long to_wait_timeout(s64 timeout_ns) * -ERESTARTSYS: signal interrupted the wait * -ENONENT: object doesn't exist * Also possible, but rare: - * -EAGAIN: GPU wedged + * -EAGAIN: incomplete, restart syscall * -ENOMEM: damn * -ENODEV: Internal IRQ fail * -E?: The add request failed @@ -3334,6 +3334,10 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) */ if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) args->timeout_ns = 0; + + /* Asked to wait beyond the jiffie/scheduler precision? */ + if (ret == -ETIME && args->timeout_ns) + ret = -EAGAIN; } i915_gem_object_put(obj); From cf6e7bac6357f0ccca51fcb5eb325e724f6b4c95 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Tue, 15 Aug 2017 15:57:33 +0100 Subject: [PATCH 160/179] drm/i915: Add support for drm syncobjs This commit adds support for waiting on or signaling DRM syncobjs as part of execbuf. It does so by hijacking the currently unused cliprects pointer to instead point to an array of i915_gem_exec_fence structs which containe a DRM syncobj and a flags parameter which specifies whether to wait on it or to signal it. This implementation theoretically allows for both flags to be set in which case it waits on the dma_fence that was in the syncobj and then immediately replaces it with the dma_fence from the current execbuf. v2: - Rebase on new syncobj API v3: - Pull everything out into helpers - Do all allocation in gem_execbuffer2 - Pack the flags in the bottom 2 bits of the drm_syncobj* v4: - Prevent a potential race on syncobj->fence Testcase: igt/gem_exec_fence/syncobj* Signed-off-by: Jason Ekstrand Link: https://patchwork.freedesktop.org/patch/msgid/1499289202-25441-1-git-send-email-jason.ekstrand@intel.com Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170815145733.4562-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 152 ++++++++++++++++++++- include/uapi/drm/i915_drm.h | 31 ++++- 3 files changed, 178 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 25de4a95526b..43100229613c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -388,6 +388,7 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_EXEC_FENCE: case I915_PARAM_HAS_EXEC_CAPTURE: case I915_PARAM_HAS_EXEC_BATCH_FIRST: + case I915_PARAM_HAS_EXEC_FENCE_ARRAY: /* For the time being all of these are always true; * if some supported hardware does not have one of these * features this value needs to be provided from @@ -2739,7 +2740,7 @@ static struct drm_driver driver = { */ .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | - DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC, + DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ, .release = i915_driver_release, .open = i915_driver_open, .lastclose = i915_driver_lastclose, diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 99520b2fac7c..8e8bc7aefd9c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -32,6 +32,7 @@ #include #include +#include #include #include "i915_drv.h" @@ -1896,8 +1897,10 @@ static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) return false; /* Kernel clipping was a DRI1 misfeature */ - if (exec->num_cliprects || exec->cliprects_ptr) - return false; + if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) { + if (exec->num_cliprects || exec->cliprects_ptr) + return false; + } if (exec->DR4 == 0xffffffff) { DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); @@ -2128,11 +2131,131 @@ eb_select_engine(struct drm_i915_private *dev_priv, return engine; } +static void +__free_fence_array(struct drm_syncobj **fences, unsigned int n) +{ + while (n--) + drm_syncobj_put(ptr_mask_bits(fences[n], 2)); + kvfree(fences); +} + +static struct drm_syncobj ** +get_fence_array(struct drm_i915_gem_execbuffer2 *args, + struct drm_file *file) +{ + const unsigned int nfences = args->num_cliprects; + struct drm_i915_gem_exec_fence __user *user; + struct drm_syncobj **fences; + unsigned int n; + int err; + + if (!(args->flags & I915_EXEC_FENCE_ARRAY)) + return NULL; + + if (nfences > SIZE_MAX / sizeof(*fences)) + return ERR_PTR(-EINVAL); + + user = u64_to_user_ptr(args->cliprects_ptr); + if (!access_ok(VERIFY_READ, user, nfences * 2 * sizeof(u32))) + return ERR_PTR(-EFAULT); + + fences = kvmalloc_array(args->num_cliprects, sizeof(*fences), + __GFP_NOWARN | GFP_TEMPORARY); + if (!fences) + return ERR_PTR(-ENOMEM); + + for (n = 0; n < nfences; n++) { + struct drm_i915_gem_exec_fence fence; + struct drm_syncobj *syncobj; + + if (__copy_from_user(&fence, user++, sizeof(fence))) { + err = -EFAULT; + goto err; + } + + syncobj = drm_syncobj_find(file, fence.handle); + if (!syncobj) { + DRM_DEBUG("Invalid syncobj handle provided\n"); + err = -ENOENT; + goto err; + } + + fences[n] = ptr_pack_bits(syncobj, fence.flags, 2); + } + + return fences; + +err: + __free_fence_array(fences, n); + return ERR_PTR(err); +} + +static void +put_fence_array(struct drm_i915_gem_execbuffer2 *args, + struct drm_syncobj **fences) +{ + if (fences) + __free_fence_array(fences, args->num_cliprects); +} + +static int +await_fence_array(struct i915_execbuffer *eb, + struct drm_syncobj **fences) +{ + const unsigned int nfences = eb->args->num_cliprects; + unsigned int n; + int err; + + for (n = 0; n < nfences; n++) { + struct drm_syncobj *syncobj; + struct dma_fence *fence; + unsigned int flags; + + syncobj = ptr_unpack_bits(fences[n], &flags, 2); + if (!(flags & I915_EXEC_FENCE_WAIT)) + continue; + + rcu_read_lock(); + fence = dma_fence_get_rcu_safe(&syncobj->fence); + rcu_read_unlock(); + if (!fence) + return -EINVAL; + + err = i915_gem_request_await_dma_fence(eb->request, fence); + dma_fence_put(fence); + if (err < 0) + return err; + } + + return 0; +} + +static void +signal_fence_array(struct i915_execbuffer *eb, + struct drm_syncobj **fences) +{ + const unsigned int nfences = eb->args->num_cliprects; + struct dma_fence * const fence = &eb->request->fence; + unsigned int n; + + for (n = 0; n < nfences; n++) { + struct drm_syncobj *syncobj; + unsigned int flags; + + syncobj = ptr_unpack_bits(fences[n], &flags, 2); + if (!(flags & I915_EXEC_FENCE_SIGNAL)) + continue; + + drm_syncobj_replace_fence(syncobj, fence); + } +} + static int i915_gem_do_execbuffer(struct drm_device *dev, struct drm_file *file, struct drm_i915_gem_execbuffer2 *args, - struct drm_i915_gem_exec_object2 *exec) + struct drm_i915_gem_exec_object2 *exec, + struct drm_syncobj **fences) { struct i915_execbuffer eb; struct dma_fence *in_fence = NULL; @@ -2318,6 +2441,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_request; } + if (fences) { + err = await_fence_array(&eb, fences); + if (err) + goto err_request; + } + if (out_fence_fd != -1) { out_fence = sync_file_create(&eb.request->fence); if (!out_fence) { @@ -2341,6 +2470,9 @@ err_request: __i915_add_request(eb.request, err == 0); add_to_client(eb.request, file); + if (fences) + signal_fence_array(&eb, fences); + if (out_fence) { if (err == 0) { fd_install(out_fence_fd, out_fence->file); @@ -2442,7 +2574,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, exec2_list[i].flags = 0; } - err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list); + err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL); if (exec2.flags & __EXEC_HAS_RELOC) { struct drm_i915_gem_exec_object __user *user_exec_list = u64_to_user_ptr(args->buffers_ptr); @@ -2474,6 +2606,7 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, const size_t sz = sizeof(struct drm_i915_gem_exec_object2); struct drm_i915_gem_execbuffer2 *args = data; struct drm_i915_gem_exec_object2 *exec2_list; + struct drm_syncobj **fences = NULL; int err; if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) { @@ -2500,7 +2633,15 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, return -EFAULT; } - err = i915_gem_do_execbuffer(dev, file, args, exec2_list); + if (args->flags & I915_EXEC_FENCE_ARRAY) { + fences = get_fence_array(args, file); + if (IS_ERR(fences)) { + kvfree(exec2_list); + return PTR_ERR(fences); + } + } + + err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences); /* * Now that we have begun execution of the batchbuffer, we ignore @@ -2530,6 +2671,7 @@ end_user: } args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS; + put_fence_array(args, fences); kvfree(exec2_list); return err; } diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index ce3833fa1e06..6598fb76d2c2 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -435,6 +435,11 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of + * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. + */ +#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 + typedef struct drm_i915_getparam { __s32 param; /* @@ -816,6 +821,17 @@ struct drm_i915_gem_exec_object2 { __u64 rsvd2; }; +struct drm_i915_gem_exec_fence { + /** + * User's handle for a drm_syncobj to wait on or signal. + */ + __u32 handle; + +#define I915_EXEC_FENCE_WAIT (1<<0) +#define I915_EXEC_FENCE_SIGNAL (1<<1) + __u32 flags; +}; + struct drm_i915_gem_execbuffer2 { /** * List of gem_exec_object2 structs @@ -830,7 +846,11 @@ struct drm_i915_gem_execbuffer2 { __u32 DR1; __u32 DR4; __u32 num_cliprects; - /** This is a struct drm_clip_rect *cliprects */ + /** + * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY + * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a + * struct drm_i915_gem_exec_fence *fences. + */ __u64 cliprects_ptr; #define I915_EXEC_RING_MASK (7<<0) #define I915_EXEC_DEFAULT (0<<0) @@ -931,7 +951,14 @@ struct drm_i915_gem_execbuffer2 { * element). */ #define I915_EXEC_BATCH_FIRST (1<<18) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_BATCH_FIRST<<1)) + +/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr + * define an array of i915_gem_exec_fence structures which specify a set of + * dma fences to wait upon or signal. + */ +#define I915_EXEC_FENCE_ARRAY (1<<19) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ From dc911f5bd8aacfcf8aabd5c26c88e04c837a938e Mon Sep 17 00:00:00 2001 From: Jim Bride Date: Wed, 9 Aug 2017 12:48:53 -0700 Subject: [PATCH 161/179] drm/i915/edp: Allow alternate fixed mode for eDP if available. Some fixed resolution panels actually support more than one mode, with the only thing different being the refresh rate. Having this alternate mode available to us is desirable, because it allows us to test PSR on panels whose setup time at the preferred mode is too long. With this patch we allow the use of the alternate mode if it's available and it was specifically requested. v2 and v3: Rebase v4: * Fix up some leaky mode stuff (Chris) * Rebase v5: * Fix a NULL pointer derefrence (David Weinehall) v6: * Whitespace / spelling / checkpatch clean-up; no functional change. (David) * Rebase Cc: David Weinehall Cc: Rodrigo Vivi Cc: Paulo Zanoni Cc: Jani Nikula Cc: Chris Wilson Reviewed-by: David Weinehall Signed-off-by: Jim Bride Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1502308133-26892-1-git-send-email-jim.bride@linux.intel.com --- drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_dsi.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 3 ++- drivers/gpu/drm/i915/intel_panel.c | 6 +++++ 6 files changed, 45 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index e5f787319725..4fd4853b2250 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1619,6 +1619,23 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, return bpp; } +static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1, + struct drm_display_mode *m2) +{ + bool bres = false; + + if (m1 && m2) + bres = (m1->hdisplay == m2->hdisplay && + m1->hsync_start == m2->hsync_start && + m1->hsync_end == m2->hsync_end && + m1->htotal == m2->htotal && + m1->vdisplay == m2->vdisplay && + m1->vsync_start == m2->vsync_start && + m1->vsync_end == m2->vsync_end && + m1->vtotal == m2->vtotal); + return bres; +} + bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, @@ -1665,8 +1682,16 @@ intel_dp_compute_config(struct intel_encoder *encoder, pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { - intel_fixed_panel_mode(intel_connector->panel.fixed_mode, - adjusted_mode); + struct drm_display_mode *panel_mode = + intel_connector->panel.alt_fixed_mode; + struct drm_display_mode *req_mode = &pipe_config->base.mode; + + if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) + panel_mode = intel_connector->panel.fixed_mode; + + drm_mode_debug_printmodeline(panel_mode); + + intel_fixed_panel_mode(panel_mode, adjusted_mode); if (INTEL_GEN(dev_priv) >= 9) { int ret; @@ -5794,6 +5819,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct drm_display_mode *fixed_mode = NULL; + struct drm_display_mode *alt_fixed_mode = NULL; struct drm_display_mode *downclock_mode = NULL; bool has_dpcd; struct drm_display_mode *scan; @@ -5849,13 +5875,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, } intel_connector->edid = edid; - /* prefer fixed mode from EDID if available */ + /* prefer fixed mode from EDID if available, save an alt mode also */ list_for_each_entry(scan, &connector->probed_modes, head) { if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { fixed_mode = drm_mode_duplicate(dev, scan); downclock_mode = intel_dp_drrs_init( intel_connector, fixed_mode); - break; + } else if (!alt_fixed_mode) { + alt_fixed_mode = drm_mode_duplicate(dev, scan); } } @@ -5892,7 +5919,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, pipe_name(pipe)); } - intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); + intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode, + downclock_mode); intel_connector->panel.backlight.power = intel_edp_backlight_power; intel_panel_setup_backlight(connector, pipe); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index b1dd5d6ed0f3..fa47285918f4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -265,6 +265,7 @@ struct intel_encoder { struct intel_panel { struct drm_display_mode *fixed_mode; + struct drm_display_mode *alt_fixed_mode; struct drm_display_mode *downclock_mode; /* backlight */ @@ -1678,6 +1679,7 @@ void intel_overlay_reset(struct drm_i915_private *dev_priv); /* intel_panel.c */ int intel_panel_init(struct intel_panel *panel, struct drm_display_mode *fixed_mode, + struct drm_display_mode *alt_fixed_mode, struct drm_display_mode *downclock_mode); void intel_panel_fini(struct intel_panel *panel); void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index b0b3adf016f8..f0c11aec5ea5 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -1849,7 +1849,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv) connector->display_info.width_mm = fixed_mode->width_mm; connector->display_info.height_mm = fixed_mode->height_mm; - intel_panel_init(&intel_connector->panel, fixed_mode, NULL); + intel_panel_init(&intel_connector->panel, fixed_mode, NULL, NULL); intel_panel_setup_backlight(connector, INVALID_PIPE); intel_dsi_add_properties(intel_connector); diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index baf369d2de30..c0a027274c06 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -552,7 +552,7 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) */ intel_panel_init(&intel_connector->panel, intel_dvo_get_current_mode(connector), - NULL); + NULL, NULL); intel_dvo->panel_wants_dither = true; } diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 61d557948e21..8e215777c7f4 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -1138,7 +1138,8 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) out: mutex_unlock(&dev->mode_config.mutex); - intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); + intel_panel_init(&intel_connector->panel, fixed_mode, NULL, + downclock_mode); intel_panel_setup_backlight(connector, INVALID_PIPE); lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 88018fccdb9f..a17b1de7d7e0 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -1920,11 +1920,13 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) int intel_panel_init(struct intel_panel *panel, struct drm_display_mode *fixed_mode, + struct drm_display_mode *alt_fixed_mode, struct drm_display_mode *downclock_mode) { intel_panel_init_backlight_funcs(panel); panel->fixed_mode = fixed_mode; + panel->alt_fixed_mode = alt_fixed_mode; panel->downclock_mode = downclock_mode; return 0; @@ -1938,6 +1940,10 @@ void intel_panel_fini(struct intel_panel *panel) if (panel->fixed_mode) drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); + if (panel->alt_fixed_mode) + drm_mode_destroy(intel_connector->base.dev, + panel->alt_fixed_mode); + if (panel->downclock_mode) drm_mode_destroy(intel_connector->base.dev, panel->downclock_mode); From 4e34935fcf691b2f553fdc34502d649bf979a06f Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Tue, 15 Aug 2017 16:25:39 -0700 Subject: [PATCH 162/179] drm/i915/cnl: Setup PAT Index. Different from previous platforms, on CNL+ there's separated registers for separated indexes. v2: Remove comments regarding uncertainty around the table. v3: Remove extra line (by Ben) Cc: Clint Taylor Cc: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi Reviewed-by: Ben Widawsky Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/i915_gem_gtt.c | 26 ++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index ef1881e256f4..d60f38adc4c4 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2742,6 +2742,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return 0; } +static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv) +{ + /* XXX: spec is unclear if this is still needed for CNL+ */ + if (!USES_PPGTT(dev_priv)) { + I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC); + return; + } + + I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC); + I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); + I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); + I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC); + I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); + I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); + I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); + I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); +} + /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability * bits. When using advanced contexts each context stores its own PAT, but * writing this data shouldn't be harmful even in those cases. */ @@ -2856,7 +2874,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; - if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + cnl_setup_private_ppat(dev_priv); + else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); @@ -3138,7 +3158,9 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) ggtt->base.closed = false; if (INTEL_GEN(dev_priv) >= 8) { - if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + cnl_setup_private_ppat(dev_priv); + else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2d785969d17..ed7cd9ee2c2a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2336,6 +2336,7 @@ enum i915_power_well_id { #define DONE_REG _MMIO(0x40b0) #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) +#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + index*4) #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) From b5273d72750555a673040070bfb23c454a7cd3ef Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 11 Aug 2017 14:39:07 +0300 Subject: [PATCH 163/179] drm/i915/vbt: ignore extraneous child devices for a port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ever since we've parsed VBT child devices, starting from 6acab15a7b0d ("drm/i915: use the HDMI DDI buffer translations from VBT"), we've ignored the child device information if more than one child device references the same port. The rationale for this seems lost in time. Since commit 311a20949f04 ("drm/i915: don't init DP or HDMI when not supported by DDI port") we started using this information more to skip HDMI/DP init if the port wasn't there per VBT child devices. However, at the same time it added port defaults without further explanation. Thus, if the child device info was skipped due to multiple child devices referencing the same port, the device info would be retrieved from the somewhat arbitrary defaults. Finally, when commit bb1d132935c2 ("drm/i915/vbt: split out defaults that are set when there is no VBT") stopped initializing the defaults whenever VBT is present, thus trusting the VBT more, we stopped initializing ports which were referenced by more than one child device. Apparently at least Asus UX305UA, UX305U, and UX306U laptops have VBT child device blocks which cause this behaviour. Arguably they were shipped with a broken VBT. Relax the rules for multiple references to the same port, and use the first child device info to reference a port. Retain the logic to debug log about this, though. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101745 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=196233 Fixes: bb1d132935c2 ("drm/i915/vbt: split out defaults that are set when there is no VBT") Tested-by: Oliver Weißbarth Reported-by: Oliver Weißbarth Reported-by: Didier G Reported-by: Giles Anderson Cc: Manasi Navare Cc: Ville Syrjälä Cc: Paulo Zanoni Cc: # v4.12+ Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20170811113907.6716-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_bios.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 82b144cdfa1d..183e87e8ea31 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1120,8 +1120,8 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; uint8_t aux_channel, ddc_pin; /* Each DDI port can have more than one value on the "DVO Port" field, - * so look for all the possible values for each port and abort if more - * than one is found. */ + * so look for all the possible values for each port. + */ int dvo_ports[][3] = { {DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, {DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, @@ -1130,7 +1130,10 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, }; - /* Find the child device to use, abort if more than one found. */ + /* + * Find the first child device to reference the port, report if more + * than one found. + */ for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { it = dev_priv->vbt.child_dev + i; @@ -1140,11 +1143,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, if (it->common.dvo_port == dvo_ports[port][j]) { if (child) { - DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n", + DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n", port_name(port)); - return; + } else { + child = it; } - child = it; } } } From acf58d4e965d40fc014252292b0911b4c9fe6697 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Tue, 15 Aug 2017 20:04:03 -0700 Subject: [PATCH 164/179] drm/i915/cnl: Fix LSPCON support. When LSPCON support was extended to CNL one part was missed on lspcon_init. So, instead of adding check per platform on lspcon_init let's use HAS_LSPCON that is already there for that purpose. Fixes: ff15947e0f02 ("drm/i915/cnl: LSPCON support is gen9+") Cc: Shashank Sharma Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Jani Nikula Reviewed-by: Shashank Sharma Link: https://patchwork.freedesktop.org/patch/msgid/20170816030403.11368-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_lspcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c index 5abef482eacf..beb9baaf2f2e 100644 --- a/drivers/gpu/drm/i915/intel_lspcon.c +++ b/drivers/gpu/drm/i915/intel_lspcon.c @@ -210,8 +210,8 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - if (!IS_GEN9(dev_priv)) { - DRM_ERROR("LSPCON is supported on GEN9 only\n"); + if (!HAS_LSPCON(dev_priv)) { + DRM_ERROR("LSPCON is not supported on this platform\n"); return false; } From 6c64dd378aca528903cb9f7a60d04fc5c1a3bdbd Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 11 Aug 2017 16:38:25 -0700 Subject: [PATCH 165/179] drm/i915/gen10: implement gen 10 watermarks calculations They're slightly different than the gen 9 calculations. v2: Remove TODO comment. Code matches recent spec. v3: Rebase on top of latest skl code using new fp16.16 and fixing a logic issue. Auto rebase bot has apparently made some bad decisions that changed the logic of the code. (Noticed by Manesh, updated by Rodrigo). Cc: Mahesh Kumar Cc: Maarten Lankhorst Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Mahesh Kumar Link: https://patchwork.freedesktop.org/patch/msgid/20170811233825.32083-1-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 66495ad36973..ed662937ec3c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4290,8 +4290,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, * should allow pixel_rate up to ~2 GHz which seems sufficient since max * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. */ -static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, - uint32_t latency) +static uint_fixed_16_16_t +skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate, + uint8_t cpp, uint32_t latency) { uint32_t wm_intermediate_val; uint_fixed_16_16_t ret; @@ -4301,6 +4302,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, wm_intermediate_val = latency * pixel_rate * cpp; ret = div_fixed16(wm_intermediate_val, 1000 * 512); + + if (INTEL_GEN(dev_priv) >= 10) + ret = add_fixed16_u32(ret, 1); + return ret; } @@ -4456,9 +4461,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (y_tiled) { interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512); + + if (INTEL_GEN(dev_priv) >= 10) + interm_pbpl++; + plane_blocks_per_line = div_fixed16(interm_pbpl, y_min_scanlines); - } else if (x_tiled) { + } else if (x_tiled && INTEL_GEN(dev_priv) == 9) { interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); plane_blocks_per_line = u32_to_fixed16(interm_pbpl); } else { @@ -4466,7 +4475,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, plane_blocks_per_line = u32_to_fixed16(interm_pbpl); } - method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); + method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency); method2 = skl_wm_method2(plane_pixel_rate, cstate->base.adjusted_mode.crtc_htotal, latency, From a029fa4d758f6a0a0f53c8f226d446206f32373f Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Wed, 9 Aug 2017 13:52:48 -0700 Subject: [PATCH 166/179] drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake. Otherwise it reuses the ilk that has a completely different wm. Cc: Mahesh Kumar Cc: Maarten Lankhorst Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170809205248.11917-6-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 29926244f4f2..0e93ec201fe3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15120,7 +15120,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_wm_get_hw_state(dev); vlv_wm_sanitize(dev_priv); - } else if (IS_GEN9(dev_priv)) { + } else if (INTEL_GEN(dev_priv) >= 9) { skl_wm_get_hw_state(dev); } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_wm_get_hw_state(dev); From ab3595bc4ff328ec90d20714f8e2674f3abfa2cd Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 17 Aug 2017 14:52:09 +0300 Subject: [PATCH 167/179] drm/i915/opregion: let user specify override VBT via firmware load Sometimes it would be most enlightening to debug systems by replacing the VBT to be used. For example, in the referenced bug the BIOS provides different VBT depending on the boot mode (UEFI vs. legacy). It would be interesting to try the failing boot mode with the VBT from the working boot, and see if that makes a difference. Add a module parameter to load the VBT using the firmware loader, not unlike the EDID firmware mechanism. As a starting point for experimenting, one can pick up the BIOS provided VBT from /sys/kernel/debug/dri/0/i915_opregion/i915_vbt. v2: clarify firmware load return value check (Bob) v3: kfree the loaded firmware blob References: https://bugs.freedesktop.org/show_bug.cgi?id=97822#c83 Reviewed-by: Bob Paauwe Acked-by: Daniel Vetter Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20170817115209.25912-1-jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_params.c | 4 +++ drivers/gpu/drm/i915/i915_params.h | 1 + drivers/gpu/drm/i915/intel_opregion.c | 45 +++++++++++++++++++++++++++ 4 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6c25c8520c87..3ee4fd2a9b41 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -646,6 +646,7 @@ struct intel_opregion { u32 swsci_sbcb_sub_functions; struct opregion_asle *asle; void *rvda; + void *vbt_firmware; const void *vbt; u32 vbt_size; u32 *lid_state; diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 14e2c2e57f96..8ab003dca113 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -118,6 +118,10 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type, module_param_named_unsafe(reset, i915.reset, int, 0600); MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); +module_param_named_unsafe(vbt_firmware, i915.vbt_firmware, charp, 0400); +MODULE_PARM_DESC(vbt_firmware, + "Load VBT from specified file under /lib/firmware"); + #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) module_param_named(error_capture, i915.error_capture, bool, 0600); MODULE_PARM_DESC(error_capture, diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index febbfdbd30bd..ac844709c97e 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -28,6 +28,7 @@ #include /* for __read_mostly */ #define I915_PARAMS_FOR_EACH(func) \ + func(char *, vbt_firmware); \ func(int, modeset); \ func(int, panel_ignore_lid); \ func(int, semaphores); \ diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index 2bd03001cc70..98154efcb2f4 100644 --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/drivers/gpu/drm/i915/intel_opregion.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -829,6 +830,10 @@ void intel_opregion_unregister(struct drm_i915_private *dev_priv) memunmap(opregion->rvda); opregion->rvda = NULL; } + if (opregion->vbt_firmware) { + kfree(opregion->vbt_firmware); + opregion->vbt_firmware = NULL; + } opregion->header = NULL; opregion->acpi = NULL; opregion->swsci = NULL; @@ -912,6 +917,43 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = { { } }; +static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) +{ + struct intel_opregion *opregion = &dev_priv->opregion; + const struct firmware *fw = NULL; + const char *name = i915.vbt_firmware; + int ret; + + if (!name || !*name) + return -ENOENT; + + ret = request_firmware(&fw, name, &dev_priv->drm.pdev->dev); + if (ret) { + DRM_ERROR("Requesting VBT firmware \"%s\" failed (%d)\n", + name, ret); + return ret; + } + + if (intel_bios_is_valid_vbt(fw->data, fw->size)) { + opregion->vbt_firmware = kmemdup(fw->data, fw->size, GFP_KERNEL); + if (opregion->vbt_firmware) { + DRM_DEBUG_KMS("Found valid VBT firmware \"%s\"\n", name); + opregion->vbt = opregion->vbt_firmware; + opregion->vbt_size = fw->size; + ret = 0; + } else { + ret = -ENOMEM; + } + } else { + DRM_DEBUG_KMS("Invalid VBT firmware \"%s\"\n", name); + ret = -EINVAL; + } + + release_firmware(fw); + + return ret; +} + int intel_opregion_setup(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; @@ -974,6 +1016,9 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) if (mboxes & MBOX_ASLE_EXT) DRM_DEBUG_DRIVER("ASLE extension supported\n"); + if (intel_load_vbt_firmware(dev_priv) == 0) + goto out; + if (dmi_check_system(intel_no_opregion_vbt)) goto out; From cec3bb013ac6743f3e3eb3a6bedc4f20a71ef942 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Wed, 16 Aug 2017 16:45:14 -0700 Subject: [PATCH 168/179] drm/i915: Split pin mapping into per platform functions Cleanup the code. Map the pins in accordance to individual platforms rather than according to ports. Create separate functions for platforms. v2: - Add missing condition for CoffeeLake. Make platform specific functions static. Add function i915_ddc_pin_mapping(). v3: - Rename functions to x_port_to_ddc_pin() which directly indicates the purpose. Correct default return values on CNP and BXT. Rename i915_port_to_ to g4x_port_to since that was the first platform to run this. Correct code style. (Paulo) Sugested-by Ville Syrjala Cc: Ville Syrjala Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Clinton Taylor Signed-off-by: Anusha Srivatsa Reviewed-by: Paulo Zanoni Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/1502927114-24012-1-git-send-email-anusha.srivatsa@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 121 +++++++++++++++++++++++------- 1 file changed, 95 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index e30c27acb94f..e8abea7594ec 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1843,6 +1843,93 @@ void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, DRM_DEBUG_KMS("sink scrambling handled\n"); } +static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_DPB; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_DPC; + break; + case PORT_D: + ddc_pin = GMBUS_PIN_DPD_CHV; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_DPB; + break; + } + return ddc_pin; +} + +static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_1_BXT; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_2_BXT; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_1_BXT; + break; + } + return ddc_pin; +} + +static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_1_BXT; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_2_BXT; + break; + case PORT_D: + ddc_pin = GMBUS_PIN_4_CNP; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_1_BXT; + break; + } + return ddc_pin; +} + +static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_DPB; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_DPC; + break; + case PORT_D: + ddc_pin = GMBUS_PIN_DPD; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_DPB; + break; + } + return ddc_pin; +} + static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { @@ -1856,32 +1943,14 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, return info->alternate_ddc_pin; } - switch (port) { - case PORT_B: - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_1_BXT; - else - ddc_pin = GMBUS_PIN_DPB; - break; - case PORT_C: - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_2_BXT; - else - ddc_pin = GMBUS_PIN_DPC; - break; - case PORT_D: - if (HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_4_CNP; - else if (IS_CHERRYVIEW(dev_priv)) - ddc_pin = GMBUS_PIN_DPD_CHV; - else - ddc_pin = GMBUS_PIN_DPD; - break; - default: - MISSING_CASE(port); - ddc_pin = GMBUS_PIN_DPB; - break; - } + if (IS_CHERRYVIEW(dev_priv)) + ddc_pin = chv_port_to_ddc_pin(dev_priv, port); + else if (IS_GEN9_LP(dev_priv)) + ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); + else if (HAS_PCH_CNP(dev_priv)) + ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); + else + ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", ddc_pin, port_name(port)); From 7bc66c6ad976ef941b97c679084948a97d33ea37 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 15 Aug 2017 18:01:01 +0200 Subject: [PATCH 169/179] MAINTAINERS: drm/i915 has a new maintainer team For a bunch of reasons[1] I've decided to step down as maintainer and let some other folks enjoy the reputation and hang out in the spotlight. Jani is going to stick around with his expertise in kms and having done the fixes flow for a long time now. Joonas will join and bring in his knowledge on all things GEM. Rodrigo has been less visible because he's been doing tons of work taking care of the internal branch, and it'd be good to have more continuity between these two worlds also on the maintainer side. 1: They all boil down to: This is going to happen sooner or later anyway, we have a great team, with the process improvements over the last few years things work rather well, now is as good as any time to do this. With that change I'll have more time for other aspects of the stack development than maintainership. Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Dave Airlie Acked-by: Joonas Lahtinen Acked-by: Jani Nikula Acked-by: Rodrigo Vivi Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20170815160101.1683-1-daniel.vetter@ffwll.ch --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a1e772e899ed..3dfc592c1cd5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6742,8 +6742,9 @@ S: Supported F: drivers/scsi/isci/ INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) -M: Daniel Vetter M: Jani Nikula +M: Joonas Lahtinen +M: Rodrigo Vivi L: intel-gfx@lists.freedesktop.org W: https://01.org/linuxgraphics/ B: https://01.org/linuxgraphics/documentation/how-report-bugs From 4055dc75d6b51c23602b11c6f716e59b8947ffbf Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 17 Aug 2017 18:32:29 +0100 Subject: [PATCH 170/179] drm/i915: Stop touching forcewake following a gen6+ engine reset Forcewake is not affected by the engine reset on gen6+. Indeed the reason why we added intel_uncore_forcewake_reset() to gen6_reset_engines() was to keep the bookkeeping intact because the reset did not touch the forcewake bit (yet we cancelled the forcewake consumers)! This was done in commit 521198a2e7095: Author: Mika Kuoppala Date: Fri Aug 23 16:52:30 2013 +0300 drm/i915: sanitize forcewake registers on reset In reset we try to restore the forcewake state to pre reset state, using forcewake_count. The reset doesn't seem to clear the forcewake bits so we get warn on forcewake ack register not clearing. That futzing of the forcewake bookkeeping was dropped in commit 0294ae7b44bb ("drm/i915: Consolidate forcewake resetting to a single function"), but it did not make the realisation that the remaining intel_uncore_forcewake_reset() was redundant. The new danger with using intel_uncore_forcewake_reset() with per-engine resets is that the driver and hw are still in an active state as we perform the reset. We may be using the forcewake to read protected registers elsewhere and those results may be clobbered by the concurrent dropping of forcewake. Reported-by: Michel Thierry Fixes: 142bc7d99bcf ("drm/i915: Modify error handler for per engine hang recovery") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Michel Thierry Link: https://patchwork.freedesktop.org/patch/msgid/20170817173229.20324-1-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry Acked-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index deb4430541cf..1d7b879cc68c 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1497,7 +1497,6 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, [VECS] = GEN6_GRDOM_VECS, }; u32 hw_mask; - int ret; if (engine_mask == ALL_ENGINES) { hw_mask = GEN6_GRDOM_FULL; @@ -1509,11 +1508,7 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, hw_mask |= hw_engine_mask[engine->id]; } - ret = gen6_hw_domain_reset(dev_priv, hw_mask); - - intel_uncore_forcewake_reset(dev_priv, true); - - return ret; + return gen6_hw_domain_reset(dev_priv, hw_mask); } /** From f2f5c0610fbc251b127a6fffda6c651288695430 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 16 Aug 2017 09:52:04 +0100 Subject: [PATCH 171/179] drm/i915: Don't use MI_STORE_DWORD_IMM on Sandybridge/vcs MI_STORE_DWORD_IMM just doesn't work on the video decode engine under Sandybridge, so refrain from using it. Then switch the selftests over to using the now common test prior to using MI_STORE_DWORD_IMM. Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: # v4.13-rc1+ Link: https://patchwork.freedesktop.org/patch/msgid/20170816085210.4199-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++++---- drivers/gpu/drm/i915/i915_selftest.h | 2 -- drivers/gpu/drm/i915/intel_ringbuffer.h | 12 ++++++++++++ .../drm/i915/selftests/i915_gem_coherency.c | 2 +- .../gpu/drm/i915/selftests/i915_gem_context.c | 6 ++++-- .../gpu/drm/i915/selftests/intel_hangcheck.c | 18 ++++++++++++------ 7 files changed, 40 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3ee4fd2a9b41..a4ce8fb25fdb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4328,4 +4328,11 @@ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, struct io_mapping *iomap); +static inline bool +intel_engine_can_store_dword(struct intel_engine_cs *engine) +{ + return __intel_engine_can_store_dword(INTEL_GEN(engine->i915), + engine->class); +} + #endif diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 8e8bc7aefd9c..359d5dc6d8df 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1268,7 +1268,9 @@ relocate_entry(struct i915_vma *vma, if (!eb->reloc_cache.vaddr && (DBG_FORCE_RELOC == FORCE_GPU_RELOC || - !reservation_object_test_signaled_rcu(vma->resv, true))) { + !reservation_object_test_signaled_rcu(vma->resv, true)) && + __intel_engine_can_store_dword(eb->reloc_cache.gen, + eb->engine->class)) { const unsigned int gen = eb->reloc_cache.gen; unsigned int len; u32 *batch; @@ -1278,10 +1280,8 @@ relocate_entry(struct i915_vma *vma, len = offset & 7 ? 8 : 5; else if (gen >= 4) len = 4; - else if (gen >= 3) + else len = 3; - else /* On gen2 MI_STORE_DWORD_IMM uses a physical address */ - goto repeat; batch = reloc_gpu(eb, vma, len); if (IS_ERR(batch)) diff --git a/drivers/gpu/drm/i915/i915_selftest.h b/drivers/gpu/drm/i915/i915_selftest.h index 9d7d86f1733d..78e1a1b168ff 100644 --- a/drivers/gpu/drm/i915/i915_selftest.h +++ b/drivers/gpu/drm/i915/i915_selftest.h @@ -101,6 +101,4 @@ bool __igt_timeout(unsigned long timeout, const char *fmt, ...); #define igt_timeout(t, fmt, ...) \ __igt_timeout((t), KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) -#define igt_can_mi_store_dword_imm(D) (INTEL_GEN(D) > 2) - #endif /* !__I915_SELFTEST_H__ */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index d33c93444c0d..02d8974bf9ab 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -735,4 +735,16 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv); void intel_engines_mark_idle(struct drm_i915_private *i915); void intel_engines_reset_default_submission(struct drm_i915_private *i915); +static inline bool +__intel_engine_can_store_dword(unsigned int gen, unsigned int class) +{ + if (gen <= 2) + return false; /* uses physical not virtual addresses */ + + if (gen == 6 && class == VIDEO_DECODE_CLASS) + return false; /* b0rked */ + + return true; +} + #endif /* _INTEL_RINGBUFFER_H_ */ diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c index 95d4aebc0181..35d778d70626 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c @@ -241,7 +241,7 @@ static bool always_valid(struct drm_i915_private *i915) static bool needs_mi_store_dword(struct drm_i915_private *i915) { - return igt_can_mi_store_dword_imm(i915); + return intel_engine_can_store_dword(i915->engine[RCS]); } static const struct igt_coherency_mode { diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 12b85b3278cd..fb0a58fc8348 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -38,8 +38,6 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value) u32 *cmd; int err; - GEM_BUG_ON(!igt_can_mi_store_dword_imm(vma->vm->i915)); - size = (4 * count + 1) * sizeof(u32); size = round_up(size, PAGE_SIZE); obj = i915_gem_object_create_internal(vma->vm->i915, size); @@ -123,6 +121,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj, int err; GEM_BUG_ON(obj->base.size > vm->total); + GEM_BUG_ON(!intel_engine_can_store_dword(engine)); vma = i915_vma_instance(obj, vm, NULL); if (IS_ERR(vma)) @@ -359,6 +358,9 @@ static int igt_ctx_exec(void *arg) } for_each_engine(engine, i915, id) { + if (!intel_engine_can_store_dword(engine)) + continue; + if (!obj) { obj = create_test_object(ctx, file, &objects); if (IS_ERR(obj)) { diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 208b34e864fb..02e52a146ed8 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -253,9 +253,6 @@ static int igt_hang_sanitycheck(void *arg) /* Basic check that we can execute our hanging batch */ - if (!igt_can_mi_store_dword_imm(i915)) - return 0; - mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); if (err) @@ -264,6 +261,9 @@ static int igt_hang_sanitycheck(void *arg) for_each_engine(engine, i915, id) { long timeout; + if (!intel_engine_can_store_dword(engine)) + continue; + rq = hang_create_request(&h, engine, i915->kernel_context); if (IS_ERR(rq)) { err = PTR_ERR(rq); @@ -599,6 +599,9 @@ static int igt_wait_reset(void *arg) long timeout; int err; + if (!intel_engine_can_store_dword(i915->engine[RCS])) + return 0; + /* Check that we detect a stuck waiter and issue a reset */ global_reset_lock(i915); @@ -664,9 +667,6 @@ static int igt_reset_queue(void *arg) /* Check that we replay pending requests following a hang */ - if (!igt_can_mi_store_dword_imm(i915)) - return 0; - global_reset_lock(i915); mutex_lock(&i915->drm.struct_mutex); @@ -679,6 +679,9 @@ static int igt_reset_queue(void *arg) IGT_TIMEOUT(end_time); unsigned int count; + if (!intel_engine_can_store_dword(engine)) + continue; + prev = hang_create_request(&h, engine, i915->kernel_context); if (IS_ERR(prev)) { err = PTR_ERR(prev); @@ -784,6 +787,9 @@ static int igt_handle_error(void *arg) if (!intel_has_reset_engine(i915)) return 0; + if (!intel_engine_can_store_dword(i915->engine[RCS])) + return 0; + mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); From 8bcbfb12818f811d63801b71d25809690d1798fc Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 16 Aug 2017 09:52:05 +0100 Subject: [PATCH 172/179] drm/i915: Check context status before looking up our obj/vma Since we keep the context around across the slow lookup where we may drop the struct_mutex, we should double check that the context is still valid upon reacquisition. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Joonas Lahtinen Cc: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20170816085210.4199-2-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 359d5dc6d8df..044fb1205554 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -679,13 +679,6 @@ static int eb_select_context(struct i915_execbuffer *eb) if (unlikely(!ctx)) return -ENOENT; - if (unlikely(i915_gem_context_is_banned(ctx))) { - DRM_DEBUG("Context %u tried to submit while banned\n", - ctx->user_handle); - i915_gem_context_put(ctx); - return -EIO; - } - eb->ctx = ctx; eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base; @@ -707,6 +700,12 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) int slow_pass = -1; int err; + if (unlikely(i915_gem_context_is_closed(eb->ctx))) + return -ENOENT; + + if (unlikely(i915_gem_context_is_banned(eb->ctx))) + return -EIO; + INIT_LIST_HEAD(&eb->relocs); INIT_LIST_HEAD(&eb->unbound); From c7c6e46f913bb3a6ff19e64940ebb54652033677 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 16 Aug 2017 09:52:06 +0100 Subject: [PATCH 173/179] drm/i915: Convert execbuf to use struct-of-array packing for critical fields When userspace is doing most of the work, avoiding relocs (using NO_RELOC) and opting out of implicit synchronisation (using ASYNC), we still spend a lot of time processing the arrays in execbuf, even though we now should have nothing to do most of the time. One issue that becomes readily apparent in profiling anv is that iterating over the large execobj[] is unfriendly to the loop prefetchers of the CPU and it much prefers iterating over a pair of arrays rather than one big array. v2: Clear vma[] on construction to handle errors during vma lookup Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20170816085210.4199-3-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_evict.c | 4 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 301 +++++++++++---------- drivers/gpu/drm/i915/i915_vma.h | 2 +- 3 files changed, 156 insertions(+), 151 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c index a193f1b36c67..4df039ef2ce3 100644 --- a/drivers/gpu/drm/i915/i915_gem_evict.c +++ b/drivers/gpu/drm/i915/i915_gem_evict.c @@ -318,8 +318,8 @@ int i915_gem_evict_for_node(struct i915_address_space *vm, /* Overlap of objects in the same batch? */ if (i915_vma_is_pinned(vma)) { ret = -ENOSPC; - if (vma->exec_entry && - vma->exec_entry->flags & EXEC_OBJECT_PINNED) + if (vma->exec_flags && + *vma->exec_flags & EXEC_OBJECT_PINNED) ret = -EINVAL; break; } diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 044fb1205554..da6cb2fe5f85 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -192,6 +192,8 @@ struct i915_execbuffer { struct drm_file *file; /** per-file lookup tables and limits */ struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */ struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */ + struct i915_vma **vma; + unsigned int *flags; struct intel_engine_cs *engine; /** engine to queue the request to */ struct i915_gem_context *ctx; /** context for building the request */ @@ -245,13 +247,7 @@ struct i915_execbuffer { struct hlist_head *buckets; /** ht for relocation handles */ }; -/* - * As an alternative to creating a hashtable of handle-to-vma for a batch, - * we used the last available reserved field in the execobject[] and stash - * a link from the execobj to its vma. - */ -#define __exec_to_vma(ee) (ee)->rsvd2 -#define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee)) +#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags]) /* * Used to convert any address to canonical form. @@ -320,85 +316,82 @@ static int eb_create(struct i915_execbuffer *eb) static bool eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, - const struct i915_vma *vma) + const struct i915_vma *vma, + unsigned int flags) { - if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) - return true; - if (vma->node.size < entry->pad_to_size) return true; if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) return true; - if (entry->flags & EXEC_OBJECT_PINNED && + if (flags & EXEC_OBJECT_PINNED && vma->node.start != entry->offset) return true; - if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && + if (flags & __EXEC_OBJECT_NEEDS_BIAS && vma->node.start < BATCH_OFFSET_BIAS) return true; - if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && + if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && (vma->node.start + vma->node.size - 1) >> 32) return true; return false; } -static inline void +static inline bool eb_pin_vma(struct i915_execbuffer *eb, - struct drm_i915_gem_exec_object2 *entry, + const struct drm_i915_gem_exec_object2 *entry, struct i915_vma *vma) { - u64 flags; + unsigned int exec_flags = *vma->exec_flags; + u64 pin_flags; if (vma->node.size) - flags = vma->node.start; + pin_flags = vma->node.start; else - flags = entry->offset & PIN_OFFSET_MASK; + pin_flags = entry->offset & PIN_OFFSET_MASK; - flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_GTT)) - flags |= PIN_GLOBAL; + pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT)) + pin_flags |= PIN_GLOBAL; - if (unlikely(i915_vma_pin(vma, 0, 0, flags))) - return; + if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) + return false; - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { if (unlikely(i915_vma_get_fence(vma))) { i915_vma_unpin(vma); - return; + return false; } if (i915_vma_pin_fence(vma)) - entry->flags |= __EXEC_OBJECT_HAS_FENCE; + exec_flags |= __EXEC_OBJECT_HAS_FENCE; } - entry->flags |= __EXEC_OBJECT_HAS_PIN; + *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN; + return !eb_vma_misplaced(entry, vma, exec_flags); } -static inline void -__eb_unreserve_vma(struct i915_vma *vma, - const struct drm_i915_gem_exec_object2 *entry) +static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) { - GEM_BUG_ON(!(entry->flags & __EXEC_OBJECT_HAS_PIN)); + GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); - if (unlikely(entry->flags & __EXEC_OBJECT_HAS_FENCE)) + if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) i915_vma_unpin_fence(vma); __i915_vma_unpin(vma); } static inline void -eb_unreserve_vma(struct i915_vma *vma, - struct drm_i915_gem_exec_object2 *entry) +eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags) { - if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) + if (!(*flags & __EXEC_OBJECT_HAS_PIN)) return; - __eb_unreserve_vma(vma, entry); - entry->flags &= ~__EXEC_OBJECT_RESERVED; + __eb_unreserve_vma(vma, *flags); + *flags &= ~__EXEC_OBJECT_RESERVED; } static int @@ -428,7 +421,7 @@ eb_validate_vma(struct i915_execbuffer *eb, entry->pad_to_size = 0; } - if (unlikely(vma->exec_entry)) { + if (unlikely(vma->exec_flags)) { DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n", entry->handle, (int)(entry - eb->exec)); return -EINVAL; @@ -441,14 +434,25 @@ eb_validate_vma(struct i915_execbuffer *eb, */ entry->offset = gen8_noncanonical_addr(entry->offset); + if (!eb->reloc_cache.has_fence) { + entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; + } else { + if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || + eb->reloc_cache.needs_unfenced) && + i915_gem_object_is_tiled(vma->obj)) + entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; + } + + if (!(entry->flags & EXEC_OBJECT_PINNED)) + entry->flags |= eb->context_flags; + return 0; } static int -eb_add_vma(struct i915_execbuffer *eb, - struct drm_i915_gem_exec_object2 *entry, - struct i915_vma *vma) +eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma) { + struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; int err; GEM_BUG_ON(i915_vma_is_closed(vma)); @@ -469,40 +473,28 @@ eb_add_vma(struct i915_execbuffer *eb, if (entry->relocation_count) list_add_tail(&vma->reloc_link, &eb->relocs); - if (!eb->reloc_cache.has_fence) { - entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; - } else { - if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || - eb->reloc_cache.needs_unfenced) && - i915_gem_object_is_tiled(vma->obj)) - entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; - } - - if (!(entry->flags & EXEC_OBJECT_PINNED)) - entry->flags |= eb->context_flags; - /* * Stash a pointer from the vma to execobj, so we can query its flags, * size, alignment etc as provided by the user. Also we stash a pointer * to the vma inside the execobj so that we can use a direct lookup * to find the right target VMA when doing relocations. */ - vma->exec_entry = entry; - __exec_to_vma(entry) = (uintptr_t)vma; + eb->vma[i] = vma; + eb->flags[i] = entry->flags; + vma->exec_flags = &eb->flags[i]; err = 0; - eb_pin_vma(eb, entry, vma); - if (eb_vma_misplaced(entry, vma)) { - eb_unreserve_vma(vma, entry); - - list_add_tail(&vma->exec_link, &eb->unbound); - if (drm_mm_node_allocated(&vma->node)) - err = i915_vma_unbind(vma); - } else { + if (eb_pin_vma(eb, entry, vma)) { if (entry->offset != vma->node.start) { entry->offset = vma->node.start | UPDATE; eb->args->flags |= __EXEC_HAS_RELOC; } + } else { + eb_unreserve_vma(vma, vma->exec_flags); + + list_add_tail(&vma->exec_link, &eb->unbound); + if (drm_mm_node_allocated(&vma->node)) + err = i915_vma_unbind(vma); } return err; } @@ -527,32 +519,35 @@ static inline int use_cpu_reloc(const struct reloc_cache *cache, static int eb_reserve_vma(const struct i915_execbuffer *eb, struct i915_vma *vma) { - struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; - u64 flags; + struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); + unsigned int exec_flags = *vma->exec_flags; + u64 pin_flags; int err; - flags = PIN_USER | PIN_NONBLOCK; - if (entry->flags & EXEC_OBJECT_NEEDS_GTT) - flags |= PIN_GLOBAL; + pin_flags = PIN_USER | PIN_NONBLOCK; + if (exec_flags & EXEC_OBJECT_NEEDS_GTT) + pin_flags |= PIN_GLOBAL; /* * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, * limit address to the first 4GBs for unflagged objects. */ - if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) - flags |= PIN_ZONE_4G; + if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) + pin_flags |= PIN_ZONE_4G; - if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) - flags |= PIN_MAPPABLE; + if (exec_flags & __EXEC_OBJECT_NEEDS_MAP) + pin_flags |= PIN_MAPPABLE; - if (entry->flags & EXEC_OBJECT_PINNED) { - flags |= entry->offset | PIN_OFFSET_FIXED; - flags &= ~PIN_NONBLOCK; /* force overlapping PINNED checks */ - } else if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) { - flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; + if (exec_flags & EXEC_OBJECT_PINNED) { + pin_flags |= entry->offset | PIN_OFFSET_FIXED; + pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */ + } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) { + pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; } - err = i915_vma_pin(vma, entry->pad_to_size, entry->alignment, flags); + err = i915_vma_pin(vma, + entry->pad_to_size, entry->alignment, + pin_flags); if (err) return err; @@ -561,7 +556,7 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, eb->args->flags |= __EXEC_HAS_RELOC; } - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { err = i915_vma_get_fence(vma); if (unlikely(err)) { i915_vma_unpin(vma); @@ -569,11 +564,11 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, } if (i915_vma_pin_fence(vma)) - entry->flags |= __EXEC_OBJECT_HAS_FENCE; + exec_flags |= __EXEC_OBJECT_HAS_FENCE; } - entry->flags |= __EXEC_OBJECT_HAS_PIN; - GEM_BUG_ON(eb_vma_misplaced(entry, vma)); + *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN; + GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags)); return 0; } @@ -615,18 +610,18 @@ static int eb_reserve(struct i915_execbuffer *eb) INIT_LIST_HEAD(&eb->unbound); INIT_LIST_HEAD(&last); for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; - if (entry->flags & EXEC_OBJECT_PINNED && - entry->flags & __EXEC_OBJECT_HAS_PIN) + if (flags & EXEC_OBJECT_PINNED && + flags & __EXEC_OBJECT_HAS_PIN) continue; - vma = exec_to_vma(entry); - eb_unreserve_vma(vma, entry); + eb_unreserve_vma(vma, &eb->flags[i]); - if (entry->flags & EXEC_OBJECT_PINNED) + if (flags & EXEC_OBJECT_PINNED) list_add(&vma->exec_link, &eb->unbound); - else if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) + else if (flags & __EXEC_OBJECT_NEEDS_MAP) list_add_tail(&vma->exec_link, &eb->unbound); else list_add_tail(&vma->exec_link, &last); @@ -714,18 +709,15 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); for (i = 0; i < count; i++) { - __exec_to_vma(&eb->exec[i]) = 0; - hlist_for_each_entry(vma, ht_head(lut, eb->exec[i].handle), ctx_node) { if (vma->ctx_handle != eb->exec[i].handle) continue; - err = eb_add_vma(eb, &eb->exec[i], vma); + err = eb_add_vma(eb, i, vma); if (unlikely(err)) return err; - goto next_vma; } @@ -746,7 +738,7 @@ next_vma: ; for (i = slow_pass; i < count; i++) { struct drm_i915_gem_object *obj; - if (__exec_to_vma(&eb->exec[i])) + if (eb->vma[i]) continue; obj = to_intel_bo(idr_find(idr, eb->exec[i].handle)); @@ -758,14 +750,17 @@ next_vma: ; goto err; } - __exec_to_vma(&eb->exec[i]) = INTERMEDIATE | (uintptr_t)obj; + eb->vma[i] = (struct i915_vma *) + ptr_pack_bits(obj, INTERMEDIATE, 1); } spin_unlock(&eb->file->table_lock); for (i = slow_pass; i < count; i++) { struct drm_i915_gem_object *obj; + unsigned int is_obj; - if (!(__exec_to_vma(&eb->exec[i]) & INTERMEDIATE)) + obj = (typeof(obj))ptr_unpack_bits(eb->vma[i], &is_obj, 1); + if (!is_obj) continue; /* @@ -776,8 +771,6 @@ next_vma: ; * from the (obj, vm) we don't run the risk of creating * duplicated vmas for the same vm. */ - obj = u64_to_ptr(typeof(*obj), - __exec_to_vma(&eb->exec[i]) & ~INTERMEDIATE); vma = i915_vma_instance(obj, eb->vm, NULL); if (unlikely(IS_ERR(vma))) { DRM_DEBUG("Failed to lookup VMA\n"); @@ -801,14 +794,17 @@ next_vma: ; i915_vma_get(vma); } - err = eb_add_vma(eb, &eb->exec[i], vma); + err = eb_add_vma(eb, i, vma); if (unlikely(err)) goto err; + GEM_BUG_ON(vma != eb->vma[i]); + GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); + /* Only after we validated the user didn't use our bits */ if (vma->ctx != eb->ctx) { i915_vma_get(vma); - eb->exec[i].flags |= __EXEC_OBJECT_HAS_REF; + *vma->exec_flags |= __EXEC_OBJECT_HAS_REF; } } @@ -822,7 +818,8 @@ next_vma: ; out: /* take note of the batch buffer before we might reorder the lists */ i = eb_batch_index(eb); - eb->batch = exec_to_vma(&eb->exec[i]); + eb->batch = eb->vma[i]; + GEM_BUG_ON(eb->batch->exec_flags != &eb->flags[i]); /* * SNA is doing fancy tricks with compressing batch buffers, which leads @@ -833,18 +830,18 @@ out: * Note that actual hangs have only been observed on gen7, but for * paranoia do it everywhere. */ - if (!(eb->exec[i].flags & EXEC_OBJECT_PINNED)) - eb->exec[i].flags |= __EXEC_OBJECT_NEEDS_BIAS; + if (!(eb->flags[i] & EXEC_OBJECT_PINNED)) + eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS; if (eb->reloc_cache.has_fence) - eb->exec[i].flags |= EXEC_OBJECT_NEEDS_FENCE; + eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE; eb->args->flags |= __EXEC_VALIDATED; return eb_reserve(eb); err: for (i = slow_pass; i < count; i++) { - if (__exec_to_vma(&eb->exec[i]) & INTERMEDIATE) - __exec_to_vma(&eb->exec[i]) = 0; + if (ptr_unmask_bits(eb->vma[i], 1)) + eb->vma[i] = NULL; } lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; return err; @@ -857,7 +854,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) if (eb->lut_size < 0) { if (handle >= -eb->lut_size) return NULL; - return exec_to_vma(&eb->exec[handle]); + return eb->vma[handle]; } else { struct hlist_head *head; struct i915_vma *vma; @@ -877,24 +874,21 @@ static void eb_release_vmas(const struct i915_execbuffer *eb) unsigned int i; for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + struct i915_vma *vma = eb->vma[i]; + unsigned int flags = eb->flags[i]; if (!vma) continue; - GEM_BUG_ON(vma->exec_entry != entry); - vma->exec_entry = NULL; - __exec_to_vma(entry) = 0; + GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); + vma->exec_flags = NULL; + eb->vma[i] = NULL; - if (entry->flags & __EXEC_OBJECT_HAS_PIN) - __eb_unreserve_vma(vma, entry); + if (flags & __EXEC_OBJECT_HAS_PIN) + __eb_unreserve_vma(vma, flags); - if (entry->flags & __EXEC_OBJECT_HAS_REF) + if (flags & __EXEC_OBJECT_HAS_REF) i915_vma_put(vma); - - entry->flags &= - ~(__EXEC_OBJECT_RESERVED | __EXEC_OBJECT_HAS_REF); } } @@ -1383,7 +1377,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, } if (reloc->write_domain) { - target->exec_entry->flags |= EXEC_OBJECT_WRITE; + *target->exec_flags |= EXEC_OBJECT_WRITE; /* * Sandybridge PPGTT errata: We need a global gtt mapping @@ -1435,7 +1429,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, * do relocations we are already stalling, disable the user's opt * of our synchronisation. */ - vma->exec_entry->flags &= ~EXEC_OBJECT_ASYNC; + *vma->exec_flags &= ~EXEC_OBJECT_ASYNC; /* and update the user's relocation entry */ return relocate_entry(vma, reloc, eb, target); @@ -1446,7 +1440,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma) #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; struct drm_i915_gem_relocation_entry __user *urelocs; - const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; + const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); unsigned int remain; urelocs = u64_to_user_ptr(entry->relocs_ptr); @@ -1529,7 +1523,7 @@ out: static int eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma) { - const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; + const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); struct drm_i915_gem_relocation_entry *relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); unsigned int i; @@ -1733,6 +1727,8 @@ repeat: if (err) goto err; + GEM_BUG_ON(!eb->batch); + list_for_each_entry(vma, &eb->relocs, reloc_link) { if (!have_copy) { pagefault_disable(); @@ -1826,11 +1822,11 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) int err; for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; struct drm_i915_gem_object *obj = vma->obj; - if (entry->flags & EXEC_OBJECT_CAPTURE) { + if (flags & EXEC_OBJECT_CAPTURE) { struct i915_gem_capture_list *capture; capture = kmalloc(sizeof(*capture), GFP_KERNEL); @@ -1838,7 +1834,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) return -ENOMEM; capture->next = eb->request->capture_list; - capture->vma = vma; + capture->vma = eb->vma[i]; eb->request->capture_list = capture; } @@ -1856,29 +1852,29 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) */ if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) { if (i915_gem_clflush_object(obj, 0)) - entry->flags &= ~EXEC_OBJECT_ASYNC; + flags &= ~EXEC_OBJECT_ASYNC; } - if (entry->flags & EXEC_OBJECT_ASYNC) - goto skip_flushes; + if (flags & EXEC_OBJECT_ASYNC) + continue; err = i915_gem_request_await_object - (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE); + (eb->request, obj, flags & EXEC_OBJECT_WRITE); if (err) return err; - -skip_flushes: - i915_vma_move_to_active(vma, eb->request, entry->flags); - __eb_unreserve_vma(vma, entry); - vma->exec_entry = NULL; } for (i = 0; i < count; i++) { - const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; - eb_export_fence(vma, eb->request, entry->flags); - if (unlikely(entry->flags & __EXEC_OBJECT_HAS_REF)) + i915_vma_move_to_active(vma, eb->request, flags); + eb_export_fence(vma, eb->request, flags); + + __eb_unreserve_vma(vma, flags); + vma->exec_flags = NULL; + + if (unlikely(flags & __EXEC_OBJECT_HAS_REF)) i915_vma_put(vma); } eb->exec = NULL; @@ -2007,11 +2003,11 @@ static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master) if (IS_ERR(vma)) goto out; - vma->exec_entry = - memset(&eb->exec[eb->buffer_count++], - 0, sizeof(*vma->exec_entry)); - vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF; - __exec_to_vma(vma->exec_entry) = (uintptr_t)i915_vma_get(vma); + eb->vma[eb->buffer_count] = i915_vma_get(vma); + eb->flags[eb->buffer_count] = + __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF; + vma->exec_flags = &eb->flags[eb->buffer_count]; + eb->buffer_count++; out: i915_gem_object_unpin_pages(shadow_batch_obj); @@ -2270,7 +2266,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.args = args; if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) args->flags |= __EXEC_HAS_RELOC; + eb.exec = exec; + eb.vma = memset(exec + args->buffer_count + 1, 0, + (args->buffer_count + 1) * sizeof(*eb.vma)); + eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1); + eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; if (USES_FULL_PPGTT(eb.i915)) eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT; @@ -2358,7 +2359,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } - if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) { + if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) { DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); err = -EINVAL; goto err_vma; @@ -2511,7 +2512,9 @@ int i915_gem_execbuffer(struct drm_device *dev, void *data, struct drm_file *file) { - const size_t sz = sizeof(struct drm_i915_gem_exec_object2); + const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) + + sizeof(struct i915_vma *) + + sizeof(unsigned int)); struct drm_i915_gem_execbuffer *args = data; struct drm_i915_gem_execbuffer2 exec2; struct drm_i915_gem_exec_object *exec_list = NULL; @@ -2602,7 +2605,9 @@ int i915_gem_execbuffer2(struct drm_device *dev, void *data, struct drm_file *file) { - const size_t sz = sizeof(struct drm_i915_gem_exec_object2); + const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) + + sizeof(struct i915_vma *) + + sizeof(unsigned int)); struct drm_i915_gem_execbuffer2 *args = data; struct drm_i915_gem_exec_object2 *exec2_list; struct drm_syncobj **fences = NULL; diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 20cf272c97b1..5c49506d14bc 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -112,7 +112,7 @@ struct i915_vma { /** * Used for performing relocations during execbuffer insertion. */ - struct drm_i915_gem_exec_object2 *exec_entry; + unsigned int *exec_flags; struct hlist_node exec_node; u32 exec_handle; From 170fa29b14fadf2deb361589cefe6a78b21b1b22 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 16 Aug 2017 09:52:07 +0100 Subject: [PATCH 174/179] drm/i915: Simplify eb_lookup_vmas() Since the introduction of being able to perform a lockless lookup of an object (i915_gem_object_get_rcu() in fbbd37b36fa5 ("drm/i915: Move object release to a freelist + worker") we no longer need to split the object/vma lookup into 3 phases and so combine them into a much simpler single loop. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20170816085210.4199-4-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 122 ++++++--------------- 1 file changed, 36 insertions(+), 86 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index da6cb2fe5f85..95e461259d24 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -450,7 +450,9 @@ eb_validate_vma(struct i915_execbuffer *eb, } static int -eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma) +eb_add_vma(struct i915_execbuffer *eb, + unsigned int i, struct i915_vma *vma, + unsigned int flags) { struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; int err; @@ -480,7 +482,7 @@ eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma) * to find the right target VMA when doing relocations. */ eb->vma[i] = vma; - eb->flags[i] = entry->flags; + eb->flags[i] = entry->flags | flags; vma->exec_flags = &eb->flags[i]; err = 0; @@ -686,13 +688,9 @@ static int eb_select_context(struct i915_execbuffer *eb) static int eb_lookup_vmas(struct i915_execbuffer *eb) { -#define INTERMEDIATE BIT(0) - const unsigned int count = eb->buffer_count; struct i915_gem_context_vma_lut *lut = &eb->ctx->vma_lut; - struct i915_vma *vma; - struct idr *idr; + struct drm_i915_gem_object *uninitialized_var(obj); unsigned int i; - int slow_pass = -1; int err; if (unlikely(i915_gem_context_is_closed(eb->ctx))) @@ -708,82 +706,38 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) flush_work(&lut->resize); GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); - for (i = 0; i < count; i++) { - hlist_for_each_entry(vma, - ht_head(lut, eb->exec[i].handle), - ctx_node) { - if (vma->ctx_handle != eb->exec[i].handle) + for (i = 0; i < eb->buffer_count; i++) { + u32 handle = eb->exec[i].handle; + struct hlist_head *hl = ht_head(lut, handle); + unsigned int flags = 0; + struct i915_vma *vma; + + hlist_for_each_entry(vma, hl, ctx_node) { + GEM_BUG_ON(vma->ctx != eb->ctx); + + if (vma->ctx_handle != handle) continue; - err = eb_add_vma(eb, i, vma); - if (unlikely(err)) - return err; - goto next_vma; + goto add_vma; } - if (slow_pass < 0) - slow_pass = i; -next_vma: ; - } - - if (slow_pass < 0) - goto out; - - spin_lock(&eb->file->table_lock); - /* - * Grab a reference to the object and release the lock so we can lookup - * or create the VMA without using GFP_ATOMIC - */ - idr = &eb->file->object_idr; - for (i = slow_pass; i < count; i++) { - struct drm_i915_gem_object *obj; - - if (eb->vma[i]) - continue; - - obj = to_intel_bo(idr_find(idr, eb->exec[i].handle)); + obj = i915_gem_object_lookup(eb->file, handle); if (unlikely(!obj)) { - spin_unlock(&eb->file->table_lock); - DRM_DEBUG("Invalid object handle %d at index %d\n", - eb->exec[i].handle, i); err = -ENOENT; - goto err; + goto err_vma; } - eb->vma[i] = (struct i915_vma *) - ptr_pack_bits(obj, INTERMEDIATE, 1); - } - spin_unlock(&eb->file->table_lock); - - for (i = slow_pass; i < count; i++) { - struct drm_i915_gem_object *obj; - unsigned int is_obj; - - obj = (typeof(obj))ptr_unpack_bits(eb->vma[i], &is_obj, 1); - if (!is_obj) - continue; - - /* - * NOTE: We can leak any vmas created here when something fails - * later on. But that's no issue since vma_unbind can deal with - * vmas which are not actually bound. And since only - * lookup_or_create exists as an interface to get at the vma - * from the (obj, vm) we don't run the risk of creating - * duplicated vmas for the same vm. - */ vma = i915_vma_instance(obj, eb->vm, NULL); if (unlikely(IS_ERR(vma))) { - DRM_DEBUG("Failed to lookup VMA\n"); err = PTR_ERR(vma); - goto err; + goto err_obj; } /* First come, first served */ if (!vma->ctx) { vma->ctx = eb->ctx; - vma->ctx_handle = eb->exec[i].handle; - hlist_add_head(&vma->ctx_node, - ht_head(lut, eb->exec[i].handle)); + vma->ctx_handle = handle; + hlist_add_head(&vma->ctx_node, hl); lut->ht_count++; lut->ht_size |= I915_CTX_RESIZE_IN_PROGRESS; if (i915_vma_is_ggtt(vma)) { @@ -791,21 +745,19 @@ next_vma: ; obj->vma_hashed = vma; } - i915_vma_get(vma); + /* transfer ref to ctx */ + obj = NULL; + } else { + flags = __EXEC_OBJECT_HAS_REF; } - err = eb_add_vma(eb, i, vma); +add_vma: + err = eb_add_vma(eb, i, vma, flags); if (unlikely(err)) - goto err; + goto err_obj; GEM_BUG_ON(vma != eb->vma[i]); GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); - - /* Only after we validated the user didn't use our bits */ - if (vma->ctx != eb->ctx) { - i915_vma_get(vma); - *vma->exec_flags |= __EXEC_OBJECT_HAS_REF; - } } if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) { @@ -815,7 +767,6 @@ next_vma: ; lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; } -out: /* take note of the batch buffer before we might reorder the lists */ i = eb_batch_index(eb); eb->batch = eb->vma[i]; @@ -838,14 +789,13 @@ out: eb->args->flags |= __EXEC_VALIDATED; return eb_reserve(eb); -err: - for (i = slow_pass; i < count; i++) { - if (ptr_unmask_bits(eb->vma[i], 1)) - eb->vma[i] = NULL; - } +err_obj: + if (obj) + i915_gem_object_put(obj); +err_vma: + eb->vma[i] = NULL; lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; return err; -#undef INTERMEDIATE } static struct i915_vma * @@ -878,7 +828,7 @@ static void eb_release_vmas(const struct i915_execbuffer *eb) unsigned int flags = eb->flags[i]; if (!vma) - continue; + break; GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); vma->exec_flags = NULL; @@ -2268,8 +2218,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, args->flags |= __EXEC_HAS_RELOC; eb.exec = exec; - eb.vma = memset(exec + args->buffer_count + 1, 0, - (args->buffer_count + 1) * sizeof(*eb.vma)); + eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1); + eb.vma[0] = NULL; eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1); eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; From d1b48c1e7184d9bc4ae6d7f9fe2eed9efed11ffc Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 16 Aug 2017 09:52:08 +0100 Subject: [PATCH 175/179] drm/i915: Replace execbuf vma ht with an idr This was the competing idea long ago, but it was only with the rewrite of the idr as an radixtree and using the radixtree directly ourselves, along with the realisation that we can store the vma directly in the radixtree and only need a list for the reverse mapping, that made the patch performant enough to displace using a hashtable. Though the vma ht is fast and doesn't require any extra allocation (as we can embed the node inside the vma), it does require a thread for resizing and serialization and will have the occasional slow lookup. That is hairy enough to investigate alternatives and favour them if equivalent in peak performance. One advantage of allocating an indirection entry is that we can support a single shared bo between many clients, something that was done on a first-come first-serve basis for shared GGTT vma previously. To offset the extra allocations, we create yet another kmem_cache for them. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20170816085210.4199-5-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_debugfs.c | 6 -- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 46 ++++++---- drivers/gpu/drm/i915/i915_gem_context.c | 87 ++++--------------- drivers/gpu/drm/i915/i915_gem_context.h | 39 +++------ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 81 ++++++----------- drivers/gpu/drm/i915/i915_gem_object.h | 23 ++++- drivers/gpu/drm/i915/i915_vma.c | 22 ----- drivers/gpu/drm/i915/i915_vma.h | 4 - drivers/gpu/drm/i915/selftests/mock_context.c | 15 +--- lib/radix-tree.c | 1 + 11 files changed, 116 insertions(+), 209 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 329fb3649dc3..48572b157222 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1954,12 +1954,6 @@ static int i915_context_status(struct seq_file *m, void *unused) seq_putc(m, '\n'); } - seq_printf(m, - "\tvma hashtable size=%u (actual %lu), count=%u\n", - ctx->vma_lut.ht_size, - BIT(ctx->vma_lut.ht_bits), - ctx->vma_lut.ht_count); - seq_putc(m, '\n'); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a4ce8fb25fdb..5b70bb9089fe 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2156,6 +2156,7 @@ struct drm_i915_private { struct kmem_cache *objects; struct kmem_cache *vmas; + struct kmem_cache *luts; struct kmem_cache *requests; struct kmem_cache *dependencies; struct kmem_cache *priorities; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5a3f3bb3f21d..b9e8e0d6e97b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3242,25 +3242,33 @@ out_rearm: void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) { + struct drm_i915_private *i915 = to_i915(gem->dev); struct drm_i915_gem_object *obj = to_intel_bo(gem); struct drm_i915_file_private *fpriv = file->driver_priv; - struct i915_vma *vma, *vn; + struct i915_lut_handle *lut, *ln; - mutex_lock(&obj->base.dev->struct_mutex); - list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) - if (vma->vm->file == fpriv) + mutex_lock(&i915->drm.struct_mutex); + + list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { + struct i915_gem_context *ctx = lut->ctx; + struct i915_vma *vma; + + if (ctx->file_priv != fpriv) + continue; + + vma = radix_tree_delete(&ctx->handles_vma, lut->handle); + + if (!i915_vma_is_ggtt(vma)) i915_vma_close(vma); - vma = obj->vma_hashed; - if (vma && vma->ctx->file_priv == fpriv) - i915_vma_unlink_ctx(vma); + list_del(&lut->obj_link); + list_del(&lut->ctx_link); - if (i915_gem_object_is_active(obj) && - !i915_gem_object_has_active_reference(obj)) { - i915_gem_object_set_active_reference(obj); - i915_gem_object_get(obj); + kmem_cache_free(i915->luts, lut); + __i915_gem_object_release_unless_active(obj); } - mutex_unlock(&obj->base.dev->struct_mutex); + + mutex_unlock(&i915->drm.struct_mutex); } static unsigned long to_wait_timeout(s64 timeout_ns) @@ -4252,6 +4260,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, INIT_LIST_HEAD(&obj->global_link); INIT_LIST_HEAD(&obj->userfault_link); INIT_LIST_HEAD(&obj->vma_list); + INIT_LIST_HEAD(&obj->lut_list); INIT_LIST_HEAD(&obj->batch_pool_link); obj->ops = ops; @@ -4495,8 +4504,8 @@ void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) { lockdep_assert_held(&obj->base.dev->struct_mutex); - GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); - if (i915_gem_object_is_active(obj)) + if (!i915_gem_object_has_active_reference(obj) && + i915_gem_object_is_active(obj)) i915_gem_object_set_active_reference(obj); else i915_gem_object_put(obj); @@ -4888,12 +4897,16 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) if (!dev_priv->vmas) goto err_objects; + dev_priv->luts = KMEM_CACHE(i915_lut_handle, 0); + if (!dev_priv->luts) + goto err_vmas; + dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, SLAB_HWCACHE_ALIGN | SLAB_RECLAIM_ACCOUNT | SLAB_TYPESAFE_BY_RCU); if (!dev_priv->requests) - goto err_vmas; + goto err_luts; dev_priv->dependencies = KMEM_CACHE(i915_dependency, SLAB_HWCACHE_ALIGN | @@ -4937,6 +4950,8 @@ err_dependencies: kmem_cache_destroy(dev_priv->dependencies); err_requests: kmem_cache_destroy(dev_priv->requests); +err_luts: + kmem_cache_destroy(dev_priv->luts); err_vmas: kmem_cache_destroy(dev_priv->vmas); err_objects: @@ -4959,6 +4974,7 @@ void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) kmem_cache_destroy(dev_priv->priorities); kmem_cache_destroy(dev_priv->dependencies); kmem_cache_destroy(dev_priv->requests); + kmem_cache_destroy(dev_priv->luts); kmem_cache_destroy(dev_priv->vmas); kmem_cache_destroy(dev_priv->objects); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 86ac74a8a5b2..58a2a44f88bd 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -93,69 +93,28 @@ #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 -/* Initial size (as log2) to preallocate the handle->object hashtable */ -#define VMA_HT_BITS 2u /* 4 x 2 pointers, 64 bytes minimum */ - -static void resize_vma_ht(struct work_struct *work) +static void lut_close(struct i915_gem_context *ctx) { - struct i915_gem_context_vma_lut *lut = - container_of(work, typeof(*lut), resize); - unsigned int bits, new_bits, size, i; - struct hlist_head *new_ht; + struct i915_lut_handle *lut, *ln; + struct radix_tree_iter iter; + void __rcu **slot; - GEM_BUG_ON(!(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)); - - bits = 1 + ilog2(4*lut->ht_count/3 + 1); - new_bits = min_t(unsigned int, - max(bits, VMA_HT_BITS), - sizeof(unsigned int) * BITS_PER_BYTE - 1); - if (new_bits == lut->ht_bits) - goto out; - - new_ht = kzalloc(sizeof(*new_ht)<ht_bits); - for (i = 0; i < size; i++) { - struct i915_vma *vma; - struct hlist_node *tmp; - - hlist_for_each_entry_safe(vma, tmp, &lut->ht[i], ctx_node) - hlist_add_head(&vma->ctx_node, - &new_ht[hash_32(vma->ctx_handle, - new_bits)]); + list_for_each_entry_safe(lut, ln, &ctx->handles_list, ctx_link) { + list_del(&lut->obj_link); + kmem_cache_free(ctx->i915->luts, lut); } - kvfree(lut->ht); - lut->ht = new_ht; - lut->ht_bits = new_bits; -out: - smp_store_release(&lut->ht_size, BIT(bits)); - GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); -} -static void vma_lut_free(struct i915_gem_context *ctx) -{ - struct i915_gem_context_vma_lut *lut = &ctx->vma_lut; - unsigned int i, size; + radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) { + struct i915_vma *vma = rcu_dereference_raw(*slot); + struct drm_i915_gem_object *obj = vma->obj; - if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) - cancel_work_sync(&lut->resize); + radix_tree_iter_delete(&ctx->handles_vma, &iter, slot); - size = BIT(lut->ht_bits); - for (i = 0; i < size; i++) { - struct i915_vma *vma; + if (!i915_vma_is_ggtt(vma)) + i915_vma_close(vma); - hlist_for_each_entry(vma, &lut->ht[i], ctx_node) { - vma->obj->vma_hashed = NULL; - vma->ctx = NULL; - i915_vma_put(vma); - } + __i915_gem_object_release_unless_active(obj); } - kvfree(lut->ht); } static void i915_gem_context_free(struct i915_gem_context *ctx) @@ -165,7 +124,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx) lockdep_assert_held(&ctx->i915->drm.struct_mutex); GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); - vma_lut_free(ctx); i915_ppgtt_put(ctx->ppgtt); for (i = 0; i < I915_NUM_ENGINES; i++) { @@ -239,8 +197,11 @@ void i915_gem_context_release(struct kref *ref) static void context_close(struct i915_gem_context *ctx) { i915_gem_context_set_closed(ctx); + + lut_close(ctx); if (ctx->ppgtt) i915_ppgtt_close(&ctx->ppgtt->base); + ctx->file_priv = ERR_PTR(-EBADF); i915_gem_context_put(ctx); } @@ -313,16 +274,8 @@ __create_hw_context(struct drm_i915_private *dev_priv, ctx->i915 = dev_priv; ctx->priority = I915_PRIORITY_NORMAL; - ctx->vma_lut.ht_bits = VMA_HT_BITS; - ctx->vma_lut.ht_size = BIT(VMA_HT_BITS); - BUILD_BUG_ON(BIT(VMA_HT_BITS) == I915_CTX_RESIZE_IN_PROGRESS); - ctx->vma_lut.ht = kcalloc(ctx->vma_lut.ht_size, - sizeof(*ctx->vma_lut.ht), - GFP_KERNEL); - if (!ctx->vma_lut.ht) - goto err_out; - - INIT_WORK(&ctx->vma_lut.resize, resize_vma_ht); + INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); + INIT_LIST_HEAD(&ctx->handles_list); /* Default context will never have a file_priv */ ret = DEFAULT_CONTEXT_HANDLE; @@ -372,8 +325,6 @@ err_pid: put_pid(ctx->pid); idr_remove(&file_priv->context_idr, ctx->user_handle); err_lut: - kvfree(ctx->vma_lut.ht); -err_out: context_close(ctx); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 2d02918a449e..44688e22a5c2 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -27,6 +27,7 @@ #include #include +#include struct pid; @@ -149,32 +150,6 @@ struct i915_gem_context { /** ggtt_offset_bias: placement restriction for context objects */ u32 ggtt_offset_bias; - struct i915_gem_context_vma_lut { - /** ht_size: last request size to allocate the hashtable for. */ - unsigned int ht_size; -#define I915_CTX_RESIZE_IN_PROGRESS BIT(0) - /** ht_bits: real log2(size) of hashtable. */ - unsigned int ht_bits; - /** ht_count: current number of entries inside the hashtable */ - unsigned int ht_count; - - /** ht: the array of buckets comprising the simple hashtable */ - struct hlist_head *ht; - - /** - * resize: After an execbuf completes, we check the load factor - * of the hashtable. If the hashtable is too full, or too empty, - * we schedule a task to resize the hashtable. During the - * resize, the entries are moved between different buckets and - * so we cannot simultaneously read the hashtable as it is - * being resized (unlike rhashtable). Therefore we treat the - * active work as a strong barrier, pausing a subsequent - * execbuf to wait for the resize worker to complete, if - * required. - */ - struct work_struct resize; - } vma_lut; - /** engine: per-engine logical HW state */ struct intel_context { struct i915_vma *state; @@ -205,6 +180,18 @@ struct i915_gem_context { /** remap_slice: Bitmask of cache lines that need remapping */ u8 remap_slice; + + /** handles_vma: rbtree to look up our context specific obj/vma for + * the user handle. (user handles are per fd, but the binding is + * per vm, which may be one per context or shared with the global GTT) + */ + struct radix_tree_root handles_vma; + + /** handles_list: reverse list of all the rbtree entries in use for + * this context, which allows us to free all the allocations on + * context close. + */ + struct list_head handles_list; }; static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 95e461259d24..9f1057c4cf1c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -450,9 +450,7 @@ eb_validate_vma(struct i915_execbuffer *eb, } static int -eb_add_vma(struct i915_execbuffer *eb, - unsigned int i, struct i915_vma *vma, - unsigned int flags) +eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma) { struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; int err; @@ -482,7 +480,7 @@ eb_add_vma(struct i915_execbuffer *eb, * to find the right target VMA when doing relocations. */ eb->vma[i] = vma; - eb->flags[i] = entry->flags | flags; + eb->flags[i] = entry->flags; vma->exec_flags = &eb->flags[i]; err = 0; @@ -647,19 +645,6 @@ static int eb_reserve(struct i915_execbuffer *eb) } while (1); } -static inline struct hlist_head * -ht_head(const struct i915_gem_context_vma_lut *lut, u32 handle) -{ - return &lut->ht[hash_32(handle, lut->ht_bits)]; -} - -static inline bool -ht_needs_resize(const struct i915_gem_context_vma_lut *lut) -{ - return (4*lut->ht_count > 3*lut->ht_size || - 4*lut->ht_count + 1 < lut->ht_size); -} - static unsigned int eb_batch_index(const struct i915_execbuffer *eb) { if (eb->args->flags & I915_EXEC_BATCH_FIRST) @@ -688,7 +673,7 @@ static int eb_select_context(struct i915_execbuffer *eb) static int eb_lookup_vmas(struct i915_execbuffer *eb) { - struct i915_gem_context_vma_lut *lut = &eb->ctx->vma_lut; + struct radix_tree_root *handles_vma = &eb->ctx->handles_vma; struct drm_i915_gem_object *uninitialized_var(obj); unsigned int i; int err; @@ -702,24 +687,14 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) INIT_LIST_HEAD(&eb->relocs); INIT_LIST_HEAD(&eb->unbound); - if (unlikely(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)) - flush_work(&lut->resize); - GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); - for (i = 0; i < eb->buffer_count; i++) { u32 handle = eb->exec[i].handle; - struct hlist_head *hl = ht_head(lut, handle); - unsigned int flags = 0; + struct i915_lut_handle *lut; struct i915_vma *vma; - hlist_for_each_entry(vma, hl, ctx_node) { - GEM_BUG_ON(vma->ctx != eb->ctx); - - if (vma->ctx_handle != handle) - continue; - + vma = radix_tree_lookup(handles_vma, handle); + if (likely(vma)) goto add_vma; - } obj = i915_gem_object_lookup(eb->file, handle); if (unlikely(!obj)) { @@ -733,26 +708,28 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) goto err_obj; } - /* First come, first served */ - if (!vma->ctx) { - vma->ctx = eb->ctx; - vma->ctx_handle = handle; - hlist_add_head(&vma->ctx_node, hl); - lut->ht_count++; - lut->ht_size |= I915_CTX_RESIZE_IN_PROGRESS; - if (i915_vma_is_ggtt(vma)) { - GEM_BUG_ON(obj->vma_hashed); - obj->vma_hashed = vma; - } - - /* transfer ref to ctx */ - obj = NULL; - } else { - flags = __EXEC_OBJECT_HAS_REF; + lut = kmem_cache_alloc(eb->i915->luts, GFP_KERNEL); + if (unlikely(!lut)) { + err = -ENOMEM; + goto err_obj; } + err = radix_tree_insert(handles_vma, handle, vma); + if (unlikely(err)) { + kfree(lut); + goto err_obj; + } + + list_add(&lut->obj_link, &obj->lut_list); + list_add(&lut->ctx_link, &eb->ctx->handles_list); + lut->ctx = eb->ctx; + lut->handle = handle; + + /* transfer ref to ctx */ + obj = NULL; + add_vma: - err = eb_add_vma(eb, i, vma, flags); + err = eb_add_vma(eb, i, vma); if (unlikely(err)) goto err_obj; @@ -760,13 +737,6 @@ add_vma: GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); } - if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) { - if (ht_needs_resize(lut)) - queue_work(system_highpri_wq, &lut->resize); - else - lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; - } - /* take note of the batch buffer before we might reorder the lists */ i = eb_batch_index(eb); eb->batch = eb->vma[i]; @@ -794,7 +764,6 @@ err_obj: i915_gem_object_put(obj); err_vma: eb->vma[i] = NULL; - lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; return err; } diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h index 3baa341432db..c30d8f808185 100644 --- a/drivers/gpu/drm/i915/i915_gem_object.h +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -38,6 +38,19 @@ struct drm_i915_gem_object; +/* + * struct i915_lut_handle tracks the fast lookups from handle to vma used + * for execbuf. Although we use a radixtree for that mapping, in order to + * remove them as the object or context is closed, we need a secondary list + * and a translation entry (i915_lut_handle). + */ +struct i915_lut_handle { + struct list_head obj_link; + struct list_head ctx_link; + struct i915_gem_context *ctx; + u32 handle; +}; + struct drm_i915_gem_object_ops { unsigned int flags; #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0) @@ -89,7 +102,15 @@ struct drm_i915_gem_object { * They are also added to @vma_list for easy iteration. */ struct rb_root vma_tree; - struct i915_vma *vma_hashed; + + /** + * @lut_list: List of vma lookup entries in use for this object. + * + * If this object is closed, we need to remove all of its VMA from + * the fast lookup index in associated contexts; @lut_list provides + * this translation from object to context->handles_vma. + */ + struct list_head lut_list; /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 958be0a95960..02d1a5eacb00 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -597,33 +597,11 @@ static void i915_vma_destroy(struct i915_vma *vma) kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); } -void i915_vma_unlink_ctx(struct i915_vma *vma) -{ - struct i915_gem_context *ctx = vma->ctx; - - if (ctx->vma_lut.ht_size & I915_CTX_RESIZE_IN_PROGRESS) { - cancel_work_sync(&ctx->vma_lut.resize); - ctx->vma_lut.ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; - } - - __hlist_del(&vma->ctx_node); - ctx->vma_lut.ht_count--; - - if (i915_vma_is_ggtt(vma)) - vma->obj->vma_hashed = NULL; - vma->ctx = NULL; - - i915_vma_put(vma); -} - void i915_vma_close(struct i915_vma *vma) { GEM_BUG_ON(i915_vma_is_closed(vma)); vma->flags |= I915_VMA_CLOSED; - if (vma->ctx) - i915_vma_unlink_ctx(vma); - list_del(&vma->obj_link); rb_erase(&vma->obj_node, &vma->obj->vma_tree); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 5c49506d14bc..1fd61e88cfd0 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -115,10 +115,6 @@ struct i915_vma { unsigned int *exec_flags; struct hlist_node exec_node; u32 exec_handle; - - struct i915_gem_context *ctx; - struct hlist_node ctx_node; - u32 ctx_handle; }; struct i915_vma * diff --git a/drivers/gpu/drm/i915/selftests/mock_context.c b/drivers/gpu/drm/i915/selftests/mock_context.c index d436f2d5089b..098ce643ad07 100644 --- a/drivers/gpu/drm/i915/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/selftests/mock_context.c @@ -40,18 +40,13 @@ mock_context(struct drm_i915_private *i915, INIT_LIST_HEAD(&ctx->link); ctx->i915 = i915; - ctx->vma_lut.ht_bits = VMA_HT_BITS; - ctx->vma_lut.ht_size = BIT(VMA_HT_BITS); - ctx->vma_lut.ht = kcalloc(ctx->vma_lut.ht_size, - sizeof(*ctx->vma_lut.ht), - GFP_KERNEL); - if (!ctx->vma_lut.ht) - goto err_free; + INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); + INIT_LIST_HEAD(&ctx->handles_list); ret = ida_simple_get(&i915->contexts.hw_ida, 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); if (ret < 0) - goto err_vma_ht; + goto err_handles; ctx->hw_id = ret; if (name) { @@ -66,9 +61,7 @@ mock_context(struct drm_i915_private *i915, return ctx; -err_vma_ht: - kvfree(ctx->vma_lut.ht); -err_free: +err_handles: kfree(ctx); return NULL; diff --git a/lib/radix-tree.c b/lib/radix-tree.c index 898e87998417..3527eb364964 100644 --- a/lib/radix-tree.c +++ b/lib/radix-tree.c @@ -2022,6 +2022,7 @@ void radix_tree_iter_delete(struct radix_tree_root *root, if (__radix_tree_delete(root, iter->node, slot)) iter->index = iter->next_index; } +EXPORT_SYMBOL(radix_tree_iter_delete); /** * radix_tree_delete_item - delete an item from a radix tree From 0519bcb1737c58b91da23735394ecf26ae211fbc Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 16 Aug 2017 09:52:09 +0100 Subject: [PATCH 176/179] drm/i915: Trivial grammar fix s/opt of/opt out of/ in comment The word out was dropped from the sentence across the line break, put it back. Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20170816085210.4199-6-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 9f1057c4cf1c..3d74f3a27c13 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1346,7 +1346,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, * patching using the GPU (though that should be serialised by the * timeline). To be completely sure, and since we are required to * do relocations we are already stalling, disable the user's opt - * of our synchronisation. + * out of our synchronisation. */ *vma->exec_flags &= ~EXEC_OBJECT_ASYNC; From 636918f130296fac1ab195ba087688f91bd627f8 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 17 Aug 2017 15:47:19 +0100 Subject: [PATCH 177/179] drm/i915: Mark the GT as busy before idling the previous request In a synchronous setup, we may retire the last request before we complete allocating the next request. As the last request is retired, we queue a timer to mark the device as idle, and promptly have to execute ad cancel that timer once we complete allocating the request and need to keep the device awake. If we rearrange the mark_busy() to occur before we retire the previous request, we can skip this ping-pong. v2: Joonas pointed out that unreserve_seqno() was now doing more than doing seqno handling and should be renamed to reflect its wider purpose. That also highlighted the new asymmetry with reserve_seqno(), so fixup that and rename both to [un]reserve_engine(). Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20170817144719.10968-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_request.c | 88 +++++++++++++------------ 1 file changed, 45 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 9eedd33eb524..813a3b546d6e 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -244,27 +244,60 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) return reset_all_global_seqno(dev_priv, seqno - 1); } -static int reserve_seqno(struct intel_engine_cs *engine) +static void mark_busy(struct drm_i915_private *i915) { + if (i915->gt.awake) + return; + + GEM_BUG_ON(!i915->gt.active_requests); + + intel_runtime_pm_get_noresume(i915); + i915->gt.awake = true; + + intel_enable_gt_powersave(i915); + i915_update_gfx_val(i915); + if (INTEL_GEN(i915) >= 6) + gen6_rps_busy(i915); + + queue_delayed_work(i915->wq, + &i915->gt.retire_work, + round_jiffies_up_relative(HZ)); +} + +static int reserve_engine(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; u32 active = ++engine->timeline->inflight_seqnos; u32 seqno = engine->timeline->seqno; int ret; /* Reservation is fine until we need to wrap around */ - if (likely(!add_overflows(seqno, active))) - return 0; - - ret = reset_all_global_seqno(engine->i915, 0); - if (ret) { - engine->timeline->inflight_seqnos--; - return ret; + if (unlikely(add_overflows(seqno, active))) { + ret = reset_all_global_seqno(i915, 0); + if (ret) { + engine->timeline->inflight_seqnos--; + return ret; + } } + if (!i915->gt.active_requests++) + mark_busy(i915); + return 0; } -static void unreserve_seqno(struct intel_engine_cs *engine) +static void unreserve_engine(struct intel_engine_cs *engine) { + struct drm_i915_private *i915 = engine->i915; + + if (!--i915->gt.active_requests) { + /* Cancel the mark_busy() from our reserve_engine() */ + GEM_BUG_ON(!i915->gt.awake); + mod_delayed_work(i915->wq, + &i915->gt.idle_work, + msecs_to_jiffies(100)); + } + GEM_BUG_ON(!engine->timeline->inflight_seqnos); engine->timeline->inflight_seqnos--; } @@ -333,13 +366,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) list_del_init(&request->link); spin_unlock_irq(&engine->timeline->lock); - if (!--request->i915->gt.active_requests) { - GEM_BUG_ON(!request->i915->gt.awake); - mod_delayed_work(request->i915->wq, - &request->i915->gt.idle_work, - msecs_to_jiffies(100)); - } - unreserve_seqno(request->engine); + unreserve_engine(request->engine); advance_ring(request); free_capture_list(request); @@ -575,7 +602,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, return ERR_CAST(ring); GEM_BUG_ON(!ring); - ret = reserve_seqno(engine); + ret = reserve_engine(engine); if (ret) goto err_unpin; @@ -681,7 +708,7 @@ err_ctx: kmem_cache_free(dev_priv->requests, req); err_unreserve: - unreserve_seqno(engine); + unreserve_engine(engine); err_unpin: engine->context_unpin(engine, ctx); return ERR_PTR(ret); @@ -863,28 +890,6 @@ i915_gem_request_await_object(struct drm_i915_gem_request *to, return ret; } -static void i915_gem_mark_busy(const struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; - - if (dev_priv->gt.awake) - return; - - GEM_BUG_ON(!dev_priv->gt.active_requests); - - intel_runtime_pm_get_noresume(dev_priv); - dev_priv->gt.awake = true; - - intel_enable_gt_powersave(dev_priv); - i915_update_gfx_val(dev_priv); - if (INTEL_GEN(dev_priv) >= 6) - gen6_rps_busy(dev_priv); - - queue_delayed_work(dev_priv->wq, - &dev_priv->gt.retire_work, - round_jiffies_up_relative(HZ)); -} - /* * NB: This function is not allowed to fail. Doing so would mean the the * request is not being tracked for completion but the work itself is @@ -966,9 +971,6 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) list_add_tail(&request->ring_link, &ring->request_list); request->emitted_jiffies = jiffies; - if (!request->i915->gt.active_requests++) - i915_gem_mark_busy(engine); - /* Let the backend know a new request has arrived that may need * to adjust the existing execution schedule due to a high priority * request - i.e. we may want to preempt the current request in order From cd55a1fbd21a820b7dd85a208b3170aa0b06adfa Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 17 Aug 2017 13:55:41 +0300 Subject: [PATCH 178/179] drm/i915/bxt: use NULL for GPIO connection ID The commit 213e08ad60ba ("drm/i915/bxt: add bxt dsi gpio element support") enables GPIO support for Broxton based platforms. While using that API we might get into troubles in the future, because we can't rely on label name in the driver since vendor firmware might provide any GPIO pin there, e.g. "reset", and even mark it in _DSD (in which case the request will fail). To avoid inconsistency and potential issues we have two options: a) generate GPIO ACPI mapping table and supply it via acpi_dev_add_driver_gpios(), or b) just pass NULL as connection ID. The b) approach is much simpler and would work since the driver relies on GPIO indices only. Moreover, the _CRS fallback mechanism, when requesting GPIO, has been made stricter, and supplying non-NULL connection ID when neither _DSD, nor GPIO ACPI mapping is present, is making request fail. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101921 Fixes: f10e4bf6632b ("gpio: acpi: Even more tighten up ACPI GPIO lookups") Cc: Mika Kahola Cc: Jani Nikula Tested-by: Mika Kahola Signed-off-by: Andy Shevchenko Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20170817105541.63914-1-andriy.shevchenko@linux.intel.com --- drivers/gpu/drm/i915/intel_dsi_vbt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c index 7158c7ce9c09..91c07b0c8db9 100644 --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c @@ -306,7 +306,7 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, if (!gpio_desc) { gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, - "panel", gpio_index, + NULL, gpio_index, value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH); From a42894ebb50d831ec0b7ee9bee7f5a5a37bad7e1 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 18 Aug 2017 22:40:45 +0200 Subject: [PATCH 179/179] drm/i915: Update DRIVER_DATE to 20170818 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5b70bb9089fe..60267e375e88 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -80,8 +80,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20170731" -#define DRIVER_TIMESTAMP 1501488491 +#define DRIVER_DATE "20170818" +#define DRIVER_TIMESTAMP 1503088845 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and * WARN_ON()) for hw state sanity checks to check for unexpected conditions