clk: hi3660: fix wrong parent name of clk_mux_sysbus
Parent name of clk_mux_sysbus is not correct. This patch fixes it. Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -205,6 +205,8 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = {
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"clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
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};
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static const char *const
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clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"};
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static const char *const
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clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",};
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static const char *const
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@ -239,8 +241,8 @@ static const char *const
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clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",};
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static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = {
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{ HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sdio_sys_p,
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ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
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{ HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
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ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
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CLK_MUX_HIWORD_MASK, },
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{ HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
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ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
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