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arm64: dts: marvell: Add AP806-quad cache description

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Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Grzegorz Jaszczyk 2019-10-04 16:27:26 +02:00 committed by Gregory CLEMENT
parent ddda843324
commit 760cabcd6a
1 changed files with 42 additions and 0 deletions
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42
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
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@ -22,6 +22,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
@ -30,6 +37,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_0>;
};
cpu2: cpu@100 {
device_type = "cpu";
@ -38,6 +52,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
};
cpu3: cpu@101 {
device_type = "cpu";
@ -46,6 +67,27 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
};
l2_0: l2-cache0 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};
};