sh: Support type 1 accesses for SH7786 PCI.
This enables support for type 1 config space accesses on the SH7786 PCI controller. At the same time, add in some extra sanity checks for controller asserted errors. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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97e0214044
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7656e2486c
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@ -1,7 +1,7 @@
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/*
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/*
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* Generic SH7786 PCI-Express operations.
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* Generic SH7786 PCI-Express operations.
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*
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*
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* Copyright (C) 2009 Paul Mundt
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* Copyright (C) 2009 - 2010 Paul Mundt
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*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* This file is subject to the terms and conditions of the GNU General Public
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* License v2. See the file "COPYING" in the main directory of this archive
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* License v2. See the file "COPYING" in the main directory of this archive
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@ -35,22 +35,34 @@ static int sh7786_pcie_config_access(unsigned char access_type,
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if (devfn)
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Clear errors */
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pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
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/* Set the PIO address */
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/* Set the PIO address */
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pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
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pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
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(func << 16) | (where & ~3), SH4A_PCIEPAR);
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(func << 16) | (where & ~3), SH4A_PCIEPAR);
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/* Enable the configuration access */
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/* Enable the configuration access */
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pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
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if (bus->number) {
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/* Type 1 */
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pci_write_reg(chan, (1 << 31) | (1 << 8), SH4A_PCIEPCTLR);
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} else {
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/* Type 0 */
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pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
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}
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/* Check for errors */
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if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Check for master and target aborts */
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if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (access_type == PCI_ACCESS_READ)
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if (access_type == PCI_ACCESS_READ)
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*data = pci_read_reg(chan, SH4A_PCIEPDR);
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*data = pci_read_reg(chan, SH4A_PCIEPDR);
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else
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else
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pci_write_reg(chan, *data, SH4A_PCIEPDR);
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pci_write_reg(chan, *data, SH4A_PCIEPDR);
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/* Check for master and target aborts */
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if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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@ -69,8 +81,10 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
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spin_lock_irqsave(&sh7786_pcie_lock, flags);
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spin_lock_irqsave(&sh7786_pcie_lock, flags);
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ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
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ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
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devfn, where, &data);
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devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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if (ret != PCIBIOS_SUCCESSFUL) {
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*val = 0xffffffff;
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goto out;
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goto out;
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}
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if (size == 1)
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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*val = (data >> ((where & 3) << 3)) & 0xff;
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