Pull context-bitmap into release branch
This commit is contained in:
commit
7669a22592
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@ -461,6 +461,7 @@ setup_arch (char **cmdline_p)
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#endif
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cpu_init(); /* initialize the bootstrap CPU */
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mmu_context_init(); /* initialize context_id bitmap */
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#ifdef CONFIG_ACPI
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acpi_boot_init();
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@ -8,6 +8,8 @@
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* Modified RID allocation for SMP
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* Goutham Rao <goutham.rao@intel.com>
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* IPI based ptc implementation and A-step IPI implementation.
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* Rohit Seth <rohit.seth@intel.com>
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* Ken Chen <kenneth.w.chen@intel.com>
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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@ -16,78 +18,75 @@
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <asm/delay.h>
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#include <asm/mmu_context.h>
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#include <asm/pgalloc.h>
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#include <asm/pal.h>
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#include <asm/tlbflush.h>
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#include <asm/dma.h>
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static struct {
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unsigned long mask; /* mask of supported purge page-sizes */
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unsigned long max_bits; /* log2() of largest supported purge page-size */
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unsigned long max_bits; /* log2 of largest supported purge page-size */
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} purge;
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struct ia64_ctx ia64_ctx = {
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.lock = SPIN_LOCK_UNLOCKED,
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.next = 1,
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.limit = (1 << 15) - 1, /* start out with the safe (architected) limit */
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.max_ctx = ~0U
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};
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DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
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/*
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* Initializes the ia64_ctx.bitmap array based on max_ctx+1.
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* Called after cpu_init() has setup ia64_ctx.max_ctx based on
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* maximum RID that is supported by boot CPU.
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*/
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void __init
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mmu_context_init (void)
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{
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ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
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ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
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}
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/*
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* Acquire the ia64_ctx.lock before calling this function!
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*/
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void
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wrap_mmu_context (struct mm_struct *mm)
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{
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unsigned long tsk_context, max_ctx = ia64_ctx.max_ctx;
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struct task_struct *tsk;
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int i;
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int i, cpu;
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unsigned long flush_bit;
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if (ia64_ctx.next > max_ctx)
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ia64_ctx.next = 300; /* skip daemons */
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ia64_ctx.limit = max_ctx + 1;
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for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
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flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
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ia64_ctx.bitmap[i] ^= flush_bit;
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}
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/* use offset at 300 to skip daemons */
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ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, 300);
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ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, ia64_ctx.next);
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/*
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* Scan all the task's mm->context and set proper safe range
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* can't call flush_tlb_all() here because of race condition
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* with O(1) scheduler [EF]
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*/
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read_lock(&tasklist_lock);
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repeat:
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for_each_process(tsk) {
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if (!tsk->mm)
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continue;
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tsk_context = tsk->mm->context;
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if (tsk_context == ia64_ctx.next) {
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if (++ia64_ctx.next >= ia64_ctx.limit) {
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/* empty range: reset the range limit and start over */
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if (ia64_ctx.next > max_ctx)
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ia64_ctx.next = 300;
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ia64_ctx.limit = max_ctx + 1;
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goto repeat;
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}
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}
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if ((tsk_context > ia64_ctx.next) && (tsk_context < ia64_ctx.limit))
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ia64_ctx.limit = tsk_context;
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}
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read_unlock(&tasklist_lock);
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/* can't call flush_tlb_all() here because of race condition with O(1) scheduler [EF] */
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{
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int cpu = get_cpu(); /* prevent preemption/migration */
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for_each_online_cpu(i) {
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if (i != cpu)
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per_cpu(ia64_need_tlb_flush, i) = 1;
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}
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put_cpu();
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}
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cpu = get_cpu(); /* prevent preemption/migration */
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for_each_online_cpu(i)
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if (i != cpu)
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per_cpu(ia64_need_tlb_flush, i) = 1;
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put_cpu();
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local_flush_tlb_all();
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}
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void
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ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start, unsigned long end, unsigned long nbits)
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ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned long nbits)
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{
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static DEFINE_SPINLOCK(ptcg_lock);
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@ -135,7 +134,8 @@ local_flush_tlb_all (void)
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}
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void
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flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end)
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flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long size = end - start;
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@ -149,7 +149,8 @@ flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long
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#endif
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nbits = ia64_fls(size + 0xfff);
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while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits))
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while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
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(nbits < purge.max_bits))
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++nbits;
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if (nbits > purge.max_bits)
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nbits = purge.max_bits;
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@ -191,5 +192,5 @@ ia64_tlb_init (void)
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local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
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local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
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local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
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local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
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}
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@ -7,12 +7,13 @@
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*/
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/*
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* Routines to manage the allocation of task context numbers. Task context numbers are
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* used to reduce or eliminate the need to perform TLB flushes due to context switches.
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* Context numbers are implemented using ia-64 region ids. Since the IA-64 TLB does not
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* consider the region number when performing a TLB lookup, we need to assign a unique
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* region id to each region in a process. We use the least significant three bits in a
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* region id for this purpose.
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* Routines to manage the allocation of task context numbers. Task context
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* numbers are used to reduce or eliminate the need to perform TLB flushes
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* due to context switches. Context numbers are implemented using ia-64
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* region ids. Since the IA-64 TLB does not consider the region number when
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* performing a TLB lookup, we need to assign a unique region id to each
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* region in a process. We use the least significant three bits in aregion
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* id for this purpose.
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*/
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#define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */
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@ -32,13 +33,17 @@
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struct ia64_ctx {
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spinlock_t lock;
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unsigned int next; /* next context number to use */
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unsigned int limit; /* next >= limit => must call wrap_mmu_context() */
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unsigned int max_ctx; /* max. context value supported by all CPUs */
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unsigned int limit; /* available free range */
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unsigned int max_ctx; /* max. context value supported by all CPUs */
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/* call wrap_mmu_context when next >= max */
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unsigned long *bitmap; /* bitmap size is max_ctx+1 */
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unsigned long *flushmap;/* pending rid to be flushed */
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};
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extern struct ia64_ctx ia64_ctx;
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DECLARE_PER_CPU(u8, ia64_need_tlb_flush);
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extern void mmu_context_init (void);
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extern void wrap_mmu_context (struct mm_struct *mm);
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static inline void
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}
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/*
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* When the context counter wraps around all TLBs need to be flushed because an old
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* context number might have been reused. This is signalled by the ia64_need_tlb_flush
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* per-CPU variable, which is checked in the routine below. Called by activate_mm().
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* <efocht@ess.nec.de>
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* When the context counter wraps around all TLBs need to be flushed because
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* an old context number might have been reused. This is signalled by the
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* ia64_need_tlb_flush per-CPU variable, which is checked in the routine
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* below. Called by activate_mm(). <efocht@ess.nec.de>
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*/
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static inline void
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delayed_tlb_flush (void)
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@ -60,11 +65,9 @@ delayed_tlb_flush (void)
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if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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{
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if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
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local_flush_tlb_all();
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__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
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}
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if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
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local_flush_tlb_all();
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__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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}
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unsigned long flags;
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nv_mm_context_t context = mm->context;
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if (unlikely(!context)) {
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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{
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/* re-check, now that we've got the lock: */
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context = mm->context;
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if (context == 0) {
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cpus_clear(mm->cpu_vm_mask);
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if (ia64_ctx.next >= ia64_ctx.limit)
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wrap_mmu_context(mm);
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mm->context = context = ia64_ctx.next++;
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}
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if (likely(context))
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goto out;
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spin_lock_irqsave(&ia64_ctx.lock, flags);
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/* re-check, now that we've got the lock: */
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context = mm->context;
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if (context == 0) {
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cpus_clear(mm->cpu_vm_mask);
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if (ia64_ctx.next >= ia64_ctx.limit) {
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ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, ia64_ctx.next);
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ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, ia64_ctx.next);
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if (ia64_ctx.next >= ia64_ctx.max_ctx)
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wrap_mmu_context(mm);
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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mm->context = context = ia64_ctx.next++;
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__set_bit(context, ia64_ctx.bitmap);
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}
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spin_unlock_irqrestore(&ia64_ctx.lock, flags);
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out:
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/*
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* Ensure we're not starting to use "context" before any old
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* uses of it are gone from our TLB.
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}
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/*
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* Initialize context number to some sane value. MM is guaranteed to be a brand-new
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* address-space, so no TLB flushing is needed, ever.
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* Initialize context number to some sane value. MM is guaranteed to be a
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* brand-new address-space, so no TLB flushing is needed, ever.
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*/
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static inline int
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init_new_context (struct task_struct *p, struct mm_struct *mm)
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@ -162,7 +172,10 @@ activate_context (struct mm_struct *mm)
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if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
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cpu_set(smp_processor_id(), mm->cpu_vm_mask);
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reload_context(context);
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/* in the unlikely event of a TLB-flush by another thread, redo the load: */
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/*
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* in the unlikely event of a TLB-flush by another thread,
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* redo the load.
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*/
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} while (unlikely(context != mm->context));
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}
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@ -175,8 +188,8 @@ static inline void
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activate_mm (struct mm_struct *prev, struct mm_struct *next)
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{
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/*
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* We may get interrupts here, but that's OK because interrupt handlers cannot
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* touch user-space.
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* We may get interrupts here, but that's OK because interrupt
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* handlers cannot touch user-space.
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*/
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ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
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activate_context(next);
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@ -51,6 +51,7 @@ flush_tlb_mm (struct mm_struct *mm)
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if (!mm)
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return;
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set_bit(mm->context, ia64_ctx.flushmap);
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mm->context = 0;
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if (atomic_read(&mm->mm_users) == 0)
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