MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume()
commitc14af233fb
upstream. The original MIPS hibernate code flushes cache and TLB entries in swsusp_arch_resume(). But they are removed in Commit44eeab6741
(MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross- CPU flush is surely unnecessary because all but the local CPU have already been disabled. But a local flush (at least the TLB flush) is needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is very easy to produce a kernel panic (kernel page fault, or unaligned access). The root cause is E1000E driver use vzalloc_node() to allocate pages, the stale TLB entries of the booting kernel will be misused by the resumed target kernel. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6643/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -43,6 +43,7 @@ LEAF(swsusp_arch_resume)
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bne t1, t3, 1b
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PTR_L t0, PBE_NEXT(t0)
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bnez t0, 0b
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jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
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PTR_LA t0, saved_regs
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PTR_L ra, PT_R31(t0)
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PTR_L sp, PT_R29(t0)
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