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Pin control bulk changes for the v4.17 kernel cycle: 

New drivers:
 
 - Qualcomm SDM845: this is their new flagship SoC platform
   which seems to be targeted at premium mobile handsets.
 
 - Renesas R-Car M3-N SoC.
 
 - Renesas R8A77980 SoC.
 
 - NXP (ex Freescale) i.MX 6SLL SoC.
 
 - Mediatek MT2712 SoC.
 
 - Allwinner H6 SoC.
 
 Improvements:
 
 - Uniphier adds a few new functions and pins.
 
 - Renesas refactorings and additional pin definitions.
 
 - Improved pin groups for Axis Artpec6.
 
 Cleanup:
 
 - Drop the TZ1090 drivers. This platform is no longer
   maintained and is being deleted.
 
 - Drop ST-Ericsson U8540/U9540 support as this was never
   productified.
 
 - Overall minor fixes and janitorial.
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Merge tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control bulk updates from Linus Walleij:
 "New drivers:

   - Qualcomm SDM845: this is their new flagship SoC platform which
     seems to be targeted at premium mobile handsets.

   - Renesas R-Car M3-N SoC.

   - Renesas R8A77980 SoC.

   - NXP (ex Freescale) i.MX 6SLL SoC.

   - Mediatek MT2712 SoC.

   - Allwinner H6 SoC.

  Improvements:

   - Uniphier adds a few new functions and pins.

   - Renesas refactorings and additional pin definitions.

   - Improved pin groups for Axis Artpec6.

  Cleanup:

   - Drop the TZ1090 drivers. This platform is no longer maintained and
     is being deleted.

   - Drop ST-Ericsson U8540/U9540 support as this was never
     productified.

   - Overall minor fixes and janitorial"

* tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
  pinctrl: uniphier: add UART hardware flow control pin-mux settings
  pinctrl: sunxi: add support for the Allwinner H6 main pin controller
  pinctrl: sunxi: change irq_bank_base to irq_bank_map
  pinctrl: sunxi: introduce IRQ bank conversion function
  pinctrl: sunxi: refactor irq related register function to have desc
  pinctrl: msm8998: Remove owner assignment from platform_driver
  pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group
  pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings
  pinctrl/amd: poll InterruptEnable bits in enable_irq
  pinctrl: ocelot: fix gpio direction
  pinctrl: mtk: fix check warnings.
  pintcrl: mtk: support bias-disable of generic and special pins simultaneously
  pinctrl: add mt2712 pinctrl driver
  pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0
  pinctrl: imx: Add pinctrl driver support for imx6sll
  dt-bindings: imx: update pinctrl doc for imx6sll
  pinctrl: intel: Implement intel_gpio_get_direction callback
  pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependency
  pinctrl: mediatek: mtk-common: use true and false for boolean values
  pinctrl: sunxi: always look for apb block
  ...
This commit is contained in:
Linus Torvalds 2018-04-03 12:20:54 -07:00
parent dc73d6a8d4 4fc97ef94b
commit 77624cd2a7
82 changed files with 13690 additions and 7622 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

178
Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt Normal file
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@ -0,0 +1,178 @@
Actions Semi S900 Pin Controller
This binding describes the pin controller found in the S900 SoC.
Required Properties:
- compatible: Should be "actions,s900-pinctrl"
- reg: Should contain the register base address and size of
the pin controller.
- clocks: phandle of the clock feeding the pin controller
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
Pinmux functions are available only for the pin groups while pinconf
parameters are available for both pin groups and individual pins.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
Required Properties:
- pins: An array of strings, each string containing the name of a pin.
These pins are used for selecting the pull control and schmitt
trigger parameters. The following are the list of pins
available:
eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3
- groups: An array of strings, each string containing the name of a pin
group. These pin groups are used for selecting the pinmux
functions.
lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
These pin groups are used for selecting the drive strength
parameters.
sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv
These pin groups are used for selecting the slew rate
parameters.
sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
sensor0_sr
- function: An array of strings, each string containing the name of the
pinmux functions. These functions can only be selected by
the corresponding pin groups. The following are the list of
pinmux functions available:
eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
nand1, spdif, sirq0, sirq1, sirq2
Optional Properties:
- bias-bus-hold: No arguments. The specified pins should retain the previous
state value.
- bias-high-impedance: No arguments. The specified pins should be configured
as high impedance.
- bias-pull-down: No arguments. The specified pins should be configured as
pull down.
- bias-pull-up: No arguments. The specified pins should be configured as
pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
pins
- slew-rate: Integer. Sets slew rate for the specified pins.
Valid values are:
<0> - Slow
<1> - Fast
- drive-strength: Integer. Selects the drive strength for the specified
pins in mA.
Valid values are:
<2>
<4>
<8>
<12>
Example:
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s900-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
clocks = <&cmu CLK_GPIO>;
uart2-default: uart2-default {
pinmux {
groups = "lvds_oep_odn_mfp";
function = "uart2";
};
pinconf {
groups = "lvds_oep_odn_drv";
drive-strength = <12>;
};
};
};

1
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
View File

@ -27,6 +27,7 @@ Required properties:
"allwinner,sun50i-a64-pinctrl"
"allwinner,sun50i-a64-r-pinctrl"
"allwinner,sun50i-h5-pinctrl"
"allwinner,sun50i-h6-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the

16
Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
View File

@ -19,8 +19,10 @@ Required subnode-properties:
Available functions and groups (function: group0, group1...):
gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,
uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,
uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,
uart5nocts
cpuclkout: cpuclkoutgrp0
udlclkout: udlclkoutgrp0
i2c1: i2c1grp0
@ -32,12 +34,12 @@ Required subnode-properties:
spi0: spi0grp0
spi1: spi1grp0
pciedebug: pciedebuggrp0
uart0: uart0grp0, uart0grp1
uart1: uart1grp0
uart2: uart2grp0, uart2grp1
uart0: uart0grp0, uart0grp1, uart0grp2
uart1: uart1grp0, uart1grp1
uart2: uart2grp0, uart2grp1, uart2grp2
uart3: uart3grp0
uart4: uart4grp0
uart5: uart5grp0
uart4: uart4grp0, uart4grp1
uart5: uart5grp0, uart5grp1, uart5nocts
nand: nandgrp0
sdio0: sdio0grp0
sdio1: sdio1grp0

40
Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt Normal file
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@ -0,0 +1,40 @@
* Freescale i.MX6 SLL IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6sll-iomuxc"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
Reference Manual for detailed CONFIG settings.
CONFIG bits definition:
PAD_CTL_LVE (1 << 22)
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (0 << 6)
PAD_CTL_SPEED_MED (1 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_260ohm (1 << 3)
PAD_CTL_DSE_130ohm (2 << 3)
PAD_CTL_DSE_87ohm (3 << 3)
PAD_CTL_DSE_65ohm (4 << 3)
PAD_CTL_DSE_52ohm (5 << 3)
PAD_CTL_DSE_43ohm (6 << 3)
PAD_CTL_DSE_37ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx6sll-pinfunc.h in device tree source folder for all available
imx6sll PIN_FUNC_ID.

127
Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
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@ -1,127 +0,0 @@
ImgTec TZ1090 PDC pin controller
Required properties:
- compatible: "img,tz1090-pdc-pinctrl"
- reg: Should contain the register physical address and length of the
SOC_GPIO_CONTROL registers in the PDC register region.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
of subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function. For this reason, even seemingly boolean
values are actually tristates in this binding: unspecified, off, or on.
Unspecified is represented as an absent property, and off/on are represented as
integer values 0 and 1.
Required subnode-properties:
- tz1090,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- tz1090,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below, including
which pingroups can be muxed to them.
- supported generic pinconfig properties (for further details see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- bias-disable
- bias-high-impedance
- bias-bus-hold
- bias-pull-up
- bias-pull-down
- input-schmitt-enable
- input-schmitt-disable
- drive-strength: Integer, control drive strength of pins in mA.
2: 2mA
4: 4mA
8: 8mA
12: 12mA
- low-power-enable: Flag, power-on-start weak pull-down for invalid power.
- low-power-disable: Flag, power-on-start weak pull-down disabled.
Note that many of these properties are only valid for certain specific pins
or groups. See the TZ1090 TRM for complete details regarding which groups
support which functionality. The Linux pinctrl driver may also be a useful
reference.
Valid values for pin and group names are:
pins:
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
bias-bus-hold (which can also be provided to any of the groups below to set
it for all gpio pins in that group).
gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
mux groups:
These all support function.
gpio0
pins: gpio0.
function: ir_mod_stable_out.
gpio1
pins: gpio1.
function: ir_mod_power_out.
drive groups:
These support input-schmitt-enable, input-schmitt-disable,
drive-strength, low-power-enable, and low-power-disable.
pdc
pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
ext_power.
Example:
pinctrl_pdc: pinctrl@2006500 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pdc-pinctrl";
reg = <0x02006500 0x100>;
};
Example board file extracts:
&pinctrl_pdc {
pinctrl-names = "default";
pinctrl-0 = <&syswake_default>;
syswake_default: syswakes {
syswake_cfg {
tz1090,pins = "sys_wake0",
"sys_wake1",
"sys_wake2";
pull-up;
};
};
irmod_default: irmod {
gpio0_cfg {
tz1090,pins = "gpio0";
tz1090,function = "ir_mod_stable_out";
};
gpio1_cfg {
tz1090,pins = "gpio1";
tz1090,function = "ir_mod_power_out";
};
};
};
ir: ir@2006200 {
pinctrl-names = "default";
pinctrl-0 = <&irmod_default>;
};

227
Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
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@ -1,227 +0,0 @@
ImgTec TZ1090 pin controller
Required properties:
- compatible: "img,tz1090-pinctrl"
- reg: Should contain the register physical address and length of the pad
configuration registers (CR_PADS_* and CR_IF_CTL0).
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
TZ1090's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function. For this reason, even seemingly boolean
values are actually tristates in this binding: unspecified, off, or on.
Unspecified is represented as an absent property, and off/on are represented as
integer values 0 and 1.
Required subnode-properties:
- tz1090,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- tz1090,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below, including
which pingroups can be muxed to them.
- supported generic pinconfig properties (for further details see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- bias-disable
- bias-high-impedance
- bias-bus-hold
- bias-pull-up
- bias-pull-down
- input-schmitt-enable
- input-schmitt-disable
- drive-strength: Integer, control drive strength of pins in mA.
2: 2mA
4: 4mA
8: 8mA
12: 12mA
Note that many of these properties are only valid for certain specific pins
or groups. See the TZ1090 TRM for complete details regarding which groups
support which functionality. The Linux pinctrl driver may also be a useful
reference.
Valid values for pin and group names are:
gpio pins:
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
bias-bus-hold (which can also be provided to any of the groups below to set
it for all pins in that group).
They also all support the some form of muxing. Any pins which are contained
in one of the mux groups (see below) can be muxed only to the functions
supported by the mux group. All other pins can be muxed to the "perip"
function which enables them with their intended peripheral.
Different pins in the same mux group cannot be muxed to different functions,
however it is possible to mux only a subset of the pins in a mux group to a
particular function and leave the remaining pins unmuxed. This is useful if
the board connects certain pins in a group to other devices to be controlled
by GPIO, and you don't want the usual peripheral to have any control of the
pin.
ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
function: perip or those supported by pin's mux group.
other pins:
These other pins are part of various pin groups below, but can't be
controlled as GPIOs. They do however support bias-high-impediance,
bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
to any of the groups below to set it for all pins in that group).
clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
mux groups:
These all support function, and some support drive configs.
afe
pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
ant_sel1, gain0, gain1, gain2, gain3, gain4,
gain5, gain6, gain7.
function: afe, ts_out_0.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
drive-strength: supported.
pdm_d
pins: pdm_d.
function: pdm_dac, usb_vbus.
sdh
pins: sdh_cd, sdh_wp, sdh_clk_in.
function: sdh, sdio.
sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
sdio_d3.
function: sdio, sdh.
spi1_cs2
pins: spi1_cs2.
function: spi1_cs2, usb_vbus.
tft
pins: tft_red0, tft_red1, tft_red2, tft_red3,
tft_red4, tft_red5, tft_red6, tft_red7,
tft_green0, tft_green1, tft_green2, tft_green3,
tft_green4, tft_green5, tft_green6, tft_green7,
tft_blue0, tft_blue1, tft_blue2, tft_blue3,
tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_vdden_gd, tft_panelclk, tft_blank_ls,
tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
tft_pwrsave.
function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
lcd_trace, phy_ringosc.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
drive-strength: supported.
drive groups:
These all support input-schmitt-enable, input-schmitt-disable,
and drive-strength.
jtag
pins: tck, trst, tdi, tdo, tms.
scb1
pins: scb1_sdat, scb1_sclk.
scb2
pins: scb2_sdat, scb2_sclk.
spi0
pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
spi1
pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
uart
pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
uart1_txd, uart1_rxd.
drive_i2s
pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
drive_pdm
pins: clk_out0, pdm_b, pdm_a.
drive_scb0
pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
drive_sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
sdh_wp, sdh_cd, sdh_clk_in.
convenience groups:
These are just convenient groupings of pins and don't support any drive
configs.
uart0
pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
uart1
pins: uart1_rxd, uart1_txd.
scb0
pins: scb0_sclk, scb0_sdat.
i2s
pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_mclk.
Example:
pinctrl: pinctrl@2005800 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pinctrl";
reg = <0x02005800 0xe4>;
};
Example board file extract:
&pinctrl {
uart0_default: uart0 {
uart0_cfg {
tz1090,pins = "uart0_rxd",
"uart0_txd";
tz1090,function = "perip";
};
};
tft_default: tft {
tft_cfg {
tz1090,pins = "tft";
tz1090,function = "tft";
};
};
};
uart@2004b00 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_default>;
};

2
Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
View File

@ -45,6 +45,8 @@ Optional properties:
- first cell is the pin number
- second cell is used to specify flags.
- interrupt-controller: Marks the device node as a interrupt controller.
- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
the IRQ output as open drain active low.
Optional device specific properties:
- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices

4
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
View File

@ -76,12 +76,12 @@ Examples:
...
{
syscfg_pctl_a: syscfg_pctl_a@10005000 {
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg_pctl_b@1020c020 {
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};

176
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt Normal file
View File

@ -0,0 +1,176 @@
Qualcomm SDM845 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
SDM845 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,sdm845-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio149
Supports mux, bias and drive-strength
sdc2_clk, sdc2_cmd, sdc2_data
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
gpio, adsp_ext, agera_pll, atest_char, atest_tsens,
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
atest_usb12, atest_usb13, atest_usb2, atest_usb20,
atest_usb21, atest_usb22, atest_usb23, audio_ref,
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update,
lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1,
mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator,
pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti,
qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1,
qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4,
qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd,
sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0,
tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2,
tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync,
tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync,
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy,
vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
wlan2_adc1,
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@3400000 {
compatible = "qcom,sdm845-pinctrl";
reg = <0x03400000 0xc00000>;
interrupts = <GIC_SPI 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
qup9_active: qup9-active {
mux {
pins = "gpio4", "gpio5";
function = "qup9";
};
config {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-disable;
};
};
};

4
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
View File

@ -15,7 +15,7 @@ Required Properties:
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
@ -24,7 +24,9 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.

12
drivers/pinctrl/Kconfig
View File

@ -244,18 +244,6 @@ config PINCTRL_ST
select PINCONF
select GPIOLIB_IRQCHIP
config PINCTRL_TZ1090
bool "Toumaz Xenif TZ1090 pin control driver"
depends on SOC_TZ1090
select PINMUX
select GENERIC_PINCONF
config PINCTRL_TZ1090_PDC
bool "Toumaz Xenif TZ1090 PDC pin control driver"
depends on SOC_TZ1090
select PINMUX
select PINCONF
config PINCTRL_U300
bool "U300 pin controller driver"
depends on ARCH_U300

2
drivers/pinctrl/Makefile
View File

@ -31,8 +31,6 @@ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o

109
drivers/pinctrl/core.c
View File

@ -1416,6 +1416,7 @@ int pinctrl_register_mappings(const struct pinctrl_map *maps,
{
return pinctrl_register_map(maps, num_maps, true);
}
EXPORT_SYMBOL_GPL(pinctrl_register_mappings);
void pinctrl_unregister_map(const struct pinctrl_map *map)
{
@ -1586,6 +1587,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_pins);
static int pinctrl_groups_show(struct seq_file *s, void *what)
{
@ -1631,6 +1633,7 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_groups);
static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
{
@ -1664,6 +1667,7 @@ static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_gpioranges);
static int pinctrl_devices_show(struct seq_file *s, void *what)
{
@ -1690,6 +1694,7 @@ static int pinctrl_devices_show(struct seq_file *s, void *what)
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_devices);
static inline const char *map_type(enum pinctrl_map_type type)
{
@ -1743,6 +1748,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what)
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pinctrl_maps);
static int pinctrl_show(struct seq_file *s, void *what)
{
@ -1788,87 +1794,30 @@ static int pinctrl_show(struct seq_file *s, void *what)
return 0;
}
static int pinctrl_pins_open(struct inode *inode, struct file *file)
{
return single_open(file, pinctrl_pins_show, inode->i_private);
}
static int pinctrl_groups_open(struct inode *inode, struct file *file)
{
return single_open(file, pinctrl_groups_show, inode->i_private);
}
static int pinctrl_gpioranges_open(struct inode *inode, struct file *file)
{
return single_open(file, pinctrl_gpioranges_show, inode->i_private);
}
static int pinctrl_devices_open(struct inode *inode, struct file *file)
{
return single_open(file, pinctrl_devices_show, NULL);
}
static int pinctrl_maps_open(struct inode *inode, struct file *file)
{
return single_open(file, pinctrl_maps_show, NULL);
}
static int pinctrl_open(struct inode *inode, struct file *file)
{
return single_open(file, pinctrl_show, NULL);
}
static const struct file_operations pinctrl_pins_ops = {
.open = pinctrl_pins_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations pinctrl_groups_ops = {
.open = pinctrl_groups_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations pinctrl_gpioranges_ops = {
.open = pinctrl_gpioranges_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations pinctrl_devices_ops = {
.open = pinctrl_devices_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations pinctrl_maps_ops = {
.open = pinctrl_maps_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations pinctrl_ops = {
.open = pinctrl_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
DEFINE_SHOW_ATTRIBUTE(pinctrl);
static struct dentry *debugfs_root;
static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
{
struct dentry *device_root;
const char *debugfs_name;
device_root = debugfs_create_dir(dev_name(pctldev->dev),
debugfs_root);
if (pctldev->desc->name &&
strcmp(dev_name(pctldev->dev), pctldev->desc->name)) {
debugfs_name = devm_kasprintf(pctldev->dev, GFP_KERNEL,
"%s-%s", dev_name(pctldev->dev),
pctldev->desc->name);
if (!debugfs_name) {
pr_warn("failed to determine debugfs dir name for %s\n",
dev_name(pctldev->dev));
return;
}
} else {
debugfs_name = dev_name(pctldev->dev);
}
device_root = debugfs_create_dir(debugfs_name, debugfs_root);
pctldev->device_root = device_root;
if (IS_ERR(device_root) || !device_root) {
@ -1877,11 +1826,11 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
return;
}
debugfs_create_file("pins", S_IFREG | S_IRUGO,
device_root, pctldev, &pinctrl_pins_ops);
device_root, pctldev, &pinctrl_pins_fops);
debugfs_create_file("pingroups", S_IFREG | S_IRUGO,
device_root, pctldev, &pinctrl_groups_ops);
device_root, pctldev, &pinctrl_groups_fops);
debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
device_root, pctldev, &pinctrl_gpioranges_ops);
device_root, pctldev, &pinctrl_gpioranges_fops);
if (pctldev->desc->pmxops)
pinmux_init_device_debugfs(device_root, pctldev);
if (pctldev->desc->confops)
@ -1903,11 +1852,11 @@ static void pinctrl_init_debugfs(void)
}
debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
debugfs_root, NULL, &pinctrl_devices_ops);
debugfs_root, NULL, &pinctrl_devices_fops);
debugfs_create_file("pinctrl-maps", S_IFREG | S_IRUGO,
debugfs_root, NULL, &pinctrl_maps_ops);
debugfs_root, NULL, &pinctrl_maps_fops);
debugfs_create_file("pinctrl-handles", S_IFREG | S_IRUGO,
debugfs_root, NULL, &pinctrl_ops);
debugfs_root, NULL, &pinctrl_fops);
}
#else /* CONFIG_DEBUG_FS */

6
drivers/pinctrl/devicetree.c
View File

@ -122,8 +122,10 @@ static int dt_to_map_one_config(struct pinctrl *p,
/* OK let's just assume this will appear later then */
return -EPROBE_DEFER;
}
if (!pctldev)
pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
/* If we're creating a hog we can use the passed pctldev */
if (pctldev && (np_pctldev == p->dev->of_node))
break;
pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
if (pctldev)
break;
/* Do not defer probing of hogs (circular loop) */

7
drivers/pinctrl/freescale/Kconfig
View File

@ -82,6 +82,13 @@ config PINCTRL_IMX6SL
help
Say Y here to enable the imx6sl pinctrl driver
config PINCTRL_IMX6SLL
bool "IMX6SLL pinctrl driver"
depends on SOC_IMX6SLL
select PINCTRL_IMX
help
Say Y here to enable the imx6sll pinctrl driver
config PINCTRL_IMX6SX
bool "IMX6SX pinctrl driver"
depends on SOC_IMX6SX

1
drivers/pinctrl/freescale/Makefile
View File

@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
obj-$(CONFIG_PINCTRL_IMX6SLL) += pinctrl-imx6sll.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o

360
drivers/pinctrl/freescale/pinctrl-imx6sll.c Normal file
View File

@ -0,0 +1,360 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP.
*
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx6sll_pads {
MX6SLL_PAD_RESERVE0 = 0,
MX6SLL_PAD_RESERVE1 = 1,
MX6SLL_PAD_RESERVE2 = 2,
MX6SLL_PAD_RESERVE3 = 3,
MX6SLL_PAD_RESERVE4 = 4,
MX6SLL_PAD_WDOG_B = 5,
MX6SLL_PAD_REF_CLK_24M = 6,
MX6SLL_PAD_REF_CLK_32K = 7,
MX6SLL_PAD_PWM1 = 8,
MX6SLL_PAD_KEY_COL0 = 9,
MX6SLL_PAD_KEY_ROW0 = 10,
MX6SLL_PAD_KEY_COL1 = 11,
MX6SLL_PAD_KEY_ROW1 = 12,
MX6SLL_PAD_KEY_COL2 = 13,
MX6SLL_PAD_KEY_ROW2 = 14,
MX6SLL_PAD_KEY_COL3 = 15,
MX6SLL_PAD_KEY_ROW3 = 16,
MX6SLL_PAD_KEY_COL4 = 17,
MX6SLL_PAD_KEY_ROW4 = 18,
MX6SLL_PAD_KEY_COL5 = 19,
MX6SLL_PAD_KEY_ROW5 = 20,
MX6SLL_PAD_KEY_COL6 = 21,
MX6SLL_PAD_KEY_ROW6 = 22,
MX6SLL_PAD_KEY_COL7 = 23,
MX6SLL_PAD_KEY_ROW7 = 24,
MX6SLL_PAD_EPDC_DATA00 = 25,
MX6SLL_PAD_EPDC_DATA01 = 26,
MX6SLL_PAD_EPDC_DATA02 = 27,
MX6SLL_PAD_EPDC_DATA03 = 28,
MX6SLL_PAD_EPDC_DATA04 = 29,
MX6SLL_PAD_EPDC_DATA05 = 30,
MX6SLL_PAD_EPDC_DATA06 = 31,
MX6SLL_PAD_EPDC_DATA07 = 32,
MX6SLL_PAD_EPDC_DATA08 = 33,
MX6SLL_PAD_EPDC_DATA09 = 34,
MX6SLL_PAD_EPDC_DATA10 = 35,
MX6SLL_PAD_EPDC_DATA11 = 36,
MX6SLL_PAD_EPDC_DATA12 = 37,
MX6SLL_PAD_EPDC_DATA13 = 38,
MX6SLL_PAD_EPDC_DATA14 = 39,
MX6SLL_PAD_EPDC_DATA15 = 40,
MX6SLL_PAD_EPDC_SDCLK = 41,
MX6SLL_PAD_EPDC_SDLE = 42,
MX6SLL_PAD_EPDC_SDOE = 43,
MX6SLL_PAD_EPDC_SDSHR = 44,
MX6SLL_PAD_EPDC_SDCE0 = 45,
MX6SLL_PAD_EPDC_SDCE1 = 46,
MX6SLL_PAD_EPDC_SDCE2 = 47,
MX6SLL_PAD_EPDC_SDCE3 = 48,
MX6SLL_PAD_EPDC_GDCLK = 49,
MX6SLL_PAD_EPDC_GDOE = 50,
MX6SLL_PAD_EPDC_GDRL = 51,
MX6SLL_PAD_EPDC_GDSP = 52,
MX6SLL_PAD_EPDC_VCOM0 = 53,
MX6SLL_PAD_EPDC_VCOM1 = 54,
MX6SLL_PAD_EPDC_BDR0 = 55,
MX6SLL_PAD_EPDC_BDR1 = 56,
MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
MX6SLL_PAD_EPDC_PWR_COM = 61,
MX6SLL_PAD_EPDC_PWR_INT = 62,
MX6SLL_PAD_EPDC_PWR_STAT = 63,
MX6SLL_PAD_EPDC_PWR_WAKE = 64,
MX6SLL_PAD_LCD_CLK = 65,
MX6SLL_PAD_LCD_ENABLE = 66,
MX6SLL_PAD_LCD_HSYNC = 67,
MX6SLL_PAD_LCD_VSYNC = 68,
MX6SLL_PAD_LCD_RESET = 69,
MX6SLL_PAD_LCD_DATA00 = 70,
MX6SLL_PAD_LCD_DATA01 = 71,
MX6SLL_PAD_LCD_DATA02 = 72,
MX6SLL_PAD_LCD_DATA03 = 73,
MX6SLL_PAD_LCD_DATA04 = 74,
MX6SLL_PAD_LCD_DATA05 = 75,
MX6SLL_PAD_LCD_DATA06 = 76,
MX6SLL_PAD_LCD_DATA07 = 77,
MX6SLL_PAD_LCD_DATA08 = 78,
MX6SLL_PAD_LCD_DATA09 = 79,
MX6SLL_PAD_LCD_DATA10 = 80,
MX6SLL_PAD_LCD_DATA11 = 81,
MX6SLL_PAD_LCD_DATA12 = 82,
MX6SLL_PAD_LCD_DATA13 = 83,
MX6SLL_PAD_LCD_DATA14 = 84,
MX6SLL_PAD_LCD_DATA15 = 85,
MX6SLL_PAD_LCD_DATA16 = 86,
MX6SLL_PAD_LCD_DATA17 = 87,
MX6SLL_PAD_LCD_DATA18 = 88,
MX6SLL_PAD_LCD_DATA19 = 89,
MX6SLL_PAD_LCD_DATA20 = 90,
MX6SLL_PAD_LCD_DATA21 = 91,
MX6SLL_PAD_LCD_DATA22 = 92,
MX6SLL_PAD_LCD_DATA23 = 93,
MX6SLL_PAD_AUD_RXFS = 94,
MX6SLL_PAD_AUD_RXC = 95,
MX6SLL_PAD_AUD_RXD = 96,
MX6SLL_PAD_AUD_TXC = 97,
MX6SLL_PAD_AUD_TXFS = 98,
MX6SLL_PAD_AUD_TXD = 99,
MX6SLL_PAD_AUD_MCLK = 100,
MX6SLL_PAD_UART1_RXD = 101,
MX6SLL_PAD_UART1_TXD = 102,
MX6SLL_PAD_I2C1_SCL = 103,
MX6SLL_PAD_I2C1_SDA = 104,
MX6SLL_PAD_I2C2_SCL = 105,
MX6SLL_PAD_I2C2_SDA = 106,
MX6SLL_PAD_ECSPI1_SCLK = 107,
MX6SLL_PAD_ECSPI1_MOSI = 108,
MX6SLL_PAD_ECSPI1_MISO = 109,
MX6SLL_PAD_ECSPI1_SS0 = 110,
MX6SLL_PAD_ECSPI2_SCLK = 111,
MX6SLL_PAD_ECSPI2_MOSI = 112,
MX6SLL_PAD_ECSPI2_MISO = 113,
MX6SLL_PAD_ECSPI2_SS0 = 114,
MX6SLL_PAD_SD1_CLK = 115,
MX6SLL_PAD_SD1_CMD = 116,
MX6SLL_PAD_SD1_DATA0 = 117,
MX6SLL_PAD_SD1_DATA1 = 118,
MX6SLL_PAD_SD1_DATA2 = 119,
MX6SLL_PAD_SD1_DATA3 = 120,
MX6SLL_PAD_SD1_DATA4 = 121,
MX6SLL_PAD_SD1_DATA5 = 122,
MX6SLL_PAD_SD1_DATA6 = 123,
MX6SLL_PAD_SD1_DATA7 = 124,
MX6SLL_PAD_SD2_RESET = 125,
MX6SLL_PAD_SD2_CLK = 126,
MX6SLL_PAD_SD2_CMD = 127,
MX6SLL_PAD_SD2_DATA0 = 128,
MX6SLL_PAD_SD2_DATA1 = 129,
MX6SLL_PAD_SD2_DATA2 = 130,
MX6SLL_PAD_SD2_DATA3 = 131,
MX6SLL_PAD_SD2_DATA4 = 132,
MX6SLL_PAD_SD2_DATA5 = 133,
MX6SLL_PAD_SD2_DATA6 = 134,
MX6SLL_PAD_SD2_DATA7 = 135,
MX6SLL_PAD_SD3_CLK = 136,
MX6SLL_PAD_SD3_CMD = 137,
MX6SLL_PAD_SD3_DATA0 = 138,
MX6SLL_PAD_SD3_DATA1 = 139,
MX6SLL_PAD_SD3_DATA2 = 140,
MX6SLL_PAD_SD3_DATA3 = 141,
MX6SLL_PAD_GPIO4_IO20 = 142,
MX6SLL_PAD_GPIO4_IO21 = 143,
MX6SLL_PAD_GPIO4_IO19 = 144,
MX6SLL_PAD_GPIO4_IO25 = 145,
MX6SLL_PAD_GPIO4_IO18 = 146,
MX6SLL_PAD_GPIO4_IO24 = 147,
MX6SLL_PAD_GPIO4_IO23 = 148,
MX6SLL_PAD_GPIO4_IO17 = 149,
MX6SLL_PAD_GPIO4_IO22 = 150,
MX6SLL_PAD_GPIO4_IO16 = 151,
MX6SLL_PAD_GPIO4_IO26 = 152,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
};
static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
.pins = imx6sll_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
.gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
};
static const struct of_device_id imx6sll_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
{ /* sentinel */ }
};
static int imx6sll_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
}
static struct platform_driver imx6sll_pinctrl_driver = {
.driver = {
.name = "imx6sll-pinctrl",
.of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imx6sll_pinctrl_probe,
};
static int __init imx6sll_pinctrl_init(void)
{
return platform_driver_register(&imx6sll_pinctrl_driver);
}
arch_initcall(imx6sll_pinctrl_init);

19
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -788,6 +788,24 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
void __iomem *reg;
u32 padcfg0;
reg = intel_get_padcfg(pctrl, offset, PADCFG0);
if (!reg)
return -EINVAL;
padcfg0 = readl(reg);
if (padcfg0 & PADCFG0_PMODE_MASK)
return -EINVAL;
return !!(padcfg0 & PADCFG0_GPIOTXDIS);
}
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
@ -804,6 +822,7 @@ static const struct gpio_chip intel_gpio_chip = {
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get_direction = intel_gpio_get_direction,
.direction_input = intel_gpio_direction_input,
.direction_output = intel_gpio_direction_output,
.get = intel_gpio_get,

7
drivers/pinctrl/mediatek/Kconfig
View File

@ -32,6 +32,13 @@ config PINCTRL_MT8127
select PINCTRL_MTK
# For ARMv8 SoCs
config PINCTRL_MT2712
bool "MediaTek MT2712 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF

1
drivers/pinctrl/mediatek/Makefile
View File

@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o

633
drivers/pinctrl/mediatek/pinctrl-mt2712.c Normal file
View File

@ -0,0 +1,633 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
*
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt2712.h"
static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
};
static int mt2712_spec_pull_set(struct regmap *regmap,
unsigned int pin,
unsigned char align,
bool isup,
unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6),
MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7),
MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6),
MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7),
MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3),
MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4),
MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3),
MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13),
MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13),
MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13),
MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13),
MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13),
MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13),
MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13),
MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13),
MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13),
MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13),
MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13),
MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13),
MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9),
MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10),
MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13),
MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13),
MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13),
MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13),
MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11),
MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3),
MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4),
MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5),
MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6),
MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7),
MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1),
MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9),
MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10),
MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11),
MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12),
MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13),
MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14),
MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15),
MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0),
MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1),
MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1),
MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3),
MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4),
MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3),
MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4),
MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5),
MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6),
MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5),
MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6),
MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7),
MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9),
MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9),
MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10),
MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11),
MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10),
MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11),
MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12),
MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13),
MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14),
MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15)
};
static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0),
MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4),
MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6),
MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7),
MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6),
MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7),
MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3),
MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4),
MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3),
MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14),
MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14),
MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14),
MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14),
MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14),
MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14),
MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14),
MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14),
MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14),
MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14),
MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3),
MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14),
MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14),
MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9),
MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10),
MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14),
MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14),
MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14),
MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14),
MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11),
MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3),
MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4),
MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5),
MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6),
MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7),
MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1),
MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9),
MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10),
MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11),
MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12),
MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13),
MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14),
MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15),
MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0),
MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1),
MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1),
MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3),
MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4),
MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3),
MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4),
MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5),
MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6),
MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5),
MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6),
MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7),
MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9),
MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9),
MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10),
MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11),
MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10),
MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11),
MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12),
MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13),
MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14),
MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
};
static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align,
int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
ARRAY_SIZE(mt2712_ies_set), pin, align, value);
if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
ARRAY_SIZE(mt2712_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(1, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(3, 0xc10, 4, 0),
MTK_PIN_DRV_GRP(4, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(5, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(6, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(7, 0xc00, 12, 0),
MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(9, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(10, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(11, 0xc10, 0, 0),
MTK_PIN_DRV_GRP(12, 0xb60, 0, 0),
MTK_PIN_DRV_GRP(13, 0xb60, 4, 0),
MTK_PIN_DRV_GRP(14, 0xb60, 0, 0),
MTK_PIN_DRV_GRP(15, 0xb60, 4, 0),
MTK_PIN_DRV_GRP(18, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(19, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(20, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(21, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(22, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(23, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(24, 0xb40, 4, 0),
MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
MTK_PIN_DRV_GRP(26, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(27, 0xb50, 0, 0),
MTK_PIN_DRV_GRP(28, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(29, 0xb40, 12, 0),
MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
MTK_PIN_DRV_GRP(75, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(76, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(77, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(78, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(79, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(80, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(81, 0xb70, 0, 1),
MTK_PIN_DRV_GRP(82, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(83, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(84, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(85, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(86, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(87, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(88, 0xb60, 12, 1),
MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
MTK_PIN_DRV_GRP(97, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(98, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(99, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(100, 0xb70, 4, 0),
MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
MTK_PIN_DRV_GRP(135, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(136, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(137, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(138, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(139, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(140, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(141, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(142, 0xb40, 0, 1),
MTK_PIN_DRV_GRP(143, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(144, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(145, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(146, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(147, 0xba0, 12, 0),
MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0),
MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0),
MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0),
MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0),
MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0),
MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0),
MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0),
MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0),
MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0),
MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0),
MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0),
MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0),
MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0),
MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0),
MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0),
MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0),
MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0),
MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0),
MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0),
MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0),
MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0),
MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0),
MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0),
MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0),
MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0),
MTK_PIN_DRV_GRP(200, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(201, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(202, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(203, 0xc00, 0, 0),
MTK_PIN_DRV_GRP(204, 0xc00, 4, 0),
MTK_PIN_DRV_GRP(205, 0xc00, 4, 0),
MTK_PIN_DRV_GRP(206, 0xc00, 4, 0),
MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
};
static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
.pins = mtk_pins_mt2712,
.npins = ARRAY_SIZE(mtk_pins_mt2712),
.grp_desc = mt2712_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
.pin_drv_grp = mt2712_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
.spec_pull_set = mt2712_spec_pull_set,
.spec_ies_smt_set = mt2712_ies_smt_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0100,
.pullsel_offset = 0x0200,
.dout_offset = 0x0300,
.din_offset = 0x0400,
.pinmux_offset = 0x0500,
.type1_start = 210,
.type1_end = 210,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.eint_offsets = {
.name = "mt2712_eint",
.stat = 0x000,
.ack = 0x040,
.mask = 0x080,
.mask_set = 0x0c0,
.mask_clr = 0x100,
.sens = 0x140,
.sens_set = 0x180,
.sens_clr = 0x1c0,
.soft = 0x200,
.soft_set = 0x240,
.soft_clr = 0x280,
.pol = 0x300,
.pol_set = 0x340,
.pol_clr = 0x380,
.dom_en = 0x400,
.dbnc_ctrl = 0x500,
.dbnc_set = 0x600,
.dbnc_clr = 0x700,
.port_mask = 0xf,
.ports = 8,
},
.ap_num = 229,
.db_cnt = 40,
};
static int mt2712_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
}
static const struct of_device_id mt2712_pctrl_match[] = {
{
.compatible = "mediatek,mt2712-pinctrl",
},
{ }
};
MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt2712_pinctrl_probe,
.driver = {
.name = "mediatek-mt2712-pinctrl",
.of_match_table = mt2712_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);

12
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
View File

@ -293,7 +293,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
unsigned int pin, bool enable, bool isup, unsigned int arg)
{
unsigned int bit;
unsigned int reg_pullen, reg_pullsel;
unsigned int reg_pullen, reg_pullsel, r1r0;
int ret;
/* Some pins' pull setting are very different,
@ -301,8 +301,12 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
* resistor bit, so we need this special handle.
*/
if (pctl->devdata->spec_pull_set) {
/* For special pins, bias-disable is set by R1R0,
* the parameter should be "MTK_PUPD_SET_R1R0_00".
*/
r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
pin, pctl->devdata->port_align, isup, arg);
pin, pctl->devdata->port_align, isup, r1r0);
if (!ret)
return 0;
}
@ -501,7 +505,7 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
int num_pins, num_funcs, maps_per_pin;
unsigned long *configs;
unsigned int num_configs;
bool has_config = 0;
bool has_config = false;
int i, err;
unsigned reserve = 0;
struct mtk_pinctrl_group *grp;
@ -520,7 +524,7 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
return err;
if (num_configs)
has_config = 1;
has_config = true;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;

840
drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
View File

File diff suppressed because it is too large Load Diff

1757
drivers/pinctrl/mediatek/pinctrl-mtk-mt2712.h Normal file
View File

File diff suppressed because it is too large Load Diff

123
drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
View File

@ -6,74 +6,64 @@
#include "pinctrl-mtk-common.h"
static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_PIN(
PINCTRL_PIN(0, "INT"),
MTK_PIN(PINCTRL_PIN(0, "INT"),
"N2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "INT")
),
MTK_PIN(
PINCTRL_PIN(1, "SRCVOLTEN"),
MTK_PIN(PINCTRL_PIN(1, "SRCVOLTEN"),
"M4", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "SRCVOLTEN"),
MTK_FUNCTION(6, "TEST_CK1")
),
MTK_PIN(
PINCTRL_PIN(2, "SRCLKEN_PERI"),
MTK_PIN(PINCTRL_PIN(2, "SRCLKEN_PERI"),
"M2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "SRCLKEN_PERI"),
MTK_FUNCTION(6, "TEST_CK2")
),
MTK_PIN(
PINCTRL_PIN(3, "RTC_32K1V8"),
MTK_PIN(PINCTRL_PIN(3, "RTC_32K1V8"),
"K3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "RTC_32K1V8"),
MTK_FUNCTION(6, "TEST_CK3")
),
MTK_PIN(
PINCTRL_PIN(4, "WRAP_EVENT"),
MTK_PIN(PINCTRL_PIN(4, "WRAP_EVENT"),
"J2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "WRAP_EVENT")
),
MTK_PIN(
PINCTRL_PIN(5, "SPI_CLK"),
MTK_PIN(PINCTRL_PIN(5, "SPI_CLK"),
"L4", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "SPI_CLK")
),
MTK_PIN(
PINCTRL_PIN(6, "SPI_CSN"),
MTK_PIN(PINCTRL_PIN(6, "SPI_CSN"),
"J3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO6"),
MTK_FUNCTION(1, "SPI_CSN")
),
MTK_PIN(
PINCTRL_PIN(7, "SPI_MOSI"),
MTK_PIN(PINCTRL_PIN(7, "SPI_MOSI"),
"J1", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "SPI_MOSI")
),
MTK_PIN(
PINCTRL_PIN(8, "SPI_MISO"),
MTK_PIN(PINCTRL_PIN(8, "SPI_MISO"),
"L3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO8"),
MTK_FUNCTION(1, "SPI_MISO")
),
MTK_PIN(
PINCTRL_PIN(9, "AUD_CLK_MOSI"),
MTK_PIN(PINCTRL_PIN(9, "AUD_CLK_MOSI"),
"H2", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO9"),
@ -81,8 +71,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN0"),
MTK_FUNCTION(7, "TEST_OUT0")
),
MTK_PIN(
PINCTRL_PIN(10, "AUD_DAT_MISO"),
MTK_PIN(PINCTRL_PIN(10, "AUD_DAT_MISO"),
"H3", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO10"),
@ -90,8 +79,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN1"),
MTK_FUNCTION(7, "TEST_OUT1")
),
MTK_PIN(
PINCTRL_PIN(11, "AUD_DAT_MOSI"),
MTK_PIN(PINCTRL_PIN(11, "AUD_DAT_MOSI"),
"H1", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO11"),
@ -99,8 +87,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN2"),
MTK_FUNCTION(7, "TEST_OUT2")
),
MTK_PIN(
PINCTRL_PIN(12, "COL0"),
MTK_PIN(PINCTRL_PIN(12, "COL0"),
"F3", "mt6397",
MTK_EINT_FUNCTION(2, 10),
MTK_FUNCTION(0, "GPIO12"),
@ -110,8 +97,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN3"),
MTK_FUNCTION(7, "TEST_OUT3")
),
MTK_PIN(
PINCTRL_PIN(13, "COL1"),
MTK_PIN(PINCTRL_PIN(13, "COL1"),
"G8", "mt6397",
MTK_EINT_FUNCTION(2, 11),
MTK_FUNCTION(0, "GPIO13"),
@ -121,8 +107,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN4"),
MTK_FUNCTION(7, "TEST_OUT4")
),
MTK_PIN(
PINCTRL_PIN(14, "COL2"),
MTK_PIN(PINCTRL_PIN(14, "COL2"),
"H4", "mt6397",
MTK_EINT_FUNCTION(2, 12),
MTK_FUNCTION(0, "GPIO14"),
@ -132,8 +117,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN5"),
MTK_FUNCTION(7, "TEST_OUT5")
),
MTK_PIN(
PINCTRL_PIN(15, "COL3"),
MTK_PIN(PINCTRL_PIN(15, "COL3"),
"G2", "mt6397",
MTK_EINT_FUNCTION(2, 13),
MTK_FUNCTION(0, "GPIO15"),
@ -143,8 +127,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN6"),
MTK_FUNCTION(7, "TEST_OUT6")
),
MTK_PIN(
PINCTRL_PIN(16, "COL4"),
MTK_PIN(PINCTRL_PIN(16, "COL4"),
"F2", "mt6397",
MTK_EINT_FUNCTION(2, 14),
MTK_FUNCTION(0, "GPIO16"),
@ -154,8 +137,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN7"),
MTK_FUNCTION(7, "TEST_OUT7")
),
MTK_PIN(
PINCTRL_PIN(17, "COL5"),
MTK_PIN(PINCTRL_PIN(17, "COL5"),
"G7", "mt6397",
MTK_EINT_FUNCTION(2, 15),
MTK_FUNCTION(0, "GPIO17"),
@ -165,8 +147,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN8"),
MTK_FUNCTION(7, "TEST_OUT8")
),
MTK_PIN(
PINCTRL_PIN(18, "COL6"),
MTK_PIN(PINCTRL_PIN(18, "COL6"),
"J6", "mt6397",
MTK_EINT_FUNCTION(2, 16),
MTK_FUNCTION(0, "GPIO18"),
@ -178,8 +159,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN9"),
MTK_FUNCTION(7, "TEST_OUT9")
),
MTK_PIN(
PINCTRL_PIN(19, "COL7"),
MTK_PIN(PINCTRL_PIN(19, "COL7"),
"J5", "mt6397",
MTK_EINT_FUNCTION(2, 17),
MTK_FUNCTION(0, "GPIO19"),
@ -191,8 +171,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN10"),
MTK_FUNCTION(7, "TEST_OUT10")
),
MTK_PIN(
PINCTRL_PIN(20, "ROW0"),
MTK_PIN(PINCTRL_PIN(20, "ROW0"),
"L7", "mt6397",
MTK_EINT_FUNCTION(2, 18),
MTK_FUNCTION(0, "GPIO20"),
@ -202,8 +181,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN11"),
MTK_FUNCTION(7, "TEST_OUT11")
),
MTK_PIN(
PINCTRL_PIN(21, "ROW1"),
MTK_PIN(PINCTRL_PIN(21, "ROW1"),
"P1", "mt6397",
MTK_EINT_FUNCTION(2, 19),
MTK_FUNCTION(0, "GPIO21"),
@ -214,8 +192,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN12"),
MTK_FUNCTION(7, "TEST_OUT12")
),
MTK_PIN(
PINCTRL_PIN(22, "ROW2"),
MTK_PIN(PINCTRL_PIN(22, "ROW2"),
"J8", "mt6397",
MTK_EINT_FUNCTION(2, 20),
MTK_FUNCTION(0, "GPIO22"),
@ -225,8 +202,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN13"),
MTK_FUNCTION(7, "TEST_OUT13")
),
MTK_PIN(
PINCTRL_PIN(23, "ROW3"),
MTK_PIN(PINCTRL_PIN(23, "ROW3"),
"J7", "mt6397",
MTK_EINT_FUNCTION(2, 21),
MTK_FUNCTION(0, "GPIO23"),
@ -236,8 +212,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN14"),
MTK_FUNCTION(7, "TEST_OUT14")
),
MTK_PIN(
PINCTRL_PIN(24, "ROW4"),
MTK_PIN(PINCTRL_PIN(24, "ROW4"),
"L5", "mt6397",
MTK_EINT_FUNCTION(2, 22),
MTK_FUNCTION(0, "GPIO24"),
@ -247,8 +222,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN15"),
MTK_FUNCTION(7, "TEST_OUT15")
),
MTK_PIN(
PINCTRL_PIN(25, "ROW5"),
MTK_PIN(PINCTRL_PIN(25, "ROW5"),
"N6", "mt6397",
MTK_EINT_FUNCTION(2, 23),
MTK_FUNCTION(0, "GPIO25"),
@ -258,8 +232,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN16"),
MTK_FUNCTION(7, "TEST_OUT16")
),
MTK_PIN(
PINCTRL_PIN(26, "ROW6"),
MTK_PIN(PINCTRL_PIN(26, "ROW6"),
"L6", "mt6397",
MTK_EINT_FUNCTION(2, 24),
MTK_FUNCTION(0, "GPIO26"),
@ -271,8 +244,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN17"),
MTK_FUNCTION(7, "TEST_OUT17")
),
MTK_PIN(
PINCTRL_PIN(27, "ROW7"),
MTK_PIN(PINCTRL_PIN(27, "ROW7"),
"P2", "mt6397",
MTK_EINT_FUNCTION(2, 3),
MTK_FUNCTION(0, "GPIO27"),
@ -284,8 +256,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN18"),
MTK_FUNCTION(7, "TEST_OUT18")
),
MTK_PIN(
PINCTRL_PIN(28, "PWM1(VMSEL1)"),
MTK_PIN(PINCTRL_PIN(28, "PWM1(VMSEL1)"),
"J4", "mt6397",
MTK_EINT_FUNCTION(2, 4),
MTK_FUNCTION(0, "GPIO28"),
@ -296,8 +267,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN19"),
MTK_FUNCTION(7, "TEST_OUT19")
),
MTK_PIN(
PINCTRL_PIN(29, "PWM2(VMSEL2)"),
MTK_PIN(PINCTRL_PIN(29, "PWM2(VMSEL2)"),
"N5", "mt6397",
MTK_EINT_FUNCTION(2, 5),
MTK_FUNCTION(0, "GPIO29"),
@ -308,8 +278,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN20"),
MTK_FUNCTION(7, "TEST_OUT20")
),
MTK_PIN(
PINCTRL_PIN(30, "PWM3(PWM)"),
MTK_PIN(PINCTRL_PIN(30, "PWM3(PWM)"),
"R3", "mt6397",
MTK_EINT_FUNCTION(2, 6),
MTK_FUNCTION(0, "GPIO30"),
@ -321,8 +290,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN21"),
MTK_FUNCTION(7, "TEST_OUT21")
),
MTK_PIN(
PINCTRL_PIN(31, "SCL0"),
MTK_PIN(PINCTRL_PIN(31, "SCL0"),
"N1", "mt6397",
MTK_EINT_FUNCTION(2, 7),
MTK_FUNCTION(0, "GPIO31"),
@ -332,8 +300,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN22"),
MTK_FUNCTION(7, "TEST_OUT22")
),
MTK_PIN(
PINCTRL_PIN(32, "SDA0"),
MTK_PIN(PINCTRL_PIN(32, "SDA0"),
"N3", "mt6397",
MTK_EINT_FUNCTION(2, 8),
MTK_FUNCTION(0, "GPIO32"),
@ -342,8 +309,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN23"),
MTK_FUNCTION(7, "TEST_OUT23")
),
MTK_PIN(
PINCTRL_PIN(33, "SCL1"),
MTK_PIN(PINCTRL_PIN(33, "SCL1"),
"T1", "mt6397",
MTK_EINT_FUNCTION(2, 9),
MTK_FUNCTION(0, "GPIO33"),
@ -353,8 +319,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN24"),
MTK_FUNCTION(7, "TEST_OUT24")
),
MTK_PIN(
PINCTRL_PIN(34, "SDA1"),
MTK_PIN(PINCTRL_PIN(34, "SDA1"),
"T2", "mt6397",
MTK_EINT_FUNCTION(2, 0),
MTK_FUNCTION(0, "GPIO34"),
@ -363,8 +328,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN25"),
MTK_FUNCTION(7, "TEST_OUT25")
),
MTK_PIN(
PINCTRL_PIN(35, "SCL2"),
MTK_PIN(PINCTRL_PIN(35, "SCL2"),
"T3", "mt6397",
MTK_EINT_FUNCTION(2, 1),
MTK_FUNCTION(0, "GPIO35"),
@ -374,8 +338,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN26"),
MTK_FUNCTION(7, "TEST_OUT26")
),
MTK_PIN(
PINCTRL_PIN(36, "SDA2"),
MTK_PIN(PINCTRL_PIN(36, "SDA2"),
"U2", "mt6397",
MTK_EINT_FUNCTION(2, 2),
MTK_FUNCTION(0, "GPIO36"),
@ -384,8 +347,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN27"),
MTK_FUNCTION(7, "TEST_OUT27")
),
MTK_PIN(
PINCTRL_PIN(37, "HDMISD"),
MTK_PIN(PINCTRL_PIN(37, "HDMISD"),
"H6", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO37"),
@ -393,8 +355,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN28"),
MTK_FUNCTION(7, "TEST_OUT28")
),
MTK_PIN(
PINCTRL_PIN(38, "HDMISCK"),
MTK_PIN(PINCTRL_PIN(38, "HDMISCK"),
"H5", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO38"),
@ -402,8 +363,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN29"),
MTK_FUNCTION(7, "TEST_OUT29")
),
MTK_PIN(
PINCTRL_PIN(39, "HTPLG"),
MTK_PIN(PINCTRL_PIN(39, "HTPLG"),
"H7", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO39"),
@ -411,8 +371,7 @@ static const struct mtk_desc_pin mtk_pins_mt6397[] = {
MTK_FUNCTION(6, "TEST_IN30"),
MTK_FUNCTION(7, "TEST_OUT30")
),
MTK_PIN(
PINCTRL_PIN(40, "CEC"),
MTK_PIN(PINCTRL_PIN(40, "CEC"),
"J9", "mt6397",
MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
MTK_FUNCTION(0, "GPIO40"),

429
drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
View File

File diff suppressed because it is too large Load Diff

609
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
View File

File diff suppressed because it is too large Load Diff

405
drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
View File

File diff suppressed because it is too large Load Diff

20
drivers/pinctrl/meson/pinctrl-meson8b.c
View File

@ -884,20 +884,24 @@ static struct meson_pmx_func meson8b_aobus_functions[] = {
};
static struct meson_bank meson8b_cbus_banks[] = {
/* name first last irq pullen pull dir out in */
BANK("X", GPIOX_0, GPIOX_21, 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("Y", GPIOY_0, GPIOY_14, 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
BANK("DV", GPIODV_9, GPIODV_29, 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
/* name first last irq pullen pull dir out in */
BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16),
BANK("Y0..1", GPIOY_0, GPIOY_1, 80, 81, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
BANK("Y3", GPIOY_3, GPIOY_3, 83, 83, 3, 3, 3, 3, 3, 3, 4, 3, 5, 3),
BANK("Y6..14", GPIOY_6, GPIOY_14, 86, 94, 3, 6, 3, 6, 3, 6, 4, 6, 5, 6),
BANK("DV9", GPIODV_9, GPIODV_9, 59, 59, 0, 9, 0, 9, 7, 9, 8, 9, 9, 9),
BANK("DV24..29", GPIODV_24, GPIODV_29, 74, 79, 0, 24, 0, 24, 7, 24, 8, 24, 9, 24),
BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
/*
* The following bank is not mentionned in the public datasheet
* There is no information whether it can be used with the gpio
* interrupt controller
*/
BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
};
static struct meson_bank meson8b_aobus_banks[] = {

12
drivers/pinctrl/nomadik/Kconfig
View File

@ -11,14 +11,6 @@ config PINCTRL_AB8500
bool "AB8500 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500
config PINCTRL_AB8540
bool "AB8540 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500
config PINCTRL_AB9540
bool "AB9540 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500
config PINCTRL_AB8505
bool "AB8505 pin controller driver"
depends on PINCTRL_ABX500 && ARCH_U8500
@ -44,8 +36,4 @@ config PINCTRL_DB8500
bool "DB8500 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_U8500
config PINCTRL_DB8540
bool "DB8540 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_U8500
endif

3
drivers/pinctrl/nomadik/Makefile
View File

@ -2,10 +2,7 @@
# Nomadik family pin control drivers
obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o

408
drivers/pinctrl/nomadik/pinctrl-ab8540.c
View File

@ -1,408 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2012
*
* Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/mfd/abx500/ab8500.h>
#include "pinctrl-abx500.h"
/* All the pins that can be used for GPIO and some other functions */
#define ABX500_GPIO(offset) (offset)
#define AB8540_PIN_J16 ABX500_GPIO(1)
#define AB8540_PIN_D17 ABX500_GPIO(2)
#define AB8540_PIN_C12 ABX500_GPIO(3)
#define AB8540_PIN_G12 ABX500_GPIO(4)
/* hole */
#define AB8540_PIN_D16 ABX500_GPIO(14)
#define AB8540_PIN_F15 ABX500_GPIO(15)
#define AB8540_PIN_J8 ABX500_GPIO(16)
#define AB8540_PIN_K16 ABX500_GPIO(17)
#define AB8540_PIN_G15 ABX500_GPIO(18)
#define AB8540_PIN_F17 ABX500_GPIO(19)
#define AB8540_PIN_E17 ABX500_GPIO(20)
/* hole */
#define AB8540_PIN_AA16 ABX500_GPIO(27)
#define AB8540_PIN_W18 ABX500_GPIO(28)
#define AB8540_PIN_Y15 ABX500_GPIO(29)
#define AB8540_PIN_W16 ABX500_GPIO(30)
#define AB8540_PIN_V15 ABX500_GPIO(31)
#define AB8540_PIN_W17 ABX500_GPIO(32)
/* hole */
#define AB8540_PIN_D12 ABX500_GPIO(42)
#define AB8540_PIN_P4 ABX500_GPIO(43)
#define AB8540_PIN_AB1 ABX500_GPIO(44)
#define AB8540_PIN_K7 ABX500_GPIO(45)
#define AB8540_PIN_L7 ABX500_GPIO(46)
#define AB8540_PIN_G10 ABX500_GPIO(47)
#define AB8540_PIN_K12 ABX500_GPIO(48)
/* hole */
#define AB8540_PIN_N8 ABX500_GPIO(51)
#define AB8540_PIN_P12 ABX500_GPIO(52)
#define AB8540_PIN_K8 ABX500_GPIO(53)
#define AB8540_PIN_J11 ABX500_GPIO(54)
#define AB8540_PIN_AC2 ABX500_GPIO(55)
#define AB8540_PIN_AB2 ABX500_GPIO(56)
/* indicates the highest GPIO number */
#define AB8540_GPIO_MAX_NUMBER 56
/*
* The names of the pins are denoted by GPIO number and ball name, even
* though they can be used for other things than GPIO, this is the first
* column in the table of the data sheet and often used on schematics and
* such.
*/
static const struct pinctrl_pin_desc ab8540_pins[] = {
PINCTRL_PIN(AB8540_PIN_J16, "GPIO1_J16"),
PINCTRL_PIN(AB8540_PIN_D17, "GPIO2_D17"),
PINCTRL_PIN(AB8540_PIN_C12, "GPIO3_C12"),
PINCTRL_PIN(AB8540_PIN_G12, "GPIO4_G12"),
/* hole */
PINCTRL_PIN(AB8540_PIN_D16, "GPIO14_D16"),
PINCTRL_PIN(AB8540_PIN_F15, "GPIO15_F15"),
PINCTRL_PIN(AB8540_PIN_J8, "GPIO16_J8"),
PINCTRL_PIN(AB8540_PIN_K16, "GPIO17_K16"),
PINCTRL_PIN(AB8540_PIN_G15, "GPIO18_G15"),
PINCTRL_PIN(AB8540_PIN_F17, "GPIO19_F17"),
PINCTRL_PIN(AB8540_PIN_E17, "GPIO20_E17"),
/* hole */
PINCTRL_PIN(AB8540_PIN_AA16, "GPIO27_AA16"),
PINCTRL_PIN(AB8540_PIN_W18, "GPIO28_W18"),
PINCTRL_PIN(AB8540_PIN_Y15, "GPIO29_Y15"),
PINCTRL_PIN(AB8540_PIN_W16, "GPIO30_W16"),
PINCTRL_PIN(AB8540_PIN_V15, "GPIO31_V15"),
PINCTRL_PIN(AB8540_PIN_W17, "GPIO32_W17"),
/* hole */
PINCTRL_PIN(AB8540_PIN_D12, "GPIO42_D12"),
PINCTRL_PIN(AB8540_PIN_P4, "GPIO43_P4"),
PINCTRL_PIN(AB8540_PIN_AB1, "GPIO44_AB1"),
PINCTRL_PIN(AB8540_PIN_K7, "GPIO45_K7"),
PINCTRL_PIN(AB8540_PIN_L7, "GPIO46_L7"),
PINCTRL_PIN(AB8540_PIN_G10, "GPIO47_G10"),
PINCTRL_PIN(AB8540_PIN_K12, "GPIO48_K12"),
/* hole */
PINCTRL_PIN(AB8540_PIN_N8, "GPIO51_N8"),
PINCTRL_PIN(AB8540_PIN_P12, "GPIO52_P12"),
PINCTRL_PIN(AB8540_PIN_K8, "GPIO53_K8"),
PINCTRL_PIN(AB8540_PIN_J11, "GPIO54_J11"),
PINCTRL_PIN(AB8540_PIN_AC2, "GPIO55_AC2"),
PINCTRL_PIN(AB8540_PIN_AB2, "GPIO56_AB2"),
};
/*
* Maps local GPIO offsets to local pin numbers
*/
static const struct abx500_pinrange ab8540_pinranges[] = {
ABX500_PINRANGE(1, 4, ABX500_ALT_A),
ABX500_PINRANGE(14, 7, ABX500_ALT_A),
ABX500_PINRANGE(27, 6, ABX500_ALT_A),
ABX500_PINRANGE(42, 7, ABX500_ALT_A),
ABX500_PINRANGE(51, 6, ABX500_ALT_A),
};
/*
* Read the pin group names like this:
* sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
*
* The groups are arranged as sets per altfunction column, so we can
* mux in one group at a time by selecting the same altfunction for them
* all. When functions require pins on different altfunctions, you need
* to combine several groups.
*/
/* default column */
static const unsigned sysclkreq2_d_1_pins[] = { AB8540_PIN_J16 };
static const unsigned sysclkreq3_d_1_pins[] = { AB8540_PIN_D17 };
static const unsigned sysclkreq4_d_1_pins[] = { AB8540_PIN_C12 };
static const unsigned sysclkreq6_d_1_pins[] = { AB8540_PIN_G12 };
static const unsigned pwmout1_d_1_pins[] = { AB8540_PIN_D16 };
static const unsigned pwmout2_d_1_pins[] = { AB8540_PIN_F15 };
static const unsigned pwmout3_d_1_pins[] = { AB8540_PIN_J8 };
/* audio data interface 1*/
static const unsigned adi1_d_1_pins[] = { AB8540_PIN_K16, AB8540_PIN_G15,
AB8540_PIN_F17, AB8540_PIN_E17 };
/* Digital microphone 1 and 2 */
static const unsigned dmic12_d_1_pins[] = { AB8540_PIN_AA16, AB8540_PIN_W18 };
/* Digital microphone 3 and 4 */
static const unsigned dmic34_d_1_pins[] = { AB8540_PIN_Y15, AB8540_PIN_W16 };
/* Digital microphone 5 and 6 */
static const unsigned dmic56_d_1_pins[] = { AB8540_PIN_V15, AB8540_PIN_W17 };
static const unsigned sysclkreq5_d_1_pins[] = { AB8540_PIN_D12 };
static const unsigned batremn_d_1_pins[] = { AB8540_PIN_P4 };
static const unsigned service_d_1_pins[] = { AB8540_PIN_AB1 };
static const unsigned pwrctrl0_d_1_pins[] = { AB8540_PIN_K7 };
static const unsigned pwrctrl1_d_1_pins[] = { AB8540_PIN_L7 };
static const unsigned pwmextvibra1_d_1_pins[] = { AB8540_PIN_G10 };
static const unsigned pwmextvibra2_d_1_pins[] = { AB8540_PIN_K12 };
static const unsigned gpio1_vbat_d_1_pins[] = { AB8540_PIN_N8 };
static const unsigned gpio2_vbat_d_1_pins[] = { AB8540_PIN_P12 };
static const unsigned gpio3_vbat_d_1_pins[] = { AB8540_PIN_K8 };
static const unsigned gpio4_vbat_d_1_pins[] = { AB8540_PIN_J11 };
static const unsigned pdmclkdat_d_1_pins[] = { AB8540_PIN_AC2, AB8540_PIN_AB2 };
/* Altfunction A column */
static const unsigned gpio1_a_1_pins[] = { AB8540_PIN_J16 };
static const unsigned gpio2_a_1_pins[] = { AB8540_PIN_D17 };
static const unsigned gpio3_a_1_pins[] = { AB8540_PIN_C12 };
static const unsigned gpio4_a_1_pins[] = { AB8540_PIN_G12 };
static const unsigned gpio14_a_1_pins[] = { AB8540_PIN_D16 };
static const unsigned gpio15_a_1_pins[] = { AB8540_PIN_F15 };
static const unsigned gpio16_a_1_pins[] = { AB8540_PIN_J8 };
static const unsigned gpio17_a_1_pins[] = { AB8540_PIN_K16 };
static const unsigned gpio18_a_1_pins[] = { AB8540_PIN_G15 };
static const unsigned gpio19_a_1_pins[] = { AB8540_PIN_F17 };
static const unsigned gpio20_a_1_pins[] = { AB8540_PIN_E17 };
static const unsigned gpio27_a_1_pins[] = { AB8540_PIN_AA16 };
static const unsigned gpio28_a_1_pins[] = { AB8540_PIN_W18 };
static const unsigned gpio29_a_1_pins[] = { AB8540_PIN_Y15 };
static const unsigned gpio30_a_1_pins[] = { AB8540_PIN_W16 };
static const unsigned gpio31_a_1_pins[] = { AB8540_PIN_V15 };
static const unsigned gpio32_a_1_pins[] = { AB8540_PIN_W17 };
static const unsigned gpio42_a_1_pins[] = { AB8540_PIN_D12 };
static const unsigned gpio43_a_1_pins[] = { AB8540_PIN_P4 };
static const unsigned gpio44_a_1_pins[] = { AB8540_PIN_AB1 };
static const unsigned gpio45_a_1_pins[] = { AB8540_PIN_K7 };
static const unsigned gpio46_a_1_pins[] = { AB8540_PIN_L7 };
static const unsigned gpio47_a_1_pins[] = { AB8540_PIN_G10 };
static const unsigned gpio48_a_1_pins[] = { AB8540_PIN_K12 };
static const unsigned gpio51_a_1_pins[] = { AB8540_PIN_N8 };
static const unsigned gpio52_a_1_pins[] = { AB8540_PIN_P12 };
static const unsigned gpio53_a_1_pins[] = { AB8540_PIN_K8 };
static const unsigned gpio54_a_1_pins[] = { AB8540_PIN_J11 };
static const unsigned gpio55_a_1_pins[] = { AB8540_PIN_AC2 };
static const unsigned gpio56_a_1_pins[] = { AB8540_PIN_AB2 };
#define AB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
static const struct abx500_pingroup ab8540_groups[] = {
/* default column */
AB8540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pwrctrl0_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pwrctrl1_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pwmextvibra1_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pwmextvibra2_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(gpio1_vbat_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(gpio2_vbat_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(gpio3_vbat_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(gpio4_vbat_d_1, ABX500_DEFAULT),
AB8540_PIN_GROUP(pdmclkdat_d_1, ABX500_DEFAULT),
/* Altfunction A column */
AB8540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio43_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio44_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio45_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio46_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio47_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio48_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio54_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio55_a_1, ABX500_ALT_A),
AB8540_PIN_GROUP(gpio56_a_1, ABX500_ALT_A),
};
/* We use this macro to define the groups applicable to a function */
#define AB8540_FUNC_GROUPS(a, b...) \
static const char * const a##_groups[] = { b };
AB8540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
"sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1");
AB8540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
"gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1",
"gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio27_a_1",
"gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
"gpio32_a_1", "gpio42_a_1", "gpio43_a_1", "gpio44_a_1",
"gpio45_a_1", "gpio46_a_1", "gpio47_a_1", "gpio48_a_1",
"gpio51_a_1", "gpio52_a_1", "gpio53_a_1", "gpio54_a_1",
"gpio55_a_1", "gpio56_a_1");
AB8540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
AB8540_FUNC_GROUPS(adi1, "adi1_d_1");
AB8540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
AB8540_FUNC_GROUPS(batremn, "batremn_d_1");
AB8540_FUNC_GROUPS(service, "service_d_1");
AB8540_FUNC_GROUPS(pwrctrl, "pwrctrl0_d_1", "pwrctrl1_d_1");
AB8540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_d_1", "pwmextvibra2_d_1");
AB8540_FUNC_GROUPS(gpio_vbat, "gpio1_vbat_d_1", "gpio2_vbat_d_1",
"gpio3_vbat_d_1", "gpio4_vbat_d_1");
AB8540_FUNC_GROUPS(pdm, "pdmclkdat_d_1");
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
static const struct abx500_function ab8540_functions[] = {
FUNCTION(sysclkreq),
FUNCTION(gpio),
FUNCTION(pwmout),
FUNCTION(adi1),
FUNCTION(dmic),
FUNCTION(batremn),
FUNCTION(service),
FUNCTION(pwrctrl),
FUNCTION(pwmextvibra),
FUNCTION(gpio_vbat),
FUNCTION(pdm),
};
/*
* this table translates what's is in the AB8540 specification regarding the
* balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
* ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
* ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
* AB8540 only supports DEFAULT and ALTA functions, so ALTERNATFUNC
* registers is not used
*
*/
static struct
alternate_functions ab8540_alternate_functions[AB8540_GPIO_MAX_NUMBER + 1] = {
/* GPIOSEL1 - bit 4-7 reserved */
ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
/* GPIOSEL2 - bit 0-4 reserved */
ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
ALTERNATE_FUNCTIONS(10, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO10 */
ALTERNATE_FUNCTIONS(11, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO11 */
ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
ALTERNATE_FUNCTIONS(13, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO13 */
ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
/* GPIOSEL3 - bit 4-7 reserved */
ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(18, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(19, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 2 */
ALTERNATE_FUNCTIONS(20, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 3 */
ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21 */
ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22 */
ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23 */
ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24 */
/* GPIOSEL4 - bit 0-1 reserved */
ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25 */
ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
/* GPIOSEL5 - bit 0-7 reserved */
ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
ALTERNATE_FUNCTIONS(34, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO34 */
ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
ALTERNATE_FUNCTIONS(40, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO40 */
/* GPIOSEL6 - bit 0 reserved */
ALTERNATE_FUNCTIONS(41, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO41 */
ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(43, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO43, altA controlled by bit 2 */
ALTERNATE_FUNCTIONS(44, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO44, altA controlled by bit 3 */
ALTERNATE_FUNCTIONS(45, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO45, altA controlled by bit 4 */
ALTERNATE_FUNCTIONS(46, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO46, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(47, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO47, altA controlled by bit 6 */
ALTERNATE_FUNCTIONS(48, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO48, altA controlled by bit 7 */
/* GPIOSEL7 - bit 0-1 reserved */
ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
ALTERNATE_FUNCTIONS(50, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO50 */
ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(55, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO55, altA controlled by bit 6 */
ALTERNATE_FUNCTIONS(56, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO56, altA controlled by bit 7 */
};
static struct pullud ab8540_pullud = {
.first_pin = 51, /* GPIO1_VBAT */
.last_pin = 54, /* GPIO4_VBAT */
};
/*
* For AB8540 Only some GPIOs are interrupt capable:
* GPIO43 to GPIO44
* GPIO51 to GPIO54
*/
static struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = {
GPIO_IRQ_CLUSTER(43, 43, AB8540_INT_GPIO43F),
GPIO_IRQ_CLUSTER(44, 44, AB8540_INT_GPIO44F),
GPIO_IRQ_CLUSTER(51, 54, AB9540_INT_GPIO51R),
};
static struct abx500_pinctrl_soc_data ab8540_soc = {
.gpio_ranges = ab8540_pinranges,
.gpio_num_ranges = ARRAY_SIZE(ab8540_pinranges),
.pins = ab8540_pins,
.npins = ARRAY_SIZE(ab8540_pins),
.functions = ab8540_functions,
.nfunctions = ARRAY_SIZE(ab8540_functions),
.groups = ab8540_groups,
.ngroups = ARRAY_SIZE(ab8540_groups),
.alternate_functions = ab8540_alternate_functions,
.pullud = &ab8540_pullud,
.gpio_irq_cluster = ab8540_gpio_irq_cluster,
.ngpio_irq_cluster = ARRAY_SIZE(ab8540_gpio_irq_cluster),
.irq_gpio_rising_offset = AB8540_INT_GPIO43R,
.irq_gpio_falling_offset = AB8540_INT_GPIO43F,
.irq_gpio_factor = 2,
};
void
abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
{
*soc = &ab8540_soc;
}

486
drivers/pinctrl/nomadik/pinctrl-ab9540.c
View File

@ -1,486 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2012
*
* Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/mfd/abx500/ab8500.h>
#include "pinctrl-abx500.h"
/* All the pins that can be used for GPIO and some other functions */
#define ABX500_GPIO(offset) (offset)
#define AB9540_PIN_R4 ABX500_GPIO(1)
#define AB9540_PIN_V3 ABX500_GPIO(2)
#define AB9540_PIN_T4 ABX500_GPIO(3)
#define AB9540_PIN_T5 ABX500_GPIO(4)
/* hole */
#define AB9540_PIN_B18 ABX500_GPIO(10)
#define AB9540_PIN_C18 ABX500_GPIO(11)
/* hole */
#define AB9540_PIN_D18 ABX500_GPIO(13)
#define AB9540_PIN_B19 ABX500_GPIO(14)
#define AB9540_PIN_C19 ABX500_GPIO(15)
#define AB9540_PIN_D19 ABX500_GPIO(16)
#define AB9540_PIN_R3 ABX500_GPIO(17)
#define AB9540_PIN_T2 ABX500_GPIO(18)
#define AB9540_PIN_U2 ABX500_GPIO(19)
#define AB9540_PIN_V2 ABX500_GPIO(20)
#define AB9540_PIN_N17 ABX500_GPIO(21)
#define AB9540_PIN_N16 ABX500_GPIO(22)
#define AB9540_PIN_M19 ABX500_GPIO(23)
#define AB9540_PIN_T3 ABX500_GPIO(24)
#define AB9540_PIN_W2 ABX500_GPIO(25)
/* hole */
#define AB9540_PIN_H4 ABX500_GPIO(27)
#define AB9540_PIN_F1 ABX500_GPIO(28)
#define AB9540_PIN_F4 ABX500_GPIO(29)
#define AB9540_PIN_F2 ABX500_GPIO(30)
#define AB9540_PIN_E4 ABX500_GPIO(31)
#define AB9540_PIN_F3 ABX500_GPIO(32)
/* hole */
#define AB9540_PIN_J13 ABX500_GPIO(34)
/* hole */
#define AB9540_PIN_L17 ABX500_GPIO(40)
#define AB9540_PIN_L16 ABX500_GPIO(41)
#define AB9540_PIN_W3 ABX500_GPIO(42)
#define AB9540_PIN_N4 ABX500_GPIO(50)
#define AB9540_PIN_G12 ABX500_GPIO(51)
#define AB9540_PIN_E17 ABX500_GPIO(52)
#define AB9540_PIN_D11 ABX500_GPIO(53)
#define AB9540_PIN_M18 ABX500_GPIO(54)
/* indicates the highest GPIO number */
#define AB9540_GPIO_MAX_NUMBER 54
/*
* The names of the pins are denoted by GPIO number and ball name, even
* though they can be used for other things than GPIO, this is the first
* column in the table of the data sheet and often used on schematics and
* such.
*/
static const struct pinctrl_pin_desc ab9540_pins[] = {
PINCTRL_PIN(AB9540_PIN_R4, "GPIO1_R4"),
PINCTRL_PIN(AB9540_PIN_V3, "GPIO2_V3"),
PINCTRL_PIN(AB9540_PIN_T4, "GPIO3_T4"),
PINCTRL_PIN(AB9540_PIN_T5, "GPIO4_T5"),
/* hole */
PINCTRL_PIN(AB9540_PIN_B18, "GPIO10_B18"),
PINCTRL_PIN(AB9540_PIN_C18, "GPIO11_C18"),
/* hole */
PINCTRL_PIN(AB9540_PIN_D18, "GPIO13_D18"),
PINCTRL_PIN(AB9540_PIN_B19, "GPIO14_B19"),
PINCTRL_PIN(AB9540_PIN_C19, "GPIO15_C19"),
PINCTRL_PIN(AB9540_PIN_D19, "GPIO16_D19"),
PINCTRL_PIN(AB9540_PIN_R3, "GPIO17_R3"),
PINCTRL_PIN(AB9540_PIN_T2, "GPIO18_T2"),
PINCTRL_PIN(AB9540_PIN_U2, "GPIO19_U2"),
PINCTRL_PIN(AB9540_PIN_V2, "GPIO20_V2"),
PINCTRL_PIN(AB9540_PIN_N17, "GPIO21_N17"),
PINCTRL_PIN(AB9540_PIN_N16, "GPIO22_N16"),
PINCTRL_PIN(AB9540_PIN_M19, "GPIO23_M19"),
PINCTRL_PIN(AB9540_PIN_T3, "GPIO24_T3"),
PINCTRL_PIN(AB9540_PIN_W2, "GPIO25_W2"),
/* hole */
PINCTRL_PIN(AB9540_PIN_H4, "GPIO27_H4"),
PINCTRL_PIN(AB9540_PIN_F1, "GPIO28_F1"),
PINCTRL_PIN(AB9540_PIN_F4, "GPIO29_F4"),
PINCTRL_PIN(AB9540_PIN_F2, "GPIO30_F2"),
PINCTRL_PIN(AB9540_PIN_E4, "GPIO31_E4"),
PINCTRL_PIN(AB9540_PIN_F3, "GPIO32_F3"),
/* hole */
PINCTRL_PIN(AB9540_PIN_J13, "GPIO34_J13"),
/* hole */
PINCTRL_PIN(AB9540_PIN_L17, "GPIO40_L17"),
PINCTRL_PIN(AB9540_PIN_L16, "GPIO41_L16"),
PINCTRL_PIN(AB9540_PIN_W3, "GPIO42_W3"),
PINCTRL_PIN(AB9540_PIN_N4, "GPIO50_N4"),
PINCTRL_PIN(AB9540_PIN_G12, "GPIO51_G12"),
PINCTRL_PIN(AB9540_PIN_E17, "GPIO52_E17"),
PINCTRL_PIN(AB9540_PIN_D11, "GPIO53_D11"),
PINCTRL_PIN(AB9540_PIN_M18, "GPIO60_M18"),
};
/*
* Maps local GPIO offsets to local pin numbers
*/
static const struct abx500_pinrange ab9540_pinranges[] = {
ABX500_PINRANGE(1, 4, ABX500_ALT_A),
ABX500_PINRANGE(10, 2, ABX500_DEFAULT),
ABX500_PINRANGE(13, 1, ABX500_DEFAULT),
ABX500_PINRANGE(14, 12, ABX500_ALT_A),
ABX500_PINRANGE(27, 6, ABX500_ALT_A),
ABX500_PINRANGE(34, 1, ABX500_ALT_A),
ABX500_PINRANGE(40, 3, ABX500_ALT_A),
ABX500_PINRANGE(50, 1, ABX500_DEFAULT),
ABX500_PINRANGE(51, 3, ABX500_ALT_A),
ABX500_PINRANGE(54, 1, ABX500_DEFAULT),
};
/*
* Read the pin group names like this:
* sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
*
* The groups are arranged as sets per altfunction column, so we can
* mux in one group at a time by selecting the same altfunction for them
* all. When functions require pins on different altfunctions, you need
* to combine several groups.
*/
/* default column */
static const unsigned sysclkreq2_d_1_pins[] = { AB9540_PIN_R4 };
static const unsigned sysclkreq3_d_1_pins[] = { AB9540_PIN_V3 };
static const unsigned sysclkreq4_d_1_pins[] = { AB9540_PIN_T4 };
static const unsigned sysclkreq6_d_1_pins[] = { AB9540_PIN_T5 };
static const unsigned gpio10_d_1_pins[] = { AB9540_PIN_B18 };
static const unsigned gpio11_d_1_pins[] = { AB9540_PIN_C18 };
static const unsigned gpio13_d_1_pins[] = { AB9540_PIN_D18 };
static const unsigned pwmout1_d_1_pins[] = { AB9540_PIN_B19 };
static const unsigned pwmout2_d_1_pins[] = { AB9540_PIN_C19 };
static const unsigned pwmout3_d_1_pins[] = { AB9540_PIN_D19 };
/* audio data interface 1*/
static const unsigned adi1_d_1_pins[] = { AB9540_PIN_R3, AB9540_PIN_T2,
AB9540_PIN_U2, AB9540_PIN_V2 };
/* USBUICC */
static const unsigned usbuicc_d_1_pins[] = { AB9540_PIN_N17, AB9540_PIN_N16,
AB9540_PIN_M19 };
static const unsigned sysclkreq7_d_1_pins[] = { AB9540_PIN_T3 };
static const unsigned sysclkreq8_d_1_pins[] = { AB9540_PIN_W2 };
/* Digital microphone 1 and 2 */
static const unsigned dmic12_d_1_pins[] = { AB9540_PIN_H4, AB9540_PIN_F1 };
/* Digital microphone 3 and 4 */
static const unsigned dmic34_d_1_pins[] = { AB9540_PIN_F4, AB9540_PIN_F2 };
/* Digital microphone 5 and 6 */
static const unsigned dmic56_d_1_pins[] = { AB9540_PIN_E4, AB9540_PIN_F3 };
static const unsigned extcpena_d_1_pins[] = { AB9540_PIN_J13 };
/* modem SDA/SCL */
static const unsigned modsclsda_d_1_pins[] = { AB9540_PIN_L17, AB9540_PIN_L16 };
static const unsigned sysclkreq5_d_1_pins[] = { AB9540_PIN_W3 };
static const unsigned gpio50_d_1_pins[] = { AB9540_PIN_N4 };
static const unsigned batremn_d_1_pins[] = { AB9540_PIN_G12 };
static const unsigned resethw_d_1_pins[] = { AB9540_PIN_E17 };
static const unsigned service_d_1_pins[] = { AB9540_PIN_D11 };
static const unsigned gpio60_d_1_pins[] = { AB9540_PIN_M18 };
/* Altfunction A column */
static const unsigned gpio1_a_1_pins[] = { AB9540_PIN_R4 };
static const unsigned gpio2_a_1_pins[] = { AB9540_PIN_V3 };
static const unsigned gpio3_a_1_pins[] = { AB9540_PIN_T4 };
static const unsigned gpio4_a_1_pins[] = { AB9540_PIN_T5 };
static const unsigned hiqclkena_a_1_pins[] = { AB9540_PIN_B18 };
static const unsigned pdmclk_a_1_pins[] = { AB9540_PIN_C18 };
static const unsigned uartdata_a_1_pins[] = { AB9540_PIN_D18, AB9540_PIN_N4 };
static const unsigned gpio14_a_1_pins[] = { AB9540_PIN_B19 };
static const unsigned gpio15_a_1_pins[] = { AB9540_PIN_C19 };
static const unsigned gpio16_a_1_pins[] = { AB9540_PIN_D19 };
static const unsigned gpio17_a_1_pins[] = { AB9540_PIN_R3 };
static const unsigned gpio18_a_1_pins[] = { AB9540_PIN_T2 };
static const unsigned gpio19_a_1_pins[] = { AB9540_PIN_U2 };
static const unsigned gpio20_a_1_pins[] = { AB9540_PIN_V2 };
static const unsigned gpio21_a_1_pins[] = { AB9540_PIN_N17 };
static const unsigned gpio22_a_1_pins[] = { AB9540_PIN_N16 };
static const unsigned gpio23_a_1_pins[] = { AB9540_PIN_M19 };
static const unsigned gpio24_a_1_pins[] = { AB9540_PIN_T3 };
static const unsigned gpio25_a_1_pins[] = { AB9540_PIN_W2 };
static const unsigned gpio27_a_1_pins[] = { AB9540_PIN_H4 };
static const unsigned gpio28_a_1_pins[] = { AB9540_PIN_F1 };
static const unsigned gpio29_a_1_pins[] = { AB9540_PIN_F4 };
static const unsigned gpio30_a_1_pins[] = { AB9540_PIN_F2 };
static const unsigned gpio31_a_1_pins[] = { AB9540_PIN_E4 };
static const unsigned gpio32_a_1_pins[] = { AB9540_PIN_F3 };
static const unsigned gpio34_a_1_pins[] = { AB9540_PIN_J13 };
static const unsigned gpio40_a_1_pins[] = { AB9540_PIN_L17 };
static const unsigned gpio41_a_1_pins[] = { AB9540_PIN_L16 };
static const unsigned gpio42_a_1_pins[] = { AB9540_PIN_W3 };
static const unsigned gpio51_a_1_pins[] = { AB9540_PIN_G12 };
static const unsigned gpio52_a_1_pins[] = { AB9540_PIN_E17 };
static const unsigned gpio53_a_1_pins[] = { AB9540_PIN_D11 };
static const unsigned usbuiccpd_a_1_pins[] = { AB9540_PIN_M18 };
/* Altfunction B colum */
static const unsigned pdmdata_b_1_pins[] = { AB9540_PIN_B18 };
static const unsigned pwmextvibra1_b_1_pins[] = { AB9540_PIN_D18 };
static const unsigned pwmextvibra2_b_1_pins[] = { AB9540_PIN_N4 };
/* Altfunction C column */
static const unsigned usbvdat_c_1_pins[] = { AB9540_PIN_D18 };
#define AB9540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
static const struct abx500_pingroup ab9540_groups[] = {
/* default column */
AB9540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(resethw_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
AB9540_PIN_GROUP(gpio60_d_1, ABX500_DEFAULT),
/* Altfunction A column */
AB9540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(uartdata_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio21_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio22_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio23_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio24_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio25_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
AB9540_PIN_GROUP(usbuiccpd_a_1, ABX500_ALT_A),
/* Altfunction B column */
AB9540_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B),
AB9540_PIN_GROUP(pwmextvibra1_b_1, ABX500_ALT_B),
AB9540_PIN_GROUP(pwmextvibra2_b_1, ABX500_ALT_B),
/* Altfunction C column */
AB9540_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
};
/* We use this macro to define the groups applicable to a function */
#define AB9540_FUNC_GROUPS(a, b...) \
static const char * const a##_groups[] = { b };
AB9540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
"sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1",
"sysclkreq7_d_1", "sysclkreq8_d_1");
AB9540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
"gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1",
"gpio15_a_1", "gpio16_a_1", "gpio17_a_1", "gpio18_a_1",
"gpio19_a_1", "gpio20_a_1", "gpio21_a_1", "gpio22_a_1",
"gpio23_a_1", "gpio24_a_1", "gpio25_a_1", "gpio27_a_1",
"gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
"gpio32_a_1", "gpio34_a_1", "gpio40_a_1", "gpio41_a_1",
"gpio42_a_1", "gpio50_d_1", "gpio51_a_1", "gpio52_a_1",
"gpio53_a_1", "gpio60_d_1");
AB9540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
AB9540_FUNC_GROUPS(adi1, "adi1_d_1");
AB9540_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_a_1");
AB9540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
AB9540_FUNC_GROUPS(extcpena, "extcpena_d_1");
AB9540_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
AB9540_FUNC_GROUPS(batremn, "batremn_d_1");
AB9540_FUNC_GROUPS(resethw, "resethw_d_1");
AB9540_FUNC_GROUPS(service, "service_d_1");
AB9540_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1");
AB9540_FUNC_GROUPS(pdm, "pdmdata_b_1", "pdmclk_a_1");
AB9540_FUNC_GROUPS(uartdata, "uartdata_a_1");
AB9540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_b_1", "pwmextvibra2_b_1");
AB9540_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
static const struct abx500_function ab9540_functions[] = {
FUNCTION(sysclkreq),
FUNCTION(gpio),
FUNCTION(pwmout),
FUNCTION(adi1),
FUNCTION(usbuicc),
FUNCTION(dmic),
FUNCTION(extcpena),
FUNCTION(modsclsda),
FUNCTION(batremn),
FUNCTION(resethw),
FUNCTION(service),
FUNCTION(hiqclkena),
FUNCTION(pdm),
FUNCTION(uartdata),
FUNCTION(pwmextvibra),
FUNCTION(usbvdat),
};
/*
* this table translates what's is in the AB9540 specification regarding the
* balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
* ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
* ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
*
* example :
*
* ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2),
* means that pin AB9540_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
* ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
* select the mux. ALTA, ALTB and ALTC val indicates values to write in
* ALTERNATFUNC register. We need to specifies these values as SOC
* designers didn't apply the same logic on how to select mux in the
* ABx500 family.
*
* As this pins supports at least ALT_B mux, default mux is
* selected by writing 1 in GPIOSEL bit :
*
* | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
* default | 1 | 0 | 0
* alt_A | 0 | 0 | 1
* alt_B | 0 | 0 | 0
* alt_C | 0 | 1 | 0
*
* ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED),
* means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
* register is used to select the mux. As this pins doesn't support at
* least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
*
* | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1=
* default | 0 | 0 | 0
* alt_A | 1 | 0 | 0
*/
static struct
alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] = {
/* GPIOSEL1 - bits 4-7 are reserved */
ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
/* GPIOSEL2 - bits 0 and 3 are reserved */
ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
/* GPIOSEL3 - bit 1-3 reserved
* pins 17 to 20 are special case, only bit 0 is used to select
* alternate function for these 4 pins.
* bits 1 to 3 are reserved
*/
ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */
ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */
ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */
/* GPIOSEL4 - bit 1 reserved */
ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
/* GPIOSEL5 - bit 0, 2-6 are reserved */
ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */
/* GPIOSEL6 - bit 2-7 are reserved */
ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43 */
ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44 */
ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45 */
ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46 */
ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47 */
ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48 */
/*
* GPIOSEL7 - bit 0 and 6-7 are reserved
* special case with GPIO60, wich is located at offset 5 of gpiosel7
* don't know why it has been called GPIO60 in AB9540 datasheet,
* GPIO54 would be logical..., so at SOC point of view we consider
* GPIO60 = GPIO54
*/
ALTERNATE_FUNCTIONS(49, 0, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA and altB controlled by bit 1 */
ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54 = GPIO60, altA controlled by bit 5 */
};
static struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = {
GPIO_IRQ_CLUSTER(10, 13, AB8500_INT_GPIO10R),
GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R),
GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R),
GPIO_IRQ_CLUSTER(50, 54, AB9540_INT_GPIO50R),
};
static struct abx500_pinctrl_soc_data ab9540_soc = {
.gpio_ranges = ab9540_pinranges,
.gpio_num_ranges = ARRAY_SIZE(ab9540_pinranges),
.pins = ab9540_pins,
.npins = ARRAY_SIZE(ab9540_pins),
.functions = ab9540_functions,
.nfunctions = ARRAY_SIZE(ab9540_functions),
.groups = ab9540_groups,
.ngroups = ARRAY_SIZE(ab9540_groups),
.alternate_functions = ab9540alternate_functions,
.gpio_irq_cluster = ab9540_gpio_irq_cluster,
.ngpio_irq_cluster = ARRAY_SIZE(ab9540_gpio_irq_cluster),
.irq_gpio_rising_offset = AB8500_INT_GPIO6R,
.irq_gpio_falling_offset = AB8500_INT_GPIO6F,
.irq_gpio_factor = 1,
};
void
abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
{
*soc = &ab9540_soc;
}

197
drivers/pinctrl/nomadik/pinctrl-abx500.c
View File

@ -37,15 +37,6 @@
#include "../pinconf.h"
#include "../pinctrl-utils.h"
/*
* The AB9540 and AB8540 GPIO support are extended versions
* of the AB8500 GPIO support.
* The AB9540 supports an additional (7th) register so that
* more GPIO may be configured and used.
* The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
* internal pull-up and pull-down capabilities.
*/
/*
* GPIO registers offset
* Bank: 0x10
@ -56,7 +47,6 @@
#define AB8500_GPIO_SEL4_REG 0x03
#define AB8500_GPIO_SEL5_REG 0x04
#define AB8500_GPIO_SEL6_REG 0x05
#define AB9540_GPIO_SEL7_REG 0x06
#define AB8500_GPIO_DIR1_REG 0x10
#define AB8500_GPIO_DIR2_REG 0x11
@ -64,7 +54,6 @@
#define AB8500_GPIO_DIR4_REG 0x13
#define AB8500_GPIO_DIR5_REG 0x14
#define AB8500_GPIO_DIR6_REG 0x15
#define AB9540_GPIO_DIR7_REG 0x16
#define AB8500_GPIO_OUT1_REG 0x20
#define AB8500_GPIO_OUT2_REG 0x21
@ -72,7 +61,6 @@
#define AB8500_GPIO_OUT4_REG 0x23
#define AB8500_GPIO_OUT5_REG 0x24
#define AB8500_GPIO_OUT6_REG 0x25
#define AB9540_GPIO_OUT7_REG 0x26
#define AB8500_GPIO_PUD1_REG 0x30
#define AB8500_GPIO_PUD2_REG 0x31
@ -80,7 +68,6 @@
#define AB8500_GPIO_PUD4_REG 0x33
#define AB8500_GPIO_PUD5_REG 0x34
#define AB8500_GPIO_PUD6_REG 0x35
#define AB9540_GPIO_PUD7_REG 0x36
#define AB8500_GPIO_IN1_REG 0x40
#define AB8500_GPIO_IN2_REG 0x41
@ -88,14 +75,7 @@
#define AB8500_GPIO_IN4_REG 0x43
#define AB8500_GPIO_IN5_REG 0x44
#define AB8500_GPIO_IN6_REG 0x45
#define AB9540_GPIO_IN7_REG 0x46
#define AB8540_GPIO_VINSEL_REG 0x47
#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
#define AB8500_GPIO_ALTFUN_REG 0x50
#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
#define AB8540_GPIO_VINSEL_MASK 0x03
#define AB8540_GPIOX_VBAT_START 51
#define AB8540_GPIOX_VBAT_END 54
#define ABX500_GPIO_INPUT 0
#define ABX500_GPIO_OUTPUT 1
@ -192,94 +172,11 @@ static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
}
#ifdef CONFIG_DEBUG_FS
static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
enum abx500_gpio_pull_updown *pull_updown)
{
u8 pos;
u8 val;
int ret;
struct pullud *pullud;
if (!pct->soc->pullud) {
dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
__func__);
ret = -EPERM;
goto out;
}
pullud = pct->soc->pullud;
if ((offset < pullud->first_pin)
|| (offset > pullud->last_pin)) {
ret = -EINVAL;
goto out;
}
ret = abx500_get_register_interruptible(pct->dev,
AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
pos = (offset - pullud->first_pin) << 1;
*pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
out:
if (ret < 0)
dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
return ret;
}
#endif
static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
int offset, enum abx500_gpio_pull_updown val)
{
u8 pos;
int ret;
struct pullud *pullud;
if (!pct->soc->pullud) {
dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
__func__);
ret = -EPERM;
goto out;
}
pullud = pct->soc->pullud;
if ((offset < pullud->first_pin)
|| (offset > pullud->last_pin)) {
ret = -EINVAL;
goto out;
}
pos = (offset - pullud->first_pin) << 1;
ret = abx500_mask_and_set_register_interruptible(pct->dev,
AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
out:
if (ret < 0)
dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
return ret;
}
static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
{
struct abx500_pinctrl *pct = gpiochip_get_data(chip);
struct pullud *pullud = pct->soc->pullud;
return (pullud &&
gpio >= pullud->first_pin &&
gpio <= pullud->last_pin);
}
static int abx500_gpio_direction_output(struct gpio_chip *chip,
unsigned offset,
int val)
{
struct abx500_pinctrl *pct = gpiochip_get_data(chip);
unsigned gpio;
int ret;
/* set direction as output */
@ -295,16 +192,7 @@ static int abx500_gpio_direction_output(struct gpio_chip *chip,
AB8500_GPIO_PUD1_REG,
offset,
ABX500_GPIO_PULL_NONE);
if (ret < 0)
goto out;
/* if supported, disable both pull down and pull up */
gpio = offset + 1;
if (abx500_pullud_supported(chip, gpio)) {
ret = abx500_set_pull_updown(pct,
gpio,
ABX500_GPIO_PULL_NONE);
}
out:
if (ret < 0) {
dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
@ -570,7 +458,6 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
int mode = -1;
bool is_out;
bool pd;
enum abx500_gpio_pull_updown pud = 0;
int ret;
const char *modes[] = {
@ -597,20 +484,12 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
is_out ? "out" : "in ");
if (!is_out) {
if (abx500_pullud_supported(chip, offset)) {
ret = abx500_get_pull_updown(pct, offset, &pud);
if (ret < 0)
goto out;
ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
gpio_offset, &pd);
if (ret < 0)
goto out;
seq_printf(s, " %-9s", pull_up_down[pud]);
} else {
ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
gpio_offset, &pd);
if (ret < 0)
goto out;
seq_printf(s, " %-9s", pull_up_down[pd]);
}
seq_printf(s, " %-9s", pull_up_down[pd]);
} else
seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
@ -994,23 +873,11 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
ret = abx500_gpio_direction_input(chip, offset);
if (ret < 0)
goto out;
/*
* Some chips only support pull down, while some
* actually support both pull up and pull down. Such
* chips have a "pullud" range specified for the pins
* that support both features. If the pin is not
* within that range, we fall back to the old bit set
* that only support pull down.
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
ABX500_GPIO_PULL_NONE);
else
/* Chip only supports pull down */
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_PUD1_REG, offset,
ABX500_GPIO_PULL_NONE);
/* Chip only supports pull down */
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_PUD1_REG, offset,
ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
@ -1020,25 +887,13 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
/*
* if argument = 1 set the pull down
* else clear the pull down
* Some chips only support pull down, while some
* actually support both pull up and pull down. Such
* chips have a "pullud" range specified for the pins
* that support both features. If the pin is not
* within that range, we fall back to the old bit set
* that only support pull down.
* Chip only supports pull down
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
argument ? ABX500_GPIO_PULL_DOWN :
ABX500_GPIO_PULL_NONE);
else
/* Chip only supports pull down */
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_PUD1_REG,
offset,
argument ? ABX500_GPIO_PULL_DOWN :
ABX500_GPIO_PULL_NONE);
ret = abx500_gpio_set_bits(chip,
AB8500_GPIO_PUD1_REG,
offset,
argument ? ABX500_GPIO_PULL_DOWN :
ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_UP:
@ -1050,18 +905,6 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
* else clear the pull up
*/
ret = abx500_gpio_direction_input(chip, offset);
/*
* Some chips only support pull down, while some
* actually support both pull up and pull down. Such
* chips have a "pullud" range specified for the pins
* that support both features. If the pin is not
* within that range, do nothing
*/
if (abx500_pullud_supported(chip, pin))
ret = abx500_set_pull_updown(pct,
pin,
argument ? ABX500_GPIO_PULL_UP :
ABX500_GPIO_PULL_NONE);
break;
case PIN_CONFIG_OUTPUT:
@ -1136,8 +979,6 @@ static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
static const struct of_device_id abx500_gpio_match[] = {
{ .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
{ .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
{ .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
{ .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
{ }
};
@ -1177,12 +1018,6 @@ static int abx500_gpio_probe(struct platform_device *pdev)
case PINCTRL_AB8500:
abx500_pinctrl_ab8500_init(&pct->soc);
break;
case PINCTRL_AB8540:
abx500_pinctrl_ab8540_init(&pct->soc);
break;
case PINCTRL_AB9540:
abx500_pinctrl_ab9540_init(&pct->soc);
break;
case PINCTRL_AB8505:
abx500_pinctrl_ab8505_init(&pct->soc);
break;

44
drivers/pinctrl/nomadik/pinctrl-abx500.h
View File

@ -4,9 +4,7 @@
/* Package definitions */
#define PINCTRL_AB8500 0
#define PINCTRL_AB8540 1
#define PINCTRL_AB9540 2
#define PINCTRL_AB8505 3
#define PINCTRL_AB8505 1
/* pins alternate function */
enum abx500_pin_func {
@ -96,17 +94,6 @@ struct alternate_functions {
u8 altc_val;
};
/**
* struct pullud - specific pull up/down feature
* @first_pin: The pin number of the first pins which support
* specific pull up/down
* @last_pin: The pin number of the last pins
*/
struct pullud {
unsigned first_pin;
unsigned last_pin;
};
#define GPIO_IRQ_CLUSTER(a, b, c) \
{ \
.start = a, \
@ -162,8 +149,6 @@ struct abx500_pinrange {
* @ngroups: The number of entries in @groups.
* @alternate_functions: array describing pins which supports alternate and
* how to set it.
* @pullud: array describing pins which supports pull up/down
* specific registers.
* @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC
* @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
* @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
@ -184,7 +169,6 @@ struct abx500_pinctrl_soc_data {
const struct abx500_pingroup *groups;
unsigned ngroups;
struct alternate_functions *alternate_functions;
struct pullud *pullud;
struct abx500_gpio_irq_cluster *gpio_irq_cluster;
unsigned ngpio_irq_cluster;
int irq_gpio_rising_offset;
@ -205,32 +189,6 @@ abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
#endif
#ifdef CONFIG_PINCTRL_AB8540
void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc);
#else
static inline void
abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
{
}
#endif
#ifdef CONFIG_PINCTRL_AB9540
void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc);
#else
static inline void
abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
{
}
#endif
#ifdef CONFIG_PINCTRL_AB8505
void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);

1243
drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
View File

File diff suppressed because it is too large Load Diff

16
drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
View File

@ -291,7 +291,17 @@ static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
static const unsigned clcd_16_23_b_1_pins[] = { STN8815_PIN_AB6,
STN8815_PIN_AA6, STN8815_PIN_Y6, STN8815_PIN_Y5, STN8815_PIN_AA5,
STN8815_PIN_AB5, STN8815_PIN_AB4, STN8815_PIN_Y4 };
/* Full-speed and high-speed USB pins */
static const unsigned usbfs_b_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20,
STN8815_PIN_C22, STN8815_PIN_D21,
STN8815_PIN_D20, STN8815_PIN_C21,
STN8815_PIN_C20 };
static const unsigned usbhs_c_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20,
STN8815_PIN_C20, STN8815_PIN_C19,
STN8815_PIN_C22, STN8815_PIN_D21,
STN8815_PIN_D20, STN8815_PIN_C21,
STN8815_PIN_C16, STN8815_PIN_A15,
STN8815_PIN_D17, STN8815_PIN_C17 };
#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
@ -308,6 +318,8 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = {
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(usbfs_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(usbhs_c_1, NMK_GPIO_ALT_C),
};
/* We use this macro to define the groups applicable to a function */
@ -321,6 +333,7 @@ STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
STN8815_FUNC_GROUPS(clcd, "clcd_16_23_b_1");
STN8815_FUNC_GROUPS(usb, "usbfs_b_1", "usbhs_c_1");
#define FUNCTION(fname) \
{ \
@ -337,6 +350,7 @@ static const struct nmk_function nmk_stn8815_functions[] = {
FUNCTION(i2c0),
FUNCTION(i2cusb),
FUNCTION(clcd),
FUNCTION(usb),
};
static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {

23
drivers/pinctrl/pinctrl-amd.c
View File

@ -40,6 +40,19 @@
#include "pinctrl-utils.h"
#include "pinctrl-amd.h"
static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags;
u32 pin_reg;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
}
static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
unsigned long flags;
@ -335,12 +348,21 @@ static void amd_gpio_irq_enable(struct irq_data *d)
unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
/*
* When debounce logic is enabled it takes ~900 us before interrupts
* can be enabled. During this "debounce warm up" period the
* "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it
* reads back as 1, signaling that interrupts are now enabled.
*/
while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
continue;
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
@ -845,6 +867,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
#endif
gpio_dev->pdev = pdev;
gpio_dev->gc.get_direction = amd_gpio_get_direction;
gpio_dev->gc.direction_input = amd_gpio_direction_input;
gpio_dev->gc.direction_output = amd_gpio_direction_output;
gpio_dev->gc.get = amd_gpio_get_value;

66
drivers/pinctrl/pinctrl-artpec6.c
View File

@ -277,37 +277,61 @@ static const struct artpec6_pin_group artpec6_pin_groups[] = {
.config = ARTPEC6_CONFIG_3,
},
{
.name = "uart0grp0",
.name = "uart0grp0", /* All pins. */
.pins = uart0_pins0,
.num_pins = ARRAY_SIZE(uart0_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart0grp1",
.name = "uart0grp1", /* RX/TX and RTS/CTS */
.pins = uart0_pins1,
.num_pins = ARRAY_SIZE(uart0_pins1),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart1grp0",
.name = "uart0grp2", /* Only RX/TX pins. */
.pins = uart0_pins1,
.num_pins = ARRAY_SIZE(uart0_pins1) - 2,
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart1grp0", /* RX/TX and RTS/CTS */
.pins = uart1_pins0,
.num_pins = ARRAY_SIZE(uart1_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart2grp0",
.name = "uart1grp1", /* Only RX/TX pins. */
.pins = uart1_pins0,
.num_pins = 2,
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart2grp0", /* Full pinout */
.pins = uart2_pins0,
.num_pins = ARRAY_SIZE(uart2_pins0),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart2grp1",
.name = "uart2grp1", /* RX/TX and RTS/CTS */
.pins = uart2_pins1,
.num_pins = ARRAY_SIZE(uart2_pins1),
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart3grp0",
.name = "uart2grp2", /* Only RX/TX */
.pins = uart2_pins1,
.num_pins = 2,
.config = ARTPEC6_CONFIG_1,
},
{
.name = "uart3grp0", /* RX/TX and CTS/RTS */
.pins = uart3_pins0,
.num_pins = ARRAY_SIZE(uart3_pins0),
.config = ARTPEC6_CONFIG_0,
},
{
.name = "uart3grp1", /* Only RX/TX */
.pins = uart3_pins0,
.num_pins = ARRAY_SIZE(uart3_pins0),
.config = ARTPEC6_CONFIG_0,
@ -319,13 +343,19 @@ static const struct artpec6_pin_group artpec6_pin_groups[] = {
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart5grp0",
.name = "uart5grp0", /* TX/RX and RTS/CTS */
.pins = uart5_pins0,
.num_pins = ARRAY_SIZE(uart5_pins0),
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart5nocts",
.name = "uart5grp1", /* Only TX/RX */
.pins = uart5_pins0,
.num_pins = 2,
.config = ARTPEC6_CONFIG_2,
},
{
.name = "uart5nocts", /* TX/RX/RTS */
.pins = uart5_pins0,
.num_pins = ARRAY_SIZE(uart5_pins0) - 1,
.config = ARTPEC6_CONFIG_2,
@ -457,8 +487,9 @@ static const char * const gpiogrps[] = {
"cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0",
"i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0",
"spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0",
"uart0grp1", "uart1grp0", "uart2grp0", "uart2grp1",
"uart4grp0", "uart5grp0",
"uart0grp1", "uart0grp2", "uart1grp0", "uart1grp1",
"uart2grp0", "uart2grp1", "uart2grp2", "uart4grp0", "uart5grp0",
"uart5grp1", "uart5nocts",
};
static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" };
static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" };
@ -471,12 +502,15 @@ static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" };
static const char * const spi0grps[] = { "spi0grp0" };
static const char * const spi1grps[] = { "spi1grp0" };
static const char * const pciedebuggrps[] = { "pciedebuggrp0" };
static const char * const uart0grps[] = { "uart0grp0", "uart0grp1" };
static const char * const uart1grps[] = { "uart1grp0" };
static const char * const uart2grps[] = { "uart2grp0", "uart2grp1" };
static const char * const uart0grps[] = { "uart0grp0", "uart0grp1",
"uart0grp2" };
static const char * const uart1grps[] = { "uart1grp0", "uart1grp1" };
static const char * const uart2grps[] = { "uart2grp0", "uart2grp1",
"uart2grp2" };
static const char * const uart3grps[] = { "uart3grp0" };
static const char * const uart4grps[] = { "uart4grp0" };
static const char * const uart5grps[] = { "uart5grp0", "uart5nocts" };
static const char * const uart4grps[] = { "uart4grp0", "uart4grp1" };
static const char * const uart5grps[] = { "uart5grp0", "uart5grp1",
"uart5nocts" };
static const char * const nandgrps[] = { "nandgrp0" };
static const char * const sdio0grps[] = { "sdio0grp0" };
static const char * const sdio1grps[] = { "sdio1grp0" };
@ -601,7 +635,7 @@ static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev)
}
static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev,
unsigned int function)
unsigned int function)
{
return artpec6_pmx_functions[function].name;
}

54
drivers/pinctrl/pinctrl-mcp23s08.c
View File

@ -771,6 +771,9 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
{
int status, ret;
bool mirror = false;
bool open_drain = false;
struct regmap_config *one_regmap_config = NULL;
int raw_chip_address = (addr & ~0x40) >> 1;
mutex_init(&mcp->lock);
@ -791,19 +794,33 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
switch (type) {
#ifdef CONFIG_SPI_MASTER
case MCP_TYPE_S08:
mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
&mcp23x08_regmap);
mcp->reg_shift = 0;
mcp->chip.ngpio = 8;
mcp->chip.label = "mcp23s08";
break;
case MCP_TYPE_S17:
switch (type) {
case MCP_TYPE_S08:
one_regmap_config =
devm_kmemdup(dev, &mcp23x08_regmap,
sizeof(struct regmap_config), GFP_KERNEL);
mcp->reg_shift = 0;
mcp->chip.ngpio = 8;
mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL,
"mcp23s08.%d", raw_chip_address);
break;
case MCP_TYPE_S17:
one_regmap_config =
devm_kmemdup(dev, &mcp23x17_regmap,
sizeof(struct regmap_config), GFP_KERNEL);
mcp->reg_shift = 1;
mcp->chip.ngpio = 16;
mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL,
"mcp23s17.%d", raw_chip_address);
break;
}
if (!one_regmap_config)
return -ENOMEM;
one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address);
mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
&mcp23x17_regmap);
mcp->reg_shift = 1;
mcp->chip.ngpio = 16;
mcp->chip.label = "mcp23s17";
one_regmap_config);
break;
case MCP_TYPE_S18:
@ -867,10 +884,11 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
"microchip,irq-active-high");
mirror = device_property_read_bool(dev, "microchip,irq-mirror");
open_drain = device_property_read_bool(dev, "drive-open-drain");
}
if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
mcp->irq_active_high) {
mcp->irq_active_high || open_drain) {
/* mcp23s17 has IOCON twice, make sure they are in sync */
status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
status |= IOCON_HAEN | (IOCON_HAEN << 8);
@ -882,6 +900,9 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
if (mirror)
status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
if (open_drain)
status |= IOCON_ODR | (IOCON_ODR << 8);
if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
status |= IOCON_INTCC | (IOCON_INTCC << 8);
@ -900,7 +921,14 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
if (ret < 0)
goto fail;
mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
if (one_regmap_config) {
mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL,
"mcp23xxx-pinctrl.%d", raw_chip_address);
if (!mcp->pinctrl_desc.name)
return -ENOMEM;
} else {
mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
}
mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
mcp->pinctrl_desc.npins = mcp->chip.ngpio;

4
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -252,7 +252,7 @@ static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
input ? BIT(pin) : 0);
input ? 0 : BIT(pin));
return 0;
}
@ -462,7 +462,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = {
{},
};
int ocelot_pinctrl_probe(struct platform_device *pdev)
static int ocelot_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ocelot_pinctrl *info;

22
drivers/pinctrl/pinctrl-single.c
View File

@ -391,9 +391,25 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
|| pin < frange->offset)
continue;
mux_bytes = pcs->width / BITS_PER_BYTE;
data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
data |= frange->gpiofunc;
pcs->write(data, pcs->base + pin * mux_bytes);
if (pcs->bits_per_mux) {
int byte_num, offset, pin_shift;
byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
offset = (byte_num / mux_bytes) * mux_bytes;
pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
pcs->bits_per_pin;
data = pcs->read(pcs->base + offset);
data &= ~(pcs->fmask << pin_shift);
data |= frange->gpiofunc << pin_shift;
pcs->write(data, pcs->base + offset);
} else {
data = pcs->read(pcs->base + pin * mux_bytes);
data &= ~pcs->fmask;
data |= frange->gpiofunc;
pcs->write(data, pcs->base + pin * mux_bytes);
}
break;
}
return 0;

989
drivers/pinctrl/pinctrl-tz1090-pdc.c
View File

@ -1,989 +0,0 @@
/*
* Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins
*
* Copyright (c) 2013, Imagination Technologies Ltd.
*
* Derived from Tegra code:
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code:
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010 NVIDIA Corporation
* Copyright (C) 2009-2011 ST-Ericsson AB
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
/*
* The registers may be shared with other threads/cores, so we need to use the
* metag global lock2 for atomicity.
*/
#include <asm/global_lock.h>
#include "core.h"
#include "pinconf.h"
/* Register offsets from bank base address */
#define REG_GPIO_CONTROL0 0x00
#define REG_GPIO_CONTROL2 0x08
/* Register field information */
#define REG_GPIO_CONTROL2_PU_PD_S 16
#define REG_GPIO_CONTROL2_PDC_POS_S 4
#define REG_GPIO_CONTROL2_PDC_DR_S 2
#define REG_GPIO_CONTROL2_PDC_SR_S 1
#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0
/* PU_PD field values */
#define REG_PU_PD_TRISTATE 0
#define REG_PU_PD_UP 1
#define REG_PU_PD_DOWN 2
#define REG_PU_PD_REPEATER 3
/* DR field values */
#define REG_DR_2mA 0
#define REG_DR_4mA 1
#define REG_DR_8mA 2
#define REG_DR_12mA 3
/**
* struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function
* @name: The name of the function, exported to pinctrl core.
* @groups: An array of pin groups that may select this function.
* @ngroups: The number of entries in @groups.
*/
struct tz1090_pdc_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
};
/**
* struct tz1090_pdc_pingroup - TZ1090 PDC pin group
* @name: Name of pin group.
* @pins: Array of pin numbers in this pin group.
* @npins: Number of pins in this pin group.
* @func: Function enabled by the mux.
* @reg: Mux register offset.
* @bit: Mux register bit.
* @drv: Drive control supported, otherwise it's a mux.
* This means Schmitt, Slew, and Drive strength.
*
* A representation of a group of pins (possibly just one pin) in the TZ1090
* PDC pin controller. Each group allows some parameter or parameters to be
* configured. The most common is mux function selection.
*/
struct tz1090_pdc_pingroup {
const char *name;
const unsigned int *pins;
unsigned int npins;
int func;
u16 reg;
u8 bit;
bool drv;
};
/*
* All PDC pins can be GPIOs. Define these first to match how the GPIO driver
* names/numbers its pins.
*/
enum tz1090_pdc_pin {
TZ1090_PDC_PIN_GPIO0,
TZ1090_PDC_PIN_GPIO1,
TZ1090_PDC_PIN_SYS_WAKE0,
TZ1090_PDC_PIN_SYS_WAKE1,
TZ1090_PDC_PIN_SYS_WAKE2,
TZ1090_PDC_PIN_IR_DATA,
TZ1090_PDC_PIN_EXT_POWER,
};
/* Pin names */
static const struct pinctrl_pin_desc tz1090_pdc_pins[] = {
/* PDC GPIOs */
PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"),
PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"),
PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"),
PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"),
PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"),
PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"),
PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"),
};
/* Pin group pins */
static const unsigned int gpio0_pins[] = {
TZ1090_PDC_PIN_GPIO0,
};
static const unsigned int gpio1_pins[] = {
TZ1090_PDC_PIN_GPIO1,
};
static const unsigned int pdc_pins[] = {
TZ1090_PDC_PIN_GPIO0,
TZ1090_PDC_PIN_GPIO1,
TZ1090_PDC_PIN_SYS_WAKE0,
TZ1090_PDC_PIN_SYS_WAKE1,
TZ1090_PDC_PIN_SYS_WAKE2,
TZ1090_PDC_PIN_IR_DATA,
TZ1090_PDC_PIN_EXT_POWER,
};
/* Mux functions */
enum tz1090_pdc_mux {
/* PDC_GPIO0 mux */
TZ1090_PDC_MUX_IR_MOD_STABLE_OUT,
/* PDC_GPIO1 mux */
TZ1090_PDC_MUX_IR_MOD_POWER_OUT,
};
/* Pin groups a function can be muxed to */
static const char * const gpio0_groups[] = {
"gpio0",
};
static const char * const gpio1_groups[] = {
"gpio1",
};
#define FUNCTION(mux, fname, group) \
[(TZ1090_PDC_MUX_ ## mux)] = { \
.name = #fname, \
.groups = group##_groups, \
.ngroups = ARRAY_SIZE(group##_groups), \
}
/* Must correlate with enum tz1090_pdc_mux */
static const struct tz1090_pdc_function tz1090_pdc_functions[] = {
/* MUX fn pingroups */
FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0),
FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1),
};
/**
* MUX_PG() - Initialise a pin group with mux control
* @pg_name: Pin group name (stringified, _pins appended to get pins array)
* @f0: Function 0 (TZ1090_PDC_MUX_ is prepended)
* @mux_r: Mux register (REG_PINCTRL_ is prepended)
* @mux_b: Bit number in register of mux field
*/
#define MUX_PG(pg_name, f0, mux_r, mux_b) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.func = TZ1090_PDC_MUX_ ## f0, \
.reg = (REG_ ## mux_r), \
.bit = (mux_b), \
}
/**
* DRV_PG() - Initialise a pin group with drive control
* @pg_name: Pin group name (stringified, _pins appended to get pins array)
*/
#define DRV_PG(pg_name) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.drv = true, \
}
static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = {
/* Muxing pin groups */
/* pg_name, f0, mux register, mux bit */
MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7),
MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6),
/* Drive pin groups */
/* pg_name */
DRV_PG(pdc),
};
/**
* struct tz1090_pdc_pmx - Private pinctrl data
* @dev: Platform device
* @pctl: Pin control device
* @regs: Register region
* @lock: Lock protecting coherency of mux_en and gpio_en
* @mux_en: Muxes that have been enabled
* @gpio_en: Muxable GPIOs that have been enabled
*/
struct tz1090_pdc_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *regs;
spinlock_t lock;
u32 mux_en;
u32 gpio_en;
};
static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg)
{
return ioread32(pmx->regs + reg);
}
static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg)
{
iowrite32(val, pmx->regs + reg);
}
/*
* Pin control operations
*/
static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(tz1090_pdc_groups);
}
static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl,
unsigned int group)
{
return tz1090_pdc_groups[group].name;
}
static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
*pins = tz1090_pdc_groups[group].pins;
*num_pins = tz1090_pdc_groups[group].npins;
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
#endif
static int reserve_map(struct device *dev, struct pinctrl_map **map,
unsigned int *reserved_maps, unsigned int *num_maps,
unsigned int reserve)
{
unsigned int old_num = *reserved_maps;
unsigned int new_num = *num_maps + reserve;
struct pinctrl_map *new_map;
if (old_num >= new_num)
return 0;
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
if (!new_map) {
dev_err(dev, "krealloc(map) failed\n");
return -ENOMEM;
}
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
*map = new_map;
*reserved_maps = new_num;
return 0;
}
static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
unsigned int *num_maps, const char *group,
const char *function)
{
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = group;
(*map)[*num_maps].data.mux.function = function;
(*num_maps)++;
return 0;
}
/**
* get_group_selector() - returns the group selector for a group
* @pin_group: the pin group to look up
*
* This is the same as pinctrl_get_group_selector except it doesn't produce an
* error message if the group isn't found or debug messages.
*/
static int get_group_selector(const char *pin_group)
{
unsigned int group;
for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group)
if (!strcmp(tz1090_pdc_groups[group].name, pin_group))
return group;
return -EINVAL;
}
static int add_map_configs(struct device *dev,
struct pinctrl_map **map,
unsigned int *reserved_maps, unsigned int *num_maps,
const char *group, unsigned long *configs,
unsigned int num_configs)
{
unsigned long *dup_configs;
enum pinctrl_map_type type;
if (WARN_ON(*num_maps == *reserved_maps))
return -ENOSPC;
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
GFP_KERNEL);
if (!dup_configs)
return -ENOMEM;
/*
* We support both pins and pin groups, but we need to figure out which
* one we have.
*/
if (get_group_selector(group) >= 0)
type = PIN_MAP_TYPE_CONFIGS_GROUP;
else
type = PIN_MAP_TYPE_CONFIGS_PIN;
(*map)[*num_maps].type = type;
(*map)[*num_maps].data.configs.group_or_pin = group;
(*map)[*num_maps].data.configs.configs = dup_configs;
(*map)[*num_maps].data.configs.num_configs = num_configs;
(*num_maps)++;
return 0;
}
static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map,
unsigned int num_maps)
{
int i;
for (i = 0; i < num_maps; i++)
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
kfree(map[i].data.configs.configs);
kfree(map);
}
static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *reserved_maps,
unsigned int *num_maps)
{
int ret;
const char *function;
unsigned long *configs = NULL;
unsigned int num_configs = 0;
unsigned int reserve;
struct property *prop;
const char *group;
ret = of_property_read_string(np, "tz1090,function", &function);
if (ret < 0) {
/* EINVAL=missing, which is fine since it's optional */
if (ret != -EINVAL)
dev_err(dev,
"could not parse property function\n");
function = NULL;
}
ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
if (ret)
return ret;
reserve = 0;
if (function != NULL)
reserve++;
if (num_configs)
reserve++;
ret = of_property_count_strings(np, "tz1090,pins");
if (ret < 0) {
dev_err(dev, "could not parse property pins\n");
goto exit;
}
reserve *= ret;
ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "tz1090,pins", prop, group) {
if (function) {
ret = add_map_mux(map, reserved_maps, num_maps,
group, function);
if (ret < 0)
goto exit;
}
if (num_configs) {
ret = add_map_configs(dev, map, reserved_maps,
num_maps, group, configs,
num_configs);
if (ret < 0)
goto exit;
}
}
ret = 0;
exit:
kfree(configs);
return ret;
}
static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map,
unsigned int *num_maps)
{
unsigned int reserved_maps;
struct device_node *np;
int ret;
reserved_maps = 0;
*map = NULL;
*num_maps = 0;
for_each_child_of_node(np_config, np) {
ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np,
map, &reserved_maps,
num_maps);
if (ret < 0) {
tz1090_pdc_pinctrl_dt_free_map(pctldev, *map,
*num_maps);
return ret;
}
}
return 0;
}
static const struct pinctrl_ops tz1090_pdc_pinctrl_ops = {
.get_groups_count = tz1090_pdc_pinctrl_get_groups_count,
.get_group_name = tz1090_pdc_pinctrl_get_group_name,
.get_group_pins = tz1090_pdc_pinctrl_get_group_pins,
#ifdef CONFIG_DEBUG_FS
.pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show,
#endif
.dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map,
.dt_free_map = tz1090_pdc_pinctrl_dt_free_map,
};
/*
* Pin mux operations
*/
static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(tz1090_pdc_functions);
}
static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
return tz1090_pdc_functions[function].name;
}
static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
*groups = tz1090_pdc_functions[function].groups;
*num_groups = tz1090_pdc_functions[function].ngroups;
return 0;
}
/**
* tz1090_pdc_pinctrl_mux() - update mux bit
* @pmx: Pinmux data
* @grp: Pin mux group
*/
static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
const struct tz1090_pdc_pingroup *grp)
{
u32 reg, select;
unsigned int pin_shift = grp->pins[0];
unsigned long flags;
/* select = mux && !gpio */
select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1;
/* set up the mux */
__global_lock2(flags);
reg = pmx_read(pmx, grp->reg);
reg &= ~BIT(grp->bit);
reg |= select << grp->bit;
pmx_write(pmx, reg, grp->reg);
__global_unlock2(flags);
}
static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
__func__,
function, tz1090_pdc_functions[function].name,
group, tz1090_pdc_groups[group].name);
/* is it even a mux? */
if (grp->drv)
return -EINVAL;
/* does this group even control the function? */
if (function != grp->func)
return -EINVAL;
/* record the pin being muxed and update mux bit */
spin_lock(&pmx->lock);
pmx->mux_en |= BIT(grp->pins[0]);
tz1090_pdc_pinctrl_mux(pmx, grp);
spin_unlock(&pmx->lock);
return 0;
}
static const struct tz1090_pdc_pingroup *find_mux_group(
struct tz1090_pdc_pmx *pmx,
unsigned int pin)
{
const struct tz1090_pdc_pingroup *grp;
unsigned int group;
grp = tz1090_pdc_groups;
for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) {
/* only match muxes */
if (grp->drv)
continue;
/* with a matching pin */
if (grp->pins[0] == pin)
return grp;
}
return NULL;
}
static int tz1090_pdc_pinctrl_gpio_request_enable(
struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
if (grp) {
/* record the pin in GPIO use and update mux bit */
spin_lock(&pmx->lock);
pmx->gpio_en |= BIT(pin);
tz1090_pdc_pinctrl_mux(pmx, grp);
spin_unlock(&pmx->lock);
}
return 0;
}
static void tz1090_pdc_pinctrl_gpio_disable_free(
struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
if (grp) {
/* record the pin not in GPIO use and update mux bit */
spin_lock(&pmx->lock);
pmx->gpio_en &= ~BIT(pin);
tz1090_pdc_pinctrl_mux(pmx, grp);
spin_unlock(&pmx->lock);
}
}
static const struct pinmux_ops tz1090_pdc_pinmux_ops = {
.get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
.get_function_name = tz1090_pdc_pinctrl_get_func_name,
.get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
.set_mux = tz1090_pdc_pinctrl_set_mux,
.gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
.gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
};
/*
* Pin config operations
*/
static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev,
unsigned int pin,
enum pin_config_param param,
bool report_err,
u32 *reg, u32 *width, u32 *mask, u32 *shift,
u32 *val)
{
/* Find information about parameter's register */
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*val = REG_PU_PD_TRISTATE;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*val = REG_PU_PD_UP;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*val = REG_PU_PD_DOWN;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
*val = REG_PU_PD_REPEATER;
break;
default:
return -ENOTSUPP;
}
/* Only input bias parameters supported */
*reg = REG_GPIO_CONTROL2;
*shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2;
*width = 2;
/* Calculate field information */
*mask = (BIT(*width) - 1) << *shift;
return 0;
}
static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
int ret;
u32 reg, width, mask, shift, val, tmp, arg;
/* Get register information */
ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
&reg, &width, &mask, &shift, &val);
if (ret < 0)
return ret;
/* Extract field from register */
tmp = pmx_read(pmx, reg);
arg = ((tmp & mask) >> shift) == val;
/* Config not active */
if (!arg)
return -EINVAL;
/* And pack config */
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned num_configs)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
unsigned int arg;
int ret;
u32 reg, width, mask, shift, val, tmp;
unsigned long flags;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
__func__, tz1090_pdc_pins[pin].name, configs[i]);
/* Get register information */
ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
&reg, &width, &mask, &shift, &val);
if (ret < 0)
return ret;
/* Unpack argument and range check it */
if (arg > 1) {
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
__func__, arg);
return -EINVAL;
}
/* Write register field */
__global_lock2(flags);
tmp = pmx_read(pmx, reg);
tmp &= ~mask;
if (arg)
tmp |= val << shift;
pmx_write(pmx, tmp, reg);
__global_unlock2(flags);
} /* for each config */
return 0;
}
static const int tz1090_pdc_boolean_map[] = {
[0] = -EINVAL,
[1] = 1,
};
static const int tz1090_pdc_dr_map[] = {
[REG_DR_2mA] = 2,
[REG_DR_4mA] = 4,
[REG_DR_8mA] = 8,
[REG_DR_12mA] = 12,
};
static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev,
const struct tz1090_pdc_pingroup *g,
enum pin_config_param param,
bool report_err, u32 *reg, u32 *width,
u32 *mask, u32 *shift, const int **map)
{
/* Drive configuration applies in groups, but not to all groups. */
if (!g->drv) {
if (report_err)
dev_dbg(pctldev->dev,
"%s: group %s has no drive control\n",
__func__, g->name);
return -ENOTSUPP;
}
/* Find information about drive parameter's register */
*reg = REG_GPIO_CONTROL2;
switch (param) {
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S;
*width = 1;
*map = tz1090_pdc_boolean_map;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
*shift = REG_GPIO_CONTROL2_PDC_DR_S;
*width = 2;
*map = tz1090_pdc_dr_map;
break;
case PIN_CONFIG_LOW_POWER_MODE:
*shift = REG_GPIO_CONTROL2_PDC_POS_S;
*width = 1;
*map = tz1090_pdc_boolean_map;
break;
default:
return -ENOTSUPP;
}
/* Calculate field information */
*mask = (BIT(*width) - 1) << *shift;
return 0;
}
static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *config)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
enum pin_config_param param = pinconf_to_config_param(*config);
int ret, arg;
u32 reg, width, mask, shift, val;
const int *map;
/* Get register information */
ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
&reg, &width, &mask, &shift, &map);
if (ret < 0)
return ret;
/* Extract field from register */
val = pmx_read(pmx, reg);
arg = map[(val & mask) >> shift];
if (arg < 0)
return arg;
/* And pack config */
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *configs,
unsigned num_configs)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
enum pin_config_param param;
const unsigned int *pit;
unsigned int i;
int ret, arg;
u32 reg, width, mask, shift, val;
unsigned long flags;
const int *map;
int j;
for (j = 0; j < num_configs; j++) {
param = pinconf_to_config_param(configs[j]);
dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
__func__, g->name, configs[j]);
/* Get register information */
ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
&reg, &width, &mask, &shift,
&map);
if (ret < 0) {
/*
* Maybe we're trying to set a per-pin configuration
* of a group, so do the pins one by one. This is
* mainly as a convenience.
*/
for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
ret = tz1090_pdc_pinconf_set(pctldev, *pit,
configs, num_configs);
if (ret)
return ret;
}
return 0;
}
/* Unpack argument and map it to register value */
arg = pinconf_to_config_argument(configs[j]);
for (i = 0; i < BIT(width); ++i) {
if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
/* Write register field */
__global_lock2(flags);
val = pmx_read(pmx, reg);
val &= ~mask;
val |= i << shift;
pmx_write(pmx, val, reg);
__global_unlock2(flags);
goto next_config;
}
}
dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
__func__, arg);
return 0;
next_config:
;
} /* for each config */
return 0;
}
static const struct pinconf_ops tz1090_pdc_pinconf_ops = {
.is_generic = true,
.pin_config_get = tz1090_pdc_pinconf_get,
.pin_config_set = tz1090_pdc_pinconf_set,
.pin_config_group_get = tz1090_pdc_pinconf_group_get,
.pin_config_group_set = tz1090_pdc_pinconf_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
/*
* Pin control driver setup
*/
static struct pinctrl_desc tz1090_pdc_pinctrl_desc = {
.pctlops = &tz1090_pdc_pinctrl_ops,
.pmxops = &tz1090_pdc_pinmux_ops,
.confops = &tz1090_pdc_pinconf_ops,
.owner = THIS_MODULE,
};
static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
{
struct tz1090_pdc_pmx *pmx;
struct resource *res;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
return -ENOMEM;
pmx->dev = &pdev->dev;
spin_lock_init(&pmx->lock);
tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev);
tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins;
tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pmx->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pmx->regs))
return PTR_ERR(pmx->regs);
pmx->pctl = devm_pinctrl_register(&pdev->dev, &tz1090_pdc_pinctrl_desc,
pmx);
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(pmx->pctl);
}
platform_set_drvdata(pdev, pmx);
dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n");
return 0;
}
static const struct of_device_id tz1090_pdc_pinctrl_of_match[] = {
{ .compatible = "img,tz1090-pdc-pinctrl", },
{ },
};
static struct platform_driver tz1090_pdc_pinctrl_driver = {
.driver = {
.name = "tz1090-pdc-pinctrl",
.of_match_table = tz1090_pdc_pinctrl_of_match,
},
.probe = tz1090_pdc_pinctrl_probe,
};
static int __init tz1090_pdc_pinctrl_init(void)
{
return platform_driver_register(&tz1090_pdc_pinctrl_driver);
}
arch_initcall(tz1090_pdc_pinctrl_init);
static void __exit tz1090_pdc_pinctrl_exit(void)
{
platform_driver_unregister(&tz1090_pdc_pinctrl_driver);
}
module_exit(tz1090_pdc_pinctrl_exit);
MODULE_AUTHOR("Imagination Technologies Ltd.");
MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match);

2005
drivers/pinctrl/pinctrl-tz1090.c
View File

File diff suppressed because it is too large Load Diff

9
drivers/pinctrl/qcom/Kconfig
View File

@ -147,4 +147,13 @@ config PINCTRL_QCOM_SSBI_PMIC
which are using SSBI for communication with SoC. Example PMIC's
devices are pm8058 and pm8921.
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM845 platform.
endif

1
drivers/pinctrl/qcom/Makefile
View File

@ -19,3 +19,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o

2
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -818,7 +818,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
return -EINVAL;
chip = &pctrl->chip;
chip->base = 0;
chip->base = -1;
chip->ngpio = ngpio;
chip->label = dev_name(pctrl->dev);
chip->parent = pctrl->dev;

1
drivers/pinctrl/qcom/pinctrl-msm8998.c
View File

@ -1566,7 +1566,6 @@ static const struct of_device_id msm8998_pinctrl_of_match[] = {
static struct platform_driver msm8998_pinctrl_driver = {
.driver = {
.name = "msm8998-pinctrl",
.owner = THIS_MODULE,
.of_match_table = msm8998_pinctrl_of_match,
},
.probe = msm8998_pinctrl_probe,

1323
drivers/pinctrl/qcom/pinctrl-sdm845.c Normal file
View File

File diff suppressed because it is too large Load Diff

10
drivers/pinctrl/sh-pfc/Kconfig
View File

@ -89,11 +89,21 @@ config PINCTRL_PFC_R8A7796
depends on ARCH_R8A7796
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77965
def_bool y
depends on ARCH_R8A77965
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77970
def_bool y
depends on ARCH_R8A77970
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77980
def_bool y
depends on ARCH_R8A77980
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77995
def_bool y
depends on ARCH_R8A77995

2
drivers/pinctrl/sh-pfc/Makefile
View File

@ -16,7 +16,9 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o

12
drivers/pinctrl/sh-pfc/core.c
View File

@ -557,12 +557,24 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a7796_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77965
{
.compatible = "renesas,pfc-r8a77965",
.data = &r8a77965_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77970
{
.compatible = "renesas,pfc-r8a77970",
.data = &r8a77970_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77980
{
.compatible = "renesas,pfc-r8a77980",
.data = &r8a77980_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77995
{
.compatible = "renesas,pfc-r8a77995",

8
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

@ -1835,8 +1835,8 @@ static const unsigned int avb_mii_pins[] = {
RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
RCAR_GP_PIN(3, 12),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
};
static const unsigned int avb_mii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
@ -1846,8 +1846,8 @@ static const unsigned int avb_mii_mux[] = {
AVB_RXD3_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
AVB_TX_CLK_MARK, AVB_COL_MARK,
};
static const unsigned int avb_gmii_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),

82
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
View File

@ -1,7 +1,7 @@
/*
* R8A7795 ES1.x processor support - PFC hardware block.
*
* Copyright (C) 2015 Renesas Electronics Corporation
* Copyright (C) 2015-2017 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -1652,11 +1652,11 @@ static const unsigned int avb_phy_int_pins[] = {
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdc_pins[] = {
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
};
static const unsigned int avb_mdc_mux[] = {
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
@ -2067,6 +2067,22 @@ static const unsigned int du_disp_pins[] = {
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HDMI ------------------------------------------------------------------- */
static const unsigned int hdmi0_cec_pins[] = {
/* HDMI0_CEC */
RCAR_GP_PIN(7, 2),
};
static const unsigned int hdmi0_cec_mux[] = {
HDMI0_CEC_MARK,
};
static const unsigned int hdmi1_cec_pins[] = {
/* HDMI1_CEC */
RCAR_GP_PIN(7, 3),
};
static const unsigned int hdmi1_cec_mux[] = {
HDMI1_CEC_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@ -3750,6 +3766,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - TMU -------------------------------------------------------------------- */
static const unsigned int tmu_tclk1_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 23),
};
static const unsigned int tmu_tclk1_a_mux[] = {
TCLK1_A_MARK,
};
static const unsigned int tmu_tclk1_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(5, 19),
};
static const unsigned int tmu_tclk1_b_mux[] = {
TCLK1_B_MARK,
};
static const unsigned int tmu_tclk2_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 19),
};
static const unsigned int tmu_tclk2_a_mux[] = {
TCLK2_A_MARK,
};
static const unsigned int tmu_tclk2_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@ -3813,7 +3859,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdc),
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
@ -3865,6 +3912,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@ -4095,6 +4144,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(tmu_tclk1_a),
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@ -4126,7 +4179,8 @@ static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdc",
"avb_mdc", /* Deprecated, please use "avb_mdio" instead */
"avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
@ -4210,6 +4264,14 @@ static const char * const du_groups[] = {
"du_disp",
};
static const char * const hdmi0_groups[] = {
"hdmi0_cec",
};
static const char * const hdmi1_groups[] = {
"hdmi1_cec",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@ -4545,6 +4607,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
static const char * const tmu_groups[] = {
"tmu_tclk1_a",
"tmu_tclk1_b",
"tmu_tclk2_a",
"tmu_tclk2_b",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -4578,6 +4647,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@ -4613,6 +4684,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),

410
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View File

@ -1,7 +1,7 @@
/*
* R8A7795 ES2.0+ processor support - PFC hardware block.
*
* Copyright (C) 2015-2016 Renesas Electronics Corporation
* Copyright (C) 2015-2017 Renesas Electronics Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -472,7 +472,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
@ -1218,7 +1218,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
@ -1226,14 +1226,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
@ -1241,7 +1241,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
@ -1250,7 +1250,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
@ -1265,7 +1265,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
@ -1274,7 +1274,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
@ -1302,10 +1302,10 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
/* IPSR15 */
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
@ -1394,11 +1394,11 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
@ -1430,7 +1430,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
@ -1440,7 +1440,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
@ -1450,7 +1450,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
@ -1462,7 +1462,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
@ -1473,7 +1473,7 @@ static const u16 pinmux_data[] = {
/* IPSR18 */
PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
@ -1483,7 +1483,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
@ -1711,11 +1711,11 @@ static const unsigned int avb_phy_int_pins[] = {
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdc_pins[] = {
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
};
static const unsigned int avb_mdc_mux[] = {
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
@ -2127,6 +2127,22 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HDMI ------------------------------------------------------------------- */
static const unsigned int hdmi0_cec_pins[] = {
/* HDMI0_CEC */
RCAR_GP_PIN(7, 2),
};
static const unsigned int hdmi0_cec_mux[] = {
HDMI0_CEC_MARK,
};
static const unsigned int hdmi1_cec_pins[] = {
/* HDMI1_CEC */
RCAR_GP_PIN(7, 3),
};
static const unsigned int hdmi1_cec_mux[] = {
HDMI1_CEC_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@ -3839,6 +3855,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - TMU -------------------------------------------------------------------- */
static const unsigned int tmu_tclk1_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 23),
};
static const unsigned int tmu_tclk1_a_mux[] = {
TCLK1_A_MARK,
};
static const unsigned int tmu_tclk1_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(5, 19),
};
static const unsigned int tmu_tclk1_b_mux[] = {
TCLK1_B_MARK,
};
static const unsigned int tmu_tclk2_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 19),
};
static const unsigned int tmu_tclk2_a_mux[] = {
TCLK2_A_MARK,
};
static const unsigned int tmu_tclk2_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@ -3881,6 +3927,236 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_a_pins[] = {
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data18_b_pins[] = {
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_a_pins = {
.data24 = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_a_mux = {
.data24 = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const union vin_data vin4_data_b_pins = {
.data24 = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_b_mux = {
.data24 = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
/* FIELD */
RCAR_GP_PIN(1, 16),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
/* CLKENB */
RCAR_GP_PIN(1, 19),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 27),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const unsigned int vin5_data8_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin5_data8_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
};
static const unsigned int vin5_data10_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
};
static const unsigned int vin5_data10_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
};
static const unsigned int vin5_data12_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
};
static const unsigned int vin5_data12_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
};
static const unsigned int vin5_data16_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_data16_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
};
static const unsigned int vin5_sync_mux[] = {
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
};
static const unsigned int vin5_field_pins[] = {
RCAR_GP_PIN(1, 11),
};
static const unsigned int vin5_field_mux[] = {
/* FIELD */
VI5_FIELD_MARK,
};
static const unsigned int vin5_clkenb_pins[] = {
RCAR_GP_PIN(1, 20),
};
static const unsigned int vin5_clkenb_mux[] = {
/* CLKENB */
VI5_CLKENB_MARK,
};
static const unsigned int vin5_clk_pins[] = {
RCAR_GP_PIN(1, 21),
};
static const unsigned int vin5_clk_mux[] = {
/* CLK */
VI5_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
@ -3902,7 +4178,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdc),
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
@ -3954,6 +4231,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@ -4189,11 +4468,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(tmu_tclk1_a),
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(usb2_ch3),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
SH_PFC_PIN_GROUP(vin5_data8),
SH_PFC_PIN_GROUP(vin5_data10),
SH_PFC_PIN_GROUP(vin5_data12),
SH_PFC_PIN_GROUP(vin5_data16),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
};
static const char * const audio_clk_groups[] = {
@ -4220,7 +4529,8 @@ static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdc",
"avb_mdc", /* Deprecated, please use "avb_mdio" instead */
"avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
@ -4304,6 +4614,14 @@ static const char * const du_groups[] = {
"du_disp",
};
static const char * const hdmi0_groups[] = {
"hdmi0_cec",
};
static const char * const hdmi1_groups[] = {
"hdmi1_cec",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@ -4638,6 +4956,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
static const char * const tmu_groups[] = {
"tmu_tclk1_a",
"tmu_tclk1_b",
"tmu_tclk2_a",
"tmu_tclk2_b",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -4658,6 +4983,38 @@ static const char * const usb30_groups[] = {
"usb30",
};
static const char * const vin4_groups[] = {
"vin4_data8_a",
"vin4_data10_a",
"vin4_data12_a",
"vin4_data16_a",
"vin4_data18_a",
"vin4_data20_a",
"vin4_data24_a",
"vin4_data8_b",
"vin4_data10_b",
"vin4_data12_b",
"vin4_data16_b",
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const char * const vin5_groups[] = {
"vin5_data8",
"vin5_data10",
"vin5_data12",
"vin5_data16",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
"vin5_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@ -4671,6 +5028,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@ -4704,11 +5063,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
SH_PFC_FUNCTION(usb2_ch3),
SH_PFC_FUNCTION(usb30),
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

415
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View File

@ -1,7 +1,7 @@
/*
* R8A7796 processor support - PFC hardware block.
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016-2017 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
*
@ -477,7 +477,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
@ -502,7 +502,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
@ -1016,35 +1016,35 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
@ -1110,16 +1110,20 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
@ -1218,7 +1222,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
@ -1226,14 +1230,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
@ -1241,7 +1245,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
@ -1250,7 +1254,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
@ -1263,9 +1267,9 @@ static const u16 pinmux_data[] = {
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
@ -1274,7 +1278,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
@ -1302,10 +1306,10 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
/* IPSR15 */
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
@ -1391,11 +1395,11 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
@ -1427,7 +1431,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
@ -1437,7 +1441,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
@ -1447,7 +1451,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
@ -1459,7 +1463,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
@ -1470,7 +1474,7 @@ static const u16 pinmux_data[] = {
/* IPSR18 */
PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
@ -1480,7 +1484,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
@ -1713,11 +1717,11 @@ static const unsigned int avb_phy_int_pins[] = {
static const unsigned int avb_phy_int_mux[] = {
AVB_PHY_INT_MARK,
};
static const unsigned int avb_mdc_pins[] = {
static const unsigned int avb_mdio_pins[] = {
/* AVB_MDC, AVB_MDIO */
RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
};
static const unsigned int avb_mdc_mux[] = {
static const unsigned int avb_mdio_mux[] = {
AVB_MDC_MARK, AVB_MDIO_MARK,
};
static const unsigned int avb_mii_pins[] = {
@ -2129,6 +2133,15 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HDMI ------------------------------------------------------------------- */
static const unsigned int hdmi0_cec_pins[] = {
/* HDMI0_CEC */
RCAR_GP_PIN(7, 2),
};
static const unsigned int hdmi0_cec_mux[] = {
HDMI0_CEC_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@ -3827,6 +3840,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - TMU -------------------------------------------------------------------- */
static const unsigned int tmu_tclk1_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 23),
};
static const unsigned int tmu_tclk1_a_mux[] = {
TCLK1_A_MARK,
};
static const unsigned int tmu_tclk1_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(5, 19),
};
static const unsigned int tmu_tclk1_b_mux[] = {
TCLK1_B_MARK,
};
static const unsigned int tmu_tclk2_a_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 19),
};
static const unsigned int tmu_tclk2_a_mux[] = {
TCLK2_A_MARK,
};
static const unsigned int tmu_tclk2_b_pins[] = {
/* TCLK */
RCAR_GP_PIN(6, 28),
};
static const unsigned int tmu_tclk2_b_mux[] = {
TCLK2_B_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@ -3853,6 +3896,236 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_a_pins[] = {
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_data18_b_pins[] = {
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_a_pins = {
.data24 = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_a_mux = {
.data24 = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const union vin_data vin4_data_b_pins = {
.data24 = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_b_mux = {
.data24 = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
/* FIELD */
RCAR_GP_PIN(1, 16),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
/* CLKENB */
RCAR_GP_PIN(1, 19),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 27),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const unsigned int vin5_data8_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin5_data8_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
};
static const unsigned int vin5_data10_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
};
static const unsigned int vin5_data10_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
};
static const unsigned int vin5_data12_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
};
static const unsigned int vin5_data12_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
};
static const unsigned int vin5_data16_pins[] = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_data16_mux[] = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
};
static const unsigned int vin5_sync_mux[] = {
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
};
static const unsigned int vin5_field_pins[] = {
RCAR_GP_PIN(1, 11),
};
static const unsigned int vin5_field_mux[] = {
/* FIELD */
VI5_FIELD_MARK,
};
static const unsigned int vin5_clkenb_pins[] = {
RCAR_GP_PIN(1, 20),
};
static const unsigned int vin5_clkenb_mux[] = {
/* CLKENB */
VI5_CLKENB_MARK,
};
static const unsigned int vin5_clk_pins[] = {
RCAR_GP_PIN(1, 21),
};
static const unsigned int vin5_clk_mux[] = {
/* CLK */
VI5_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
@ -3874,7 +4147,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mdc),
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a),
@ -3926,6 +4200,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@ -4159,9 +4434,39 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(tmu_tclk1_a),
SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
SH_PFC_PIN_GROUP(vin5_data8),
SH_PFC_PIN_GROUP(vin5_data10),
SH_PFC_PIN_GROUP(vin5_data12),
SH_PFC_PIN_GROUP(vin5_data16),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
};
static const char * const audio_clk_groups[] = {
@ -4188,7 +4493,8 @@ static const char * const avb_groups[] = {
"avb_link",
"avb_magic",
"avb_phy_int",
"avb_mdc",
"avb_mdc", /* Deprecated, please use "avb_mdio" instead */
"avb_mdio",
"avb_mii",
"avb_avtp_pps",
"avb_avtp_match_a",
@ -4272,6 +4578,10 @@ static const char * const du_groups[] = {
"du_disp",
};
static const char * const hdmi0_groups[] = {
"hdmi0_cec",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@ -4601,6 +4911,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
static const char * const tmu_groups[] = {
"tmu_tclk1_a",
"tmu_tclk1_b",
"tmu_tclk2_a",
"tmu_tclk2_b",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -4613,6 +4930,38 @@ static const char * const usb30_groups[] = {
"usb30",
};
static const char * const vin4_groups[] = {
"vin4_data8_a",
"vin4_data10_a",
"vin4_data12_a",
"vin4_data16_a",
"vin4_data18_a",
"vin4_data20_a",
"vin4_data24_a",
"vin4_data8_b",
"vin4_data10_b",
"vin4_data12_b",
"vin4_data16_b",
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const char * const vin5_groups[] = {
"vin5_data8",
"vin5_data10",
"vin5_data12",
"vin5_data16",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
"vin5_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@ -4626,6 +4975,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@ -4658,9 +5008,12 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

3243
drivers/pinctrl/sh-pfc/pfc-r8a77965.c Normal file
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File diff suppressed because it is too large Load Diff

98
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
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@ -728,6 +728,82 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
/* - AVB0 ------------------------------------------------------------------- */
static const unsigned int avb0_link_pins[] = {
/* AVB0_LINK */
RCAR_GP_PIN(1, 18),
};
static const unsigned int avb0_link_mux[] = {
AVB0_LINK_MARK,
};
static const unsigned int avb0_magic_pins[] = {
/* AVB0_MAGIC */
RCAR_GP_PIN(1, 16),
};
static const unsigned int avb0_magic_mux[] = {
AVB0_MAGIC_MARK,
};
static const unsigned int avb0_phy_int_pins[] = {
/* AVB0_PHY_INT */
RCAR_GP_PIN(1, 17),
};
static const unsigned int avb0_phy_int_mux[] = {
AVB0_PHY_INT_MARK,
};
static const unsigned int avb0_mdio_pins[] = {
/* AVB0_MDC, AVB0_MDIO */
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
};
static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
static const unsigned int avb0_rgmii_pins[] = {
/*
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
* AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
*/
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
};
static const unsigned int avb0_rgmii_mux[] = {
AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
};
static const unsigned int avb0_txcrefclk_pins[] = {
/* AVB0_TXCREFCLK */
RCAR_GP_PIN(1, 13),
};
static const unsigned int avb0_txcrefclk_mux[] = {
AVB0_TXCREFCLK_MARK,
};
static const unsigned int avb0_avtp_pps_pins[] = {
/* AVB0_AVTP_PPS */
RCAR_GP_PIN(2, 6),
};
static const unsigned int avb0_avtp_pps_mux[] = {
AVB0_AVTP_PPS_MARK,
};
static const unsigned int avb0_avtp_capture_pins[] = {
/* AVB0_AVTP_CAPTURE */
RCAR_GP_PIN(1, 20),
};
static const unsigned int avb0_avtp_capture_mux[] = {
AVB0_AVTP_CAPTURE_MARK,
};
static const unsigned int avb0_avtp_match_pins[] = {
/* AVB0_AVTP_MATCH */
RCAR_GP_PIN(1, 19),
};
static const unsigned int avb0_avtp_match_mux[] = {
AVB0_AVTP_MATCH_MARK,
};
/* - CANFD Clock ------------------------------------------------------------ */
static const unsigned int canfd_clk_a_pins[] = {
/* CANFD_CLK */
@ -1599,6 +1675,15 @@ static const unsigned int vin1_clk_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
SH_PFC_PIN_GROUP(avb0_mdio),
SH_PFC_PIN_GROUP(avb0_rgmii),
SH_PFC_PIN_GROUP(avb0_txcrefclk),
SH_PFC_PIN_GROUP(avb0_avtp_pps),
SH_PFC_PIN_GROUP(avb0_avtp_capture),
SH_PFC_PIN_GROUP(avb0_avtp_match),
SH_PFC_PIN_GROUP(canfd_clk_a),
SH_PFC_PIN_GROUP(canfd_clk_b),
SH_PFC_PIN_GROUP(canfd0_data_a),
@ -1709,6 +1794,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(vin1_clk),
};
static const char * const avb0_groups[] = {
"avb0_link",
"avb0_magic",
"avb0_phy_int",
"avb0_mdio",
"avb0_rgmii",
"avb0_txcrefclk",
"avb0_avtp_pps",
"avb0_avtp_capture",
"avb0_avtp_match",
};
static const char * const canfd_clk_groups[] = {
"canfd_clk_a",
"canfd_clk_b",
@ -1914,6 +2011,7 @@ static const char * const vin1_groups[] = {
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(canfd_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),

2799
drivers/pinctrl/sh-pfc/pfc-r8a77980.c Normal file
View File

File diff suppressed because it is too large Load Diff

221
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
View File

@ -988,11 +988,11 @@ static const unsigned int avb0_phy_int_pins[] = {
static const unsigned int avb0_phy_int_mux[] = {
AVB0_PHY_INT_MARK,
};
static const unsigned int avb0_mdc_pins[] = {
static const unsigned int avb0_mdio_pins[] = {
/* AVB0_MDC, AVB0_MDIO */
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
};
static const unsigned int avb0_mdc_mux[] = {
static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
static const unsigned int avb0_mii_pins[] = {
@ -1114,6 +1114,87 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
};
static const unsigned int du_rgb666_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK,
};
static const unsigned int du_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int du_rgb888_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
};
static const unsigned int du_clk_in_1_pins[] = {
/* CLKIN */
RCAR_GP_PIN(1, 28),
};
static const unsigned int du_clk_in_1_mux[] = {
DU_DOTCLKIN1_MARK
};
static const unsigned int du_clk_out_0_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(1, 24),
};
static const unsigned int du_clk_out_0_mux[] = {
DU_DOTCLKOUT0_MARK
};
static const unsigned int du_sync_pins[] = {
/* VSYNC, HSYNC */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int du_sync_mux[] = {
DU_VSYNC_MARK, DU_HSYNC_MARK
};
static const unsigned int du_disp_cde_pins[] = {
/* DISP_CDE */
RCAR_GP_PIN(1, 28),
};
static const unsigned int du_disp_cde_mux[] = {
DU_DISP_CDE_MARK,
};
static const unsigned int du_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(1, 29),
};
static const unsigned int du_cde_mux[] = {
DU_CDE_MARK,
};
static const unsigned int du_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(1, 27),
};
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
@ -1545,6 +1626,90 @@ static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_pins[] = {
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
};
static const unsigned int vin4_data18_mux[] = {
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_pins = {
.data24 = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
},
};
static const union vin_data vin4_data_mux = {
.data24 = {
VI4_DATA0_MARK, VI4_DATA1_MARK,
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
/* FIELD */
RCAR_GP_PIN(2, 27),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
/* CLKENB */
RCAR_GP_PIN(2, 28),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(2, 0),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a),
SH_PFC_PIN_GROUP(audio_clk_b),
@ -1553,7 +1718,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
SH_PFC_PIN_GROUP(avb0_mdc),
SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb0_mdio),
SH_PFC_PIN_GROUP(avb0_mii),
SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
SH_PFC_PIN_GROUP(avb0_avtp_match_a),
@ -1568,6 +1734,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_in_1),
SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(du_disp_cde),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2_a),
@ -1622,6 +1796,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
SH_PFC_PIN_GROUP(ssi4_data_b),
SH_PFC_PIN_GROUP(usb0),
VIN_DATA_PIN_GROUP(vin4_data, 8),
VIN_DATA_PIN_GROUP(vin4_data, 10),
VIN_DATA_PIN_GROUP(vin4_data, 12),
VIN_DATA_PIN_GROUP(vin4_data, 16),
SH_PFC_PIN_GROUP(vin4_data18),
VIN_DATA_PIN_GROUP(vin4_data, 20),
VIN_DATA_PIN_GROUP(vin4_data, 24),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
};
static const char * const audio_clk_groups[] = {
@ -1635,7 +1820,8 @@ static const char * const avb0_groups[] = {
"avb0_link",
"avb0_magic",
"avb0_phy_int",
"avb0_mdc",
"avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
"avb0_mdio",
"avb0_mii",
"avb0_avtp_pps_a",
"avb0_avtp_match_a",
@ -1664,6 +1850,17 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
"du_clk_in_1",
"du_clk_out_0",
"du_sync",
"du_disp_cde",
"du_cde",
"du_disp",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
@ -1771,6 +1968,20 @@ static const char * const usb0_groups[] = {
"usb0",
};
static const char * const vin4_groups[] = {
"vin4_data8",
"vin4_data10",
"vin4_data12",
"vin4_data16",
"vin4_data18",
"vin4_data20",
"vin4_data24",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb0),
@ -1779,6 +1990,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
@ -1797,6 +2009,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(vin4),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

2
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -75,7 +75,7 @@ static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
seq_printf(s, "%s", DRV_NAME);
seq_puts(s, DRV_NAME);
}
#ifdef CONFIG_OF

15
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -39,13 +39,14 @@ struct sh_pfc_pin {
unsigned int configs;
};
#define SH_PFC_PIN_GROUP(n) \
#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
{ \
.name = #n, \
.name = #alias, \
.pins = n##_pins, \
.mux = n##_mux, \
.nr_pins = ARRAY_SIZE(n##_pins), \
}
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
struct sh_pfc_pin_group {
const char *name;
@ -283,7 +284,9 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
@ -470,9 +473,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
PORT_GP_CFG_25(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)

12
drivers/pinctrl/stm32/Kconfig
View File

@ -11,37 +11,37 @@ config PINCTRL_STM32
config PINCTRL_STM32F429
bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
depends on OF
depends on OF && HAS_IOMEM
default MACH_STM32F429
select PINCTRL_STM32
config PINCTRL_STM32F469
bool "STMicroelectronics STM32F469 pin control" if COMPILE_TEST && !MACH_STM32F469
depends on OF
depends on OF && HAS_IOMEM
default MACH_STM32F469
select PINCTRL_STM32
config PINCTRL_STM32F746
bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST && !MACH_STM32F746
depends on OF
depends on OF && HAS_IOMEM
default MACH_STM32F746
select PINCTRL_STM32
config PINCTRL_STM32F769
bool "STMicroelectronics STM32F769 pin control" if COMPILE_TEST && !MACH_STM32F769
depends on OF
depends on OF && HAS_IOMEM
default MACH_STM32F769
select PINCTRL_STM32
config PINCTRL_STM32H743
bool "STMicroelectronics STM32H743 pin control" if COMPILE_TEST && !MACH_STM32H743
depends on OF
depends on OF && HAS_IOMEM
default MACH_STM32H743
select PINCTRL_STM32
config PINCTRL_STM32MP157
bool "STMicroelectronics STM32MP157 pin control" if COMPILE_TEST && !MACH_STM32MP157
depends on OF
depends on OF && HAS_IOMEM
default MACH_STM32MP157
select PINCTRL_STM32
endif

3
drivers/pinctrl/stm32/pinctrl-stm32.c
View File

@ -268,10 +268,11 @@ static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
static struct irq_chip stm32_gpio_irq_chip = {
.name = "stm32gpio",
.irq_eoi = irq_chip_eoi_parent,
.irq_ack = irq_chip_ack_parent,
.irq_mask = irq_chip_mask_parent,
.irq_unmask = irq_chip_unmask_parent,
.irq_set_type = irq_chip_set_type_parent,
.irq_set_wake = irq_chip_set_wake_parent,
.irq_request_resources = stm32_gpio_irq_request_resources,
.irq_release_resources = stm32_gpio_irq_release_resources,
};

4
drivers/pinctrl/sunxi/Kconfig
View File

@ -77,4 +77,8 @@ config PINCTRL_SUN50I_H5
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
config PINCTRL_SUN50I_H6
def_bool ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
endif

1
drivers/pinctrl/sunxi/Makefile
View File

@ -18,5 +18,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o

614
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c Normal file
View File

@ -0,0 +1,614 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Allwinner H6 SoC pinctrl driver.
*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin h6_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x2, "emac")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x2, "emac")), /* EMDIO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x2, "ccir"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x2, "ccir"), /* DE */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x2, "ccir"), /* HSYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x2, "ccir"), /* VSYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x2, "ccir"), /* DO0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x2, "ccir"), /* DO1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x2, "ccir"), /* DO2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x2, "ccir"), /* DO3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x2, "ccir"), /* DO4 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x2, "ccir"), /* DO5 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x2, "ccir"), /* DO6 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x2, "ccir"), /* DO7 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x2, "i2s3"), /* SYNC */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
SUNXI_FUNCTION(0x2, "i2s3"), /* DOUT */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
SUNXI_FUNCTION(0x2, "i2s3"), /* DIN */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
SUNXI_FUNCTION(0x2, "i2s3"), /* MCLK */
SUNXI_FUNCTION(0x4, "h_i2s3"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
SUNXI_FUNCTION(0x2, "pwm1"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* WE */
SUNXI_FUNCTION(0x4, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
SUNXI_FUNCTION(0x3, "mmc2")), /* DS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RE */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
SUNXI_FUNCTION(0x4, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
SUNXI_FUNCTION(0x4, "spi0")), /* WP */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
SUNXI_FUNCTION(0x4, "csi"), /* PCLK */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
SUNXI_FUNCTION(0x4, "csi"), /* MCLK */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
SUNXI_FUNCTION(0x4, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "ts0"), /* DVLD */
SUNXI_FUNCTION(0x4, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x5, "emac")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
SUNXI_FUNCTION(0x4, "csi"), /* D0 */
SUNXI_FUNCTION(0x5, "emac")), /* ERXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
SUNXI_FUNCTION(0x4, "csi"), /* D1 */
SUNXI_FUNCTION(0x5, "emac")), /* ERXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
SUNXI_FUNCTION(0x4, "csi"), /* D2 */
SUNXI_FUNCTION(0x5, "emac")), /* ENULL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
SUNXI_FUNCTION(0x4, "csi"), /* D3 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
SUNXI_FUNCTION(0x4, "csi"), /* D4 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
SUNXI_FUNCTION(0x4, "csi"), /* D5 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
SUNXI_FUNCTION(0x4, "csi"), /* D6 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
SUNXI_FUNCTION(0x4, "csi"), /* D7 */
SUNXI_FUNCTION(0x5, "emac")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "ts1"), /* CLK */
SUNXI_FUNCTION(0x4, "csi"), /* SCK */
SUNXI_FUNCTION(0x5, "emac")), /* ETXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "ts1"), /* ERR */
SUNXI_FUNCTION(0x4, "csi"), /* SDA */
SUNXI_FUNCTION(0x5, "emac")), /* ECLKIN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "ts1"), /* SYNC */
SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
SUNXI_FUNCTION(0x5, "csi")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "ts1"), /* DVLD */
SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */
SUNXI_FUNCTION(0x5, "csi")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "ts1"), /* D0 */
SUNXI_FUNCTION(0x4, "dmic")), /* DATA1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "ts2"), /* CLK */
SUNXI_FUNCTION(0x4, "dmic")), /* DATA2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "ts2"), /* ERR */
SUNXI_FUNCTION(0x4, "dmic")), /* DATA3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "ts2"), /* SYNC */
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
SUNXI_FUNCTION(0x5, "emac")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "ts2"), /* DVLD */
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
SUNXI_FUNCTION(0x5, "emac")), /* EMDIO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "ts2"), /* D0 */
SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
SUNXI_FUNCTION(0x3, "ts3"), /* CLK */
SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x3, "ts3"), /* ERR */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION(0x5, "jtag")), /* MS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x3, "ts3"), /* SYNC */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION(0x5, "jtag")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x3, "ts3"), /* DVLD */
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION(0x5, "jtag")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x3, "ts3"), /* D0 */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION(0x5, "jtag")), /* DI */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* SYNC */
SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* CLK */
SUNXI_FUNCTION(0x4, "sim0"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* DOUT */
SUNXI_FUNCTION(0x4, "sim0"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* DIN */
SUNXI_FUNCTION(0x4, "sim0"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
SUNXI_FUNCTION(0x3, "h_i2s2"), /* MCLK */
SUNXI_FUNCTION(0x4, "sim0"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* SYNC */
SUNXI_FUNCTION(0x5, "sim1"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* RX */
SUNXI_FUNCTION(0x3, "i2s0"), /* CLK */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* CLK */
SUNXI_FUNCTION(0x5, "sim1"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir_tx"),
SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT */
SUNXI_FUNCTION(0x5, "sim1"), /* PWREN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS */
SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN */
SUNXI_FUNCTION(0x5, "sim1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x4, "h_i2s0"), /* MCLK */
SUNXI_FUNCTION(0x5, "sim1"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */
SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x5, "sim1"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "spdif"), /* IN */
SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x5, "sim1"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */
};
static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
.pins = h6_pins,
.npins = ARRAY_SIZE(h6_pins),
.irq_banks = 3,
.irq_bank_map = h6_irq_bank_map,
.irq_read_needs_mux = true,
};
static int h6_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&h6_pinctrl_data);
}
static const struct of_device_id h6_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-h6-pinctrl", },
{}
};
static struct platform_driver h6_pinctrl_driver = {
.probe = h6_pinctrl_probe,
.driver = {
.name = "sun50i-h6-pinctrl",
.of_match_table = h6_pinctrl_match,
},
};
builtin_platform_driver(h6_pinctrl_driver);

4
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
View File

@ -481,11 +481,13 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = {
SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
};
static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 };
static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
.pins = sun8i_a33_pins,
.npins = ARRAY_SIZE(sun8i_a33_pins),
.irq_banks = 2,
.irq_bank_base = 1,
.irq_bank_map = sun8i_a33_pinctrl_irq_bank_map,
.disable_strict_mode = true,
};

4
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
View File

@ -293,11 +293,13 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
};
static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 };
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
.irq_bank_base = 1,
.irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map,
.irq_read_needs_mux = true
};

25
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -835,7 +835,7 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
u8 index = sunxi_irq_cfg_offset(d->hwirq);
unsigned long flags;
u32 regval;
@ -882,8 +882,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
static void sunxi_pinctrl_irq_ack(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 status_reg = sunxi_irq_status_reg(d->hwirq,
pctl->desc->irq_bank_base);
u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
/* Clear the IRQ */
@ -893,7 +892,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d)
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
@ -910,7 +909,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
unsigned long flags;
u32 val;
@ -1002,7 +1001,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
if (bank == pctl->desc->irq_banks)
return;
reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
if (val) {
@ -1234,8 +1233,7 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
writel(src | div << 4,
pctl->membase +
sunxi_irq_debounce_reg_from_bank(i,
pctl->desc->irq_bank_base));
sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
}
return 0;
@ -1363,7 +1361,8 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
goto gpiochip_error;
}
clk = devm_clk_get(&pdev->dev, NULL);
ret = of_count_phandle_with_args(node, "clocks", "#clock-cells");
clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto gpiochip_error;
@ -1410,11 +1409,11 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
for (i = 0; i < pctl->desc->irq_banks; i++) {
/* Mask and clear all IRQs before registering a handler */
writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
pctl->desc->irq_bank_base));
writel(0, pctl->membase +
sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
writel(0xffffffff,
pctl->membase + sunxi_irq_status_reg_from_bank(i,
pctl->desc->irq_bank_base));
pctl->membase +
sunxi_irq_status_reg_from_bank(pctl->desc, i));
irq_set_chained_handler_and_data(pctl->irq[i],
sunxi_pinctrl_irq_handler,

40
drivers/pinctrl/sunxi/pinctrl-sunxi.h
View File

@ -110,7 +110,7 @@ struct sunxi_pinctrl_desc {
int npins;
unsigned pin_base;
unsigned irq_banks;
unsigned irq_bank_base;
const unsigned int *irq_bank_map;
bool irq_read_needs_mux;
bool disable_strict_mode;
};
@ -263,12 +263,22 @@ static inline u32 sunxi_pull_offset(u16 pin)
return pin_num * PULL_PINS_BITS;
}
static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base)
static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
if (!desc->irq_bank_map)
return bank;
else
return desc->irq_bank_map[bank];
}
static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
u16 irq)
{
u8 bank = irq / IRQ_PER_BANK;
u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg;
return IRQ_CFG_REG +
sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
}
static inline u32 sunxi_irq_cfg_offset(u16 irq)
@ -277,16 +287,17 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
return irq_num * IRQ_CFG_IRQ_BITS;
}
static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base)
static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE;
return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}
static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base)
static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
u16 irq)
{
u8 bank = irq / IRQ_PER_BANK;
return sunxi_irq_ctrl_reg_from_bank(bank, bank_base);
return sunxi_irq_ctrl_reg_from_bank(desc, bank);
}
static inline u32 sunxi_irq_ctrl_offset(u16 irq)
@ -295,21 +306,24 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
return irq_num * IRQ_CTRL_IRQ_BITS;
}
static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base)
static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE;
return IRQ_DEBOUNCE_REG +
sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}
static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base)
static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE;
return IRQ_STATUS_REG +
sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}
static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base)
static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
u16 irq)
{
u8 bank = irq / IRQ_PER_BANK;
return sunxi_irq_status_reg_from_bank(bank, bank_base);
return sunxi_irq_status_reg_from_bank(desc, bank);
}
static inline u32 sunxi_irq_status_offset(u16 irq)

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
View File

@ -470,8 +470,10 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = {
166, UNIPHIER_PIN_PULL_DOWN),
};
static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142};
static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
static const unsigned aoutiec1_pins[] = {135, 136};
static const int aoutiec1_muxvals[] = {0, 0};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@ -504,6 +506,8 @@ static const unsigned uart2_pins[] = {90, 91};
static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {94, 95};
static const int uart3_muxvals[] = {1, 1};
static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101};
static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1};
static const unsigned usb0_pins[] = {46, 47};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {48, 49};
@ -547,7 +551,8 @@ static const unsigned int gpio_range5_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(aout),
UNIPHIER_PINCTRL_GROUP(aout1),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rmii),
@ -562,6 +567,7 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@ -573,7 +579,8 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5),
};
static const char * const aout_groups[] = {"aout"};
static const char * const aout1_groups[] = {"aout1"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const i2c0_groups[] = {"i2c0"};
@ -586,13 +593,14 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
static const struct uniphier_pinmux_function uniphier_ld11_functions[] = {
UNIPHIER_PINMUX_FUNCTION(aout),
UNIPHIER_PINMUX_FUNCTION(aout1),
UNIPHIER_PINMUX_FUNCTION(aoutiec1),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
View File

@ -551,8 +551,10 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = {
175, UNIPHIER_PIN_PULL_DOWN),
};
static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142};
static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
static const unsigned aoutiec1_pins[] = {135, 136};
static const int aoutiec1_muxvals[] = {0, 0};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@ -591,6 +593,8 @@ static const unsigned uart2_pins[] = {90, 91};
static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {94, 95};
static const int uart3_muxvals[] = {1, 1};
static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101};
static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1};
static const unsigned usb0_pins[] = {46, 47};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {48, 49};
@ -631,7 +635,8 @@ static const unsigned int gpio_range2_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(aout),
UNIPHIER_PINCTRL_GROUP(aout1),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rgmii),
@ -648,6 +653,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@ -657,7 +663,8 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
static const char * const aout_groups[] = {"aout"};
static const char * const aout1_groups[] = {"aout1"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
@ -672,14 +679,15 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
UNIPHIER_PINMUX_FUNCTION(aout),
UNIPHIER_PINMUX_FUNCTION(aout1),
UNIPHIER_PINMUX_FUNCTION(aoutiec1),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),

5
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
View File

@ -590,6 +590,8 @@ static const unsigned system_bus_cs3_pins[] = {156};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned uart0_pins[] = {85, 88};
static const int uart0_muxvals[] = {1, 1};
static const unsigned uart0_ctsrts_pins[] = {86, 87, 89};
static const int uart0_ctsrts_muxvals[] = {1, 1, 1};
static const unsigned uart1_pins[] = {155, 156};
static const int uart1_muxvals[] = {13, 13};
static const unsigned uart1b_pins[] = {69, 70};
@ -644,6 +646,7 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart1b),
UNIPHIER_PINCTRL_GROUP(uart2),
@ -669,7 +672,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1",
"system_bus_cs2",
"system_bus_cs3"};
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};

5
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
View File

@ -785,6 +785,8 @@ static const unsigned system_bus_cs5_pins[] = {55};
static const int system_bus_cs5_muxvals[] = {6};
static const unsigned uart0_pins[] = {135, 136};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart0_ctsrts_pins[] = {137, 138, 139, 140, 141, 124};
static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned uart0b_pins[] = {11, 12};
static const int uart0b_muxvals[] = {2, 2};
static const unsigned uart1_pins[] = {115, 116};
@ -856,6 +858,7 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart1b),
@ -885,7 +888,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs3",
"system_bus_cs4",
"system_bus_cs5"};
static const char * const uart0_groups[] = {"uart0", "uart0b"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", "uart0b"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2", "uart2b"};
static const char * const usb0_groups[] = {"usb0"};

5
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
View File

@ -1078,6 +1078,8 @@ static const unsigned uart2_pins[] = {131, 132};
static const int uart2_muxvals[] = {0, 0};
static const unsigned uart3_pins[] = {88, 89};
static const int uart3_muxvals[] = {2, 2};
static const unsigned uart3_ctsrts_pins[] = {80, 81, 82, 83, 90, 91};
static const int uart3_ctsrts_muxvals[] = {2, 2, 2, 2, 2, 2};
static const unsigned usb0_pins[] = {180, 181};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {182, 183};
@ -1149,6 +1151,7 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@ -1180,7 +1183,7 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};

5
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
View File

@ -842,6 +842,8 @@ static const unsigned uart0_pins[] = {47, 48};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart0b_pins[] = {227, 228};
static const int uart0b_muxvals[] = {3, 3};
static const unsigned uart0b_ctsrts_pins[] = {229, 230, 231, 232, 233, 234};
static const int uart0b_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned uart1_pins[] = {49, 50};
static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {51, 52};
@ -913,6 +915,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -940,7 +943,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs5",
"system_bus_cs6",
"system_bus_cs7"};
static const char * const uart0_groups[] = {"uart0", "uart0b"};
static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};

40
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
View File

@ -728,6 +728,20 @@ static const struct pinctrl_pin_desc uniphier_pxs2_pins[] = {
234, UNIPHIER_PIN_PULL_DOWN),
};
static const unsigned ain1_pins[] = {161, 162, 173, 174};
static const int ain1_muxvals[] = {8, 8, 8, 8};
static const unsigned ain2_pins[] = {98, 99, 100, 101, 102, 103, 104};
static const int ain2_muxvals[] = {8, 8, 8, 8, 8, 8, 8};
static const unsigned ainiec1_pins[] = {91};
static const int ainiec1_muxvals[] = {11};
static const unsigned aout2_pins[] = {175, 176, 177, 178, 183, 184, 185};
static const int aout2_muxvals[] = {8, 8, 8, 8, 9, 9, 9};
static const unsigned aout3_pins[] = {105, 106, 107, 108};
static const int aout3_muxvals[] = {8, 8, 8, 8};
static const unsigned aoutiec1_pins[] = {95};
static const int aoutiec1_muxvals[] = {11};
static const unsigned aoutiec2_pins[] = {97};
static const int aoutiec2_muxvals[] = {8};
static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
@ -774,6 +788,8 @@ static const unsigned uart0_pins[] = {217, 218};
static const int uart0_muxvals[] = {8, 8};
static const unsigned uart0b_pins[] = {179, 180};
static const int uart0b_muxvals[] = {10, 10};
static const unsigned uart0b_ctsrts_pins[] = {176, 177, 178, 183, 184, 185};
static const int uart0b_ctsrts_muxvals[] = {10, 10, 10, 10, 10, 10};
static const unsigned uart1_pins[] = {115, 116};
static const int uart1_muxvals[] = {8, 8};
static const unsigned uart2_pins[] = {113, 114};
@ -824,6 +840,13 @@ static const unsigned int gpio_range1_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP(ain1),
UNIPHIER_PINCTRL_GROUP(ain2),
UNIPHIER_PINCTRL_GROUP(ainiec1),
UNIPHIER_PINCTRL_GROUP(aout2),
UNIPHIER_PINCTRL_GROUP(aout3),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_mii),
@ -842,6 +865,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -854,6 +878,13 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1),
};
static const char * const ain1_groups[] = {"ain1"};
static const char * const ain2_groups[] = {"ain2"};
static const char * const ainiec1_groups[] = {"ainiec1"};
static const char * const aout2_groups[] = {"aout2"};
static const char * const aout3_groups[] = {"aout3"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_mii_groups[] = {"ether_mii"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
@ -868,7 +899,7 @@ static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0", "uart0b"};
static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3", "uart3b"};
@ -878,6 +909,13 @@ static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = {
UNIPHIER_PINMUX_FUNCTION(ain1),
UNIPHIER_PINMUX_FUNCTION(ain2),
UNIPHIER_PINMUX_FUNCTION(ainiec1),
UNIPHIER_PINMUX_FUNCTION(aout2),
UNIPHIER_PINMUX_FUNCTION(aout3),
UNIPHIER_PINMUX_FUNCTION(aoutiec1),
UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_mii),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),

5
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
View File

@ -816,6 +816,8 @@ static const unsigned int system_bus_cs1_pins[] = {15};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned int uart0_pins[] = {92, 93};
static const int uart0_muxvals[] = {0, 0};
static const unsigned int uart0_ctsrts_pins[] = {243, 244, 245, 246, 247, 248};
static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned int uart1_pins[] = {94, 95};
static const int uart1_muxvals[] = {0, 0};
static const unsigned int uart2_pins[] = {96, 97};
@ -887,6 +889,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -912,7 +915,7 @@ static const char * const nand_groups[] = {"nand"};
static const char * const sd_groups[] = {"sd"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};

5
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
View File

@ -520,6 +520,8 @@ static const unsigned system_bus_cs5_pins[] = {13};
static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {70, 71};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart0_ctsrts_pins[] = {72, 73, 74};
static const int uart0_ctsrts_muxvals[] = {3, 3, 3};
static const unsigned uart1_pins[] = {114, 115};
static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {112, 113};
@ -575,6 +577,7 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -601,7 +604,7 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs3",
"system_bus_cs4",
"system_bus_cs5"};
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};

119
include/dt-bindings/gpio/meson8b-gpio.h
View File

@ -15,18 +15,113 @@
#ifndef _DT_BINDINGS_MESON8B_GPIO_H
#define _DT_BINDINGS_MESON8B_GPIO_H
#include <dt-bindings/gpio/meson8-gpio.h>
/* EE (CBUS) GPIO chip */
#define GPIOX_0 0
#define GPIOX_1 1
#define GPIOX_2 2
#define GPIOX_3 3
#define GPIOX_4 4
#define GPIOX_5 5
#define GPIOX_6 6
#define GPIOX_7 7
#define GPIOX_8 8
#define GPIOX_9 9
#define GPIOX_10 10
#define GPIOX_11 11
#define GPIOX_16 12
#define GPIOX_17 13
#define GPIOX_18 14
#define GPIOX_19 15
#define GPIOX_20 16
#define GPIOX_21 17
/* GPIO Bank DIF */
#define DIF_0_P 120
#define DIF_0_N 121
#define DIF_1_P 122
#define DIF_1_N 123
#define DIF_2_P 124
#define DIF_2_N 125
#define DIF_3_P 126
#define DIF_3_N 127
#define DIF_4_P 128
#define DIF_4_N 129
#define GPIOY_0 18
#define GPIOY_1 19
#define GPIOY_3 20
#define GPIOY_6 21
#define GPIOY_7 22
#define GPIOY_8 23
#define GPIOY_9 24
#define GPIOY_10 25
#define GPIOY_11 26
#define GPIOY_12 27
#define GPIOY_13 28
#define GPIOY_14 29
#define GPIODV_9 30
#define GPIODV_24 31
#define GPIODV_25 32
#define GPIODV_26 33
#define GPIODV_27 34
#define GPIODV_28 35
#define GPIODV_29 36
#define GPIOH_0 37
#define GPIOH_1 38
#define GPIOH_2 39
#define GPIOH_3 40
#define GPIOH_4 41
#define GPIOH_5 42
#define GPIOH_6 43
#define GPIOH_7 44
#define GPIOH_8 45
#define GPIOH_9 46
#define CARD_0 47
#define CARD_1 48
#define CARD_2 49
#define CARD_3 50
#define CARD_4 51
#define CARD_5 52
#define CARD_6 53
#define BOOT_0 54
#define BOOT_1 55
#define BOOT_2 56
#define BOOT_3 57
#define BOOT_4 58
#define BOOT_5 59
#define BOOT_6 60
#define BOOT_7 61
#define BOOT_8 62
#define BOOT_9 63
#define BOOT_10 64
#define BOOT_11 65
#define BOOT_12 66
#define BOOT_13 67
#define BOOT_14 68
#define BOOT_15 69
#define BOOT_16 70
#define BOOT_17 71
#define BOOT_18 72
#define DIF_0_P 73
#define DIF_0_N 74
#define DIF_1_P 75
#define DIF_1_N 76
#define DIF_2_P 77
#define DIF_2_N 78
#define DIF_3_P 79
#define DIF_3_N 80
#define DIF_4_P 81
#define DIF_4_N 82
/* AO GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_BSD_EN 14
#define GPIO_TEST_N 15
#endif /* _DT_BINDINGS_MESON8B_GPIO_H */

24
include/dt-bindings/pinctrl/mt7623-pinfunc.h
View File

@ -251,6 +251,12 @@
#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
#define MT7623_PIN_77_SDA2_FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
#define MT7623_PIN_77_SDA2_FUNC_SDA2 (MTK_PIN_NO(77) | 1)
#define MT7623_PIN_78_SCL2_FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
#define MT7623_PIN_78_SCL2_FUNC_SCL2 (MTK_PIN_NO(78) | 1)
#define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
#define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1)
#define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
@ -291,6 +297,24 @@
#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1)
#define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
#define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3)
#define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
#define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3)
#define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
#define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3)
#define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
#define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3)