MIPS: Netlogic: Support for multi-chip configuration
Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a coherent multi-node system. Each SoC has its own set of on-chip devices including PIC. To support this, add a per SoC stucture and use it for the PIC and SYS block addresses instead of using global variables. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4469 Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jayachandran C
John Crispin
parent
2a37b1ae44
commit
77ae798f5b
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@ -46,10 +46,10 @@
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#ifndef __ASSEMBLY__
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#include <linux/cpumask.h>
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#include <linux/spinlock.h>
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#include <asm/irq.h>
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struct irq_desc;
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extern struct plat_smp_ops nlm_smp_ops;
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extern char nlm_reset_entry[], nlm_reset_entry_end[];
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void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_irq_init(void);
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@ -70,10 +70,42 @@ nlm_set_nmi_handler(void *handler)
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* Misc.
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*/
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unsigned int nlm_get_cpu_frequency(void);
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void nlm_node_init(int node);
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extern struct plat_smp_ops nlm_smp_ops;
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extern char nlm_reset_entry[], nlm_reset_entry_end[];
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extern unsigned long nlm_common_ebase;
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extern int nlm_threads_per_core;
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extern uint32_t nlm_coremask;
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extern unsigned int nlm_threads_per_core;
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extern cpumask_t nlm_cpumask;
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struct nlm_soc_info {
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unsigned long coremask; /* cores enabled on the soc */
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unsigned long ebase;
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uint64_t irqmask;
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uint64_t sysbase; /* only for XLP */
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uint64_t picbase;
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spinlock_t piclock;
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};
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#define NLM_CORES_PER_NODE 8
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#define NLM_THREADS_PER_CORE 4
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#define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE)
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#define nlm_get_node(i) (&nlm_nodes[i])
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#define NLM_NR_NODES 1
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#define nlm_current_node() (&nlm_nodes[0])
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struct irq_data;
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uint64_t nlm_pci_irqmask(int node);
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void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
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/*
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* The NR_IRQs is divided between nodes, each of them has a separate irq space
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*/
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static inline int nlm_irq_to_xirq(int node, int irq)
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{
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return node * NR_IRQS / NLM_NR_NODES + irq;
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}
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extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
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extern int nlm_cpu_ready[];
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#endif
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#endif /* _NETLOGIC_COMMON_H_ */
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@ -73,4 +73,9 @@ static inline int hard_smp_processor_id(void)
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return __read_32bit_c0_register($15, 1) & 0x3ff;
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}
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static inline int nlm_nodeid(void)
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{
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return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
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}
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#endif /*_ASM_NLM_MIPS_EXTS_H */
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@ -381,7 +381,6 @@ nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
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nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt);
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}
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extern uint64_t nlm_pic_base;
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int nlm_irq_to_irt(int irq);
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int nlm_irt_to_irq(int irt);
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@ -124,6 +124,5 @@
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#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
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#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
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extern uint64_t nlm_sys_base;
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#endif
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#endif
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@ -258,7 +258,5 @@ nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
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nlm_write_reg(base, PIC_IRT_1(irt),
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(1 << 30) | (1 << 6) | irq);
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}
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extern uint64_t nlm_pic_base;
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#endif
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#endif /* _ASM_NLM_XLR_PIC_H */
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@ -70,33 +70,34 @@
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*/
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/* Globals */
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static uint64_t nlm_irq_mask;
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static DEFINE_SPINLOCK(nlm_pic_lock);
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static void xlp_pic_enable(struct irq_data *d)
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{
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unsigned long flags;
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struct nlm_soc_info *nodep;
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int irt;
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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spin_lock_irqsave(&nlm_pic_lock, flags);
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nlm_pic_enable_irt(nlm_pic_base, irt);
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spin_unlock_irqrestore(&nlm_pic_lock, flags);
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spin_lock_irqsave(&nodep->piclock, flags);
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nlm_pic_enable_irt(nodep->picbase, irt);
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spin_unlock_irqrestore(&nodep->piclock, flags);
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}
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static void xlp_pic_disable(struct irq_data *d)
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{
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struct nlm_soc_info *nodep;
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unsigned long flags;
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int irt;
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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spin_lock_irqsave(&nlm_pic_lock, flags);
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nlm_pic_disable_irt(nlm_pic_base, irt);
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spin_unlock_irqrestore(&nlm_pic_lock, flags);
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spin_lock_irqsave(&nodep->piclock, flags);
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nlm_pic_disable_irt(nodep->picbase, irt);
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spin_unlock_irqrestore(&nodep->piclock, flags);
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}
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static void xlp_pic_mask_ack(struct irq_data *d)
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@ -109,8 +110,10 @@ static void xlp_pic_mask_ack(struct irq_data *d)
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static void xlp_pic_unmask(struct irq_data *d)
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{
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void *hd = irq_data_get_irq_handler_data(d);
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struct nlm_soc_info *nodep;
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int irt;
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nodep = nlm_current_node();
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irt = nlm_irq_to_irt(d->irq);
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if (irt == -1)
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return;
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@ -120,7 +123,7 @@ static void xlp_pic_unmask(struct irq_data *d)
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extra_ack(d);
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}
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/* Ack is a single write, no need to lock */
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nlm_pic_ack(nlm_pic_base, irt);
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nlm_pic_ack(nodep->picbase, irt);
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}
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static struct irq_chip xlp_pic = {
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@ -177,7 +180,11 @@ struct irq_chip nlm_cpu_intr = {
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void __init init_nlm_common_irqs(void)
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{
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int i, irq, irt;
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uint64_t irqmask;
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struct nlm_soc_info *nodep;
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nodep = nlm_current_node();
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irqmask = (1ULL << IRQ_TIMER);
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for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
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irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
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@ -189,7 +196,7 @@ void __init init_nlm_common_irqs(void)
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nlm_smp_function_ipi_handler);
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irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
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nlm_smp_resched_ipi_handler);
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nlm_irq_mask |=
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irqmask |=
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((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
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#endif
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@ -197,11 +204,11 @@ void __init init_nlm_common_irqs(void)
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irt = nlm_irq_to_irt(irq);
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if (irt == -1)
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continue;
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nlm_irq_mask |= (1ULL << irq);
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nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
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irqmask |= (1ULL << irq);
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nlm_pic_init_irt(nodep->picbase, irt, irq, 0);
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}
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nlm_irq_mask |= (1ULL << IRQ_TIMER);
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nodep->irqmask = irqmask;
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}
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void __init arch_init_irq(void)
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@ -209,29 +216,39 @@ void __init arch_init_irq(void)
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/* Initialize the irq descriptors */
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init_nlm_common_irqs();
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write_c0_eimr(nlm_irq_mask);
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write_c0_eimr(nlm_current_node()->irqmask);
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}
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void __cpuinit nlm_smp_irq_init(void)
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{
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/* set interrupt mask for non-zero cpus */
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write_c0_eimr(nlm_irq_mask);
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write_c0_eimr(nlm_current_node()->irqmask);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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uint64_t eirr;
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int i;
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int i, node;
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node = nlm_nodeid();
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eirr = read_c0_eirr() & read_c0_eimr();
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if (eirr & (1 << IRQ_TIMER)) {
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do_IRQ(IRQ_TIMER);
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return;
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}
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#ifdef CONFIG_SMP
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if (eirr & IRQ_IPI_SMP_FUNCTION) {
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do_IRQ(IRQ_IPI_SMP_FUNCTION);
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return;
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}
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if (eirr & IRQ_IPI_SMP_RESCHEDULE) {
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do_IRQ(IRQ_IPI_SMP_RESCHEDULE);
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return;
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}
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#endif
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i = __ilog2_u64(eirr);
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if (i == -1)
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return;
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do_IRQ(i);
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do_IRQ(nlm_irq_to_xirq(node, i));
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}
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@ -59,12 +59,17 @@
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void nlm_send_ipi_single(int logical_cpu, unsigned int action)
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{
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int cpu = cpu_logical_map(logical_cpu);
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int cpu, node;
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uint64_t picbase;
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cpu = cpu_logical_map(logical_cpu);
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node = cpu / NLM_CPUS_PER_NODE;
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picbase = nlm_get_node(node)->picbase;
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if (action & SMP_CALL_FUNCTION)
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nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
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nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_FUNCTION, 0);
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if (action & SMP_RESCHEDULE_YOURSELF)
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nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
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nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
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}
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void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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@ -96,11 +101,12 @@ void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
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void nlm_early_init_secondary(int cpu)
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{
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change_c0_config(CONF_CM_CMASK, 0x3);
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write_c0_ebase((uint32_t)nlm_common_ebase);
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#ifdef CONFIG_CPU_XLP
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if (cpu % 4 == 0)
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/* mmu init, once per core */
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if (cpu % NLM_THREADS_PER_CORE == 0)
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xlp_mmu_init();
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#endif
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write_c0_ebase(nlm_current_node()->ebase);
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}
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/*
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@ -108,7 +114,7 @@ void nlm_early_init_secondary(int cpu)
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*/
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static void __cpuinit nlm_init_secondary(void)
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{
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current_cpu_data.core = hard_smp_processor_id() / 4;
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current_cpu_data.core = hard_smp_processor_id() / NLM_THREADS_PER_CORE;
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nlm_smp_irq_init();
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}
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@ -142,22 +148,22 @@ cpumask_t phys_cpu_present_map;
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void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
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{
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unsigned long gp = (unsigned long)task_thread_info(idle);
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unsigned long sp = (unsigned long)__KSTK_TOS(idle);
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int cpu = cpu_logical_map(logical_cpu);
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int cpu, node;
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nlm_next_sp = sp;
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nlm_next_gp = gp;
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cpu = cpu_logical_map(logical_cpu);
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node = cpu / NLM_CPUS_PER_NODE;
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nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
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nlm_next_gp = (unsigned long)task_thread_info(idle);
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/* barrier */
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/* barrier for sp/gp store above */
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__sync();
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nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);
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nlm_pic_send_ipi(nlm_get_node(node)->picbase, cpu, 1, 1); /* NMI */
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}
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void __init nlm_smp_setup(void)
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{
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unsigned int boot_cpu;
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int num_cpus, i;
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int num_cpus, i, ncore;
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boot_cpu = hard_smp_processor_id();
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cpumask_clear(&phys_cpu_present_map);
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@ -182,11 +188,16 @@ void __init nlm_smp_setup(void)
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}
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}
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/* check with the cores we have worken up */
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for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
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ncore += hweight32(nlm_get_node(i)->coremask);
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pr_info("Phys CPU present map: %lx, possible map %lx\n",
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(unsigned long)cpumask_bits(&phys_cpu_present_map)[0],
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(unsigned long)cpumask_bits(cpu_possible_mask)[0]);
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pr_info("Detected %i Slave CPU(s)\n", num_cpus);
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pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
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nlm_threads_per_core, num_cpus);
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nlm_set_nmi_handler(nlm_boot_secondary_cpus);
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}
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@ -196,7 +207,7 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
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int threadmode, i, j;
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core0_thr_mask = 0;
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for (i = 0; i < 4; i++)
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for (i = 0; i < NLM_THREADS_PER_CORE; i++)
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if (cpumask_test_cpu(i, wakeup_mask))
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core0_thr_mask |= (1 << i);
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switch (core0_thr_mask) {
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@ -217,9 +228,9 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
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}
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/* Verify other cores CPU masks */
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for (i = 0; i < NR_CPUS; i += 4) {
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for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) {
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core_thr_mask = 0;
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for (j = 0; j < 4; j++)
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for (j = 0; j < NLM_THREADS_PER_CORE; j++)
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if (cpumask_test_cpu(i + j, wakeup_mask))
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core_thr_mask |= (1 << j);
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if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
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@ -40,23 +40,23 @@
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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/* These addresses are computed by the nlm_hal_init() */
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uint64_t nlm_io_base;
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uint64_t nlm_sys_base;
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uint64_t nlm_pic_base;
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/* Main initialization */
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void nlm_hal_init(void)
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void nlm_node_init(int node)
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{
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nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
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nlm_sys_base = nlm_get_sys_regbase(0); /* node 0 */
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nlm_pic_base = nlm_get_pic_regbase(0); /* node 0 */
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struct nlm_soc_info *nodep;
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nodep = nlm_get_node(node);
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nodep->sysbase = nlm_get_sys_regbase(node);
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nodep->picbase = nlm_get_pic_regbase(node);
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nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
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spin_lock_init(&nodep->piclock);
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}
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int nlm_irq_to_irt(int irq)
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@ -138,14 +138,15 @@ int nlm_irt_to_irq(int irt)
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}
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}
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unsigned int nlm_get_core_frequency(int core)
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unsigned int nlm_get_core_frequency(int node, int core)
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{
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unsigned int pll_divf, pll_divr, dfs_div, ext_div;
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unsigned int rstval, dfsval, denom;
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uint64_t num;
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uint64_t num, sysbase;
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rstval = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
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dfsval = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIV_VALUE);
|
||||
sysbase = nlm_get_node(node)->sysbase;
|
||||
rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
|
||||
dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
|
||||
pll_divf = ((rstval >> 10) & 0x7f) + 1;
|
||||
pll_divr = ((rstval >> 8) & 0x3) + 1;
|
||||
ext_div = ((rstval >> 30) & 0x3) + 1;
|
||||
|
|
@ -159,5 +160,5 @@ unsigned int nlm_get_core_frequency(int core)
|
|||
|
||||
unsigned int nlm_get_cpu_frequency(void)
|
||||
{
|
||||
return nlm_get_core_frequency(0);
|
||||
return nlm_get_core_frequency(0, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,17 +52,17 @@
|
|||
#include <asm/netlogic/xlp-hal/xlp.h>
|
||||
#include <asm/netlogic/xlp-hal/sys.h>
|
||||
|
||||
unsigned long nlm_common_ebase = 0x0;
|
||||
|
||||
/* default to uniprocessor */
|
||||
uint32_t nlm_coremask = 1;
|
||||
uint64_t nlm_io_base;
|
||||
struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
|
||||
cpumask_t nlm_cpumask = CPU_MASK_CPU0;
|
||||
int nlm_threads_per_core = 1;
|
||||
unsigned int nlm_threads_per_core;
|
||||
extern u32 __dtb_start[];
|
||||
|
||||
static void nlm_linux_exit(void)
|
||||
{
|
||||
nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
|
||||
uint64_t sysbase = nlm_get_node(0)->sysbase;
|
||||
|
||||
nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
|
||||
for ( ; ; )
|
||||
cpu_wait();
|
||||
}
|
||||
|
|
@ -110,10 +110,9 @@ void xlp_mmu_init(void)
|
|||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
|
||||
xlp_mmu_init();
|
||||
nlm_hal_init();
|
||||
|
||||
nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
|
||||
nlm_node_init(0);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
cpumask_setall(&nlm_cpumask);
|
||||
|
|
|
|||
|
|
@ -79,32 +79,38 @@ static int xlp_wakeup_core(uint64_t sysbase, int core)
|
|||
|
||||
static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
|
||||
{
|
||||
uint64_t syspcibase, sysbase;
|
||||
struct nlm_soc_info *nodep;
|
||||
uint64_t syspcibase;
|
||||
uint32_t syscoremask;
|
||||
int core, n;
|
||||
int core, n, cpu;
|
||||
|
||||
for (n = 0; n < 4; n++) {
|
||||
for (n = 0; n < NLM_NR_NODES; n++) {
|
||||
syspcibase = nlm_get_sys_pcibase(n);
|
||||
if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
|
||||
break;
|
||||
|
||||
/* read cores in reset from SYS and account for boot cpu */
|
||||
sysbase = nlm_get_sys_regbase(n);
|
||||
syscoremask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
|
||||
nlm_node_init(n);
|
||||
nodep = nlm_get_node(n);
|
||||
syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET);
|
||||
if (n == 0)
|
||||
syscoremask |= 1;
|
||||
|
||||
for (core = 0; core < 8; core++) {
|
||||
for (core = 0; core < NLM_CORES_PER_NODE; core++) {
|
||||
/* see if the core exists */
|
||||
if ((syscoremask & (1 << core)) == 0)
|
||||
continue;
|
||||
|
||||
/* see if at least the first thread is enabled */
|
||||
if (!cpumask_test_cpu((n * 8 + core) * 4, wakeup_mask))
|
||||
cpu = (n * NLM_CORES_PER_NODE + core)
|
||||
* NLM_THREADS_PER_CORE;
|
||||
if (!cpumask_test_cpu(cpu, wakeup_mask))
|
||||
continue;
|
||||
|
||||
/* wake up the core */
|
||||
if (!xlp_wakeup_core(sysbase, core))
|
||||
if (xlp_wakeup_core(nodep->sysbase, core))
|
||||
nodep->coremask |= 1u << core;
|
||||
else
|
||||
pr_err("Failed to enable core %d\n", core);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,14 +51,11 @@
|
|||
#include <asm/netlogic/xlr/gpio.h>
|
||||
|
||||
uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
|
||||
uint64_t nlm_pic_base;
|
||||
struct psb_info nlm_prom_info;
|
||||
|
||||
unsigned long nlm_common_ebase = 0x0;
|
||||
|
||||
/* default to uniprocessor */
|
||||
uint32_t nlm_coremask = 1;
|
||||
int nlm_threads_per_core = 1;
|
||||
unsigned int nlm_threads_per_core = 1;
|
||||
struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
|
||||
cpumask_t nlm_cpumask = CPU_MASK_CPU0;
|
||||
|
||||
static void __init nlm_early_serial_setup(void)
|
||||
|
|
@ -177,6 +174,16 @@ static void prom_add_memory(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void nlm_init_node(void)
|
||||
{
|
||||
struct nlm_soc_info *nodep;
|
||||
|
||||
nodep = nlm_current_node();
|
||||
nodep->picbase = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
|
||||
nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
|
||||
spin_lock_init(&nodep->piclock);
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
int i, *argv, *envp; /* passed as 32 bit ptrs */
|
||||
|
|
@ -188,11 +195,10 @@ void __init prom_init(void)
|
|||
prom_infop = (struct psb_info *)(long)(int)fw_arg3;
|
||||
|
||||
nlm_prom_info = *prom_infop;
|
||||
nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
|
||||
nlm_init_node();
|
||||
|
||||
nlm_early_serial_setup();
|
||||
build_arcs_cmdline(argv);
|
||||
nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
|
||||
prom_add_memory();
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/threads.h>
|
||||
|
||||
#include <asm/asm.h>
|
||||
|
|
@ -50,18 +51,34 @@
|
|||
|
||||
int __cpuinit xlr_wakeup_secondary_cpus(void)
|
||||
{
|
||||
unsigned int i, boot_cpu;
|
||||
struct nlm_soc_info *nodep;
|
||||
unsigned int i, j, boot_cpu;
|
||||
|
||||
/*
|
||||
* In case of RMI boot, hit with NMI to get the cores
|
||||
* from bootloader to linux code.
|
||||
*/
|
||||
nodep = nlm_get_node(0);
|
||||
boot_cpu = hard_smp_processor_id();
|
||||
nlm_set_nmi_handler(nlm_rmiboot_preboot);
|
||||
for (i = 0; i < NR_CPUS; i++) {
|
||||
if (i == boot_cpu || !cpumask_test_cpu(i, &nlm_cpumask))
|
||||
continue;
|
||||
nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
|
||||
nlm_pic_send_ipi(nodep->picbase, i, 1, 1); /* send NMI */
|
||||
}
|
||||
|
||||
/* Fill up the coremask early */
|
||||
nodep->coremask = 1;
|
||||
for (i = 1; i < NLM_CORES_PER_NODE; i++) {
|
||||
for (j = 1000000; j > 0; j--) {
|
||||
if (nlm_cpu_ready[i * NLM_THREADS_PER_CORE])
|
||||
break;
|
||||
udelay(10);
|
||||
}
|
||||
if (j != 0)
|
||||
nodep->coremask |= (1u << i);
|
||||
else
|
||||
pr_err("Failed to wakeup core %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue