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[MIPS] IP22: Get rid of volatile in IP22 core code. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2007-04-26 15:46:24 +01:00
parent 2127435e57
commit 78709b9df3
5 changed files with 22 additions and 22 deletions
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24
arch/mips/sgi-ip22/ip22-nvram.c
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@ -52,8 +52,7 @@
* national semiconductor nv ram chip the op code is 3 bits and * national semiconductor nv ram chip the op code is 3 bits and
* the address is 6/8 bits. * the address is 6/8 bits.
*/ */
static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd, static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg)
unsigned reg)
{ {
unsigned short ser_cmd; unsigned short ser_cmd;
int i; int i;
@ -61,33 +60,34 @@ static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
for (i = 0; i < BITS_IN_COMMAND; i++) { for (i = 0; i < BITS_IN_COMMAND; i++) {
if (ser_cmd & (1<<15)) /* if high order bit set */ if (ser_cmd & (1<<15)) /* if high order bit set */
*ctrl |= EEPROM_DATO; writel(readl(ctrl) | EEPROM_DATO, ctrl);
else else
*ctrl &= ~EEPROM_DATO; writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
*ctrl &= ~EEPROM_ECLK; writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
*ctrl |= EEPROM_ECLK; writel(readl(ctrl) | EEPROM_ECLK, ctrl);
ser_cmd <<= 1; ser_cmd <<= 1;
} }
*ctrl &= ~EEPROM_DATO; /* see data sheet timing diagram */ /* see data sheet timing diagram */
writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
} }
unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg) unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg)
{ {
unsigned short res = 0; unsigned short res = 0;
int i; int i;
*ctrl &= ~EEPROM_EPROT; writel(readl(ctrl) & ~EEPROM_EPROT, ctrl);
eeprom_cs_on(ctrl); eeprom_cs_on(ctrl);
eeprom_cmd(ctrl, EEPROM_READ, reg); eeprom_cmd(ctrl, EEPROM_READ, reg);
/* clock the data ouf of serial mem */ /* clock the data ouf of serial mem */
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
*ctrl &= ~EEPROM_ECLK; writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
delay(); delay();
*ctrl |= EEPROM_ECLK; writel(readl(ctrl) | EEPROM_ECLK, ctrl);
delay(); delay();
res <<= 1; res <<= 1;
if (*ctrl & EEPROM_DATI) if (readl(ctrl) & EEPROM_DATI)
res |= 1; res |= 1;
} }

14
arch/mips/sgi-ip22/ip22-time.c
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@ -94,7 +94,7 @@ static int indy_rtc_set_time(unsigned long tim)
static unsigned long dosample(void) static unsigned long dosample(void)
{ {
u32 ct0, ct1; u32 ct0, ct1;
volatile u8 msb, lsb; u8 msb, lsb;
/* Start the counter. */ /* Start the counter. */
sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
@ -107,21 +107,21 @@ static unsigned long dosample(void)
/* Latch and spin until top byte of counter2 is zero */ /* Latch and spin until top byte of counter2 is zero */
do { do {
sgint->tcword = SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT; writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword);
lsb = sgint->tcnt2; lsb = readb(&sgint->tcnt2);
msb = sgint->tcnt2; msb = readb(&sgint->tcnt2);
ct1 = read_c0_count(); ct1 = read_c0_count();
} while (msb); } while (msb);
/* Stop the counter. */ /* Stop the counter. */
sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | writeb(sgint->tcword, (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
SGINT_TCWORD_MSWST); SGINT_TCWORD_MSWST));
/* /*
* Return the difference, this is how far the r4k counter increments * Return the difference, this is how far the r4k counter increments
* for every 1/HZ seconds. We round off the nearest 1 MHz of master * for every 1/HZ seconds. We round off the nearest 1 MHz of master
* clock (= 1000000 / HZ / 2). * clock (= 1000000 / HZ / 2).
*/ */
/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
return (ct1 - ct0) / (500000/HZ) * (500000/HZ); return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
} }

2
include/asm-mips/sgi/hpc3.h
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@ -206,7 +206,7 @@ struct hpc3_regs {
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */ #define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */ #define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
volatile u32 eeprom; /* EEPROM data reg. */ u32 eeprom; /* EEPROM data reg. */
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */ #define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */ #define HPC3_EEPROM_CSEL 0x02 /* Chip select */
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */ #define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */

2
include/asm-mips/sgi/ip22.h
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@ -72,7 +72,7 @@
#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE) #define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg); extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
extern unsigned short ip22_nvram_read(int reg); extern unsigned short ip22_nvram_read(int reg);
#endif #endif

2
include/asm-mips/sgi/mc.h
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@ -57,7 +57,7 @@ struct sgimc_regs {
volatile u32 divider; /* Divider reg for RPSS */ volatile u32 divider; /* Divider reg for RPSS */
u32 _unused5; u32 _unused5;
volatile u32 eeprom; /* EEPROM byte reg for r4k */ u32 eeprom; /* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ #define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ #define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ #define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */