ARM: tegra: Add firmware calls required for suspend-resume on Tegra30

In order to suspend-resume CPU with Trusted Foundations firmware being
present on Tegra30, the LP1/LP2 boot vectors and CPU caches need to be
set up using the firmware calls and then suspend code shall avoid
re-disabling parts that were disabled by the firmware.

Tested-by: Robert Yang <decatf@gmail.com>
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2019-03-18 01:52:10 +03:00 committed by Thierry Reding
parent dae84be59d
commit 78ee399f16
3 changed files with 84 additions and 5 deletions

View File

@ -33,11 +33,13 @@
#include <soc/tegra/pmc.h>
#include <asm/cacheflush.h>
#include <asm/firmware.h>
#include <asm/idmap.h>
#include <asm/proc-fns.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/tlbflush.h>
#include <asm/trusted_foundations.h>
#include "iomap.h"
#include "pm.h"
@ -159,6 +161,28 @@ int tegra_cpu_do_idle(void)
static int tegra_sleep_cpu(unsigned long v2p)
{
/*
* L2 cache disabling using kernel API only allowed when all
* secondary CPU's are offline. Cache have to be disabled with
* MMU-on if cache maintenance is done via Trusted Foundations
* firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
* if any of secondary CPU's is online and this is the LP2-idle
* code-path only for Tegra20/30.
*/
if (trusted_foundations_registered())
outer_disable();
/*
* Note that besides of setting up CPU reset vector this firmware
* call may also do the following, depending on the FW version:
* 1) Disable L2. But this doesn't matter since we already
* disabled the L2.
* 2) Disable D-cache. This need to be taken into account in
* particular by the tegra_disable_clean_inv_dcache() which
* shall avoid the re-disable.
*/
call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
setup_mm_for_reboot();
tegra_sleep_cpu_finish(v2p);
@ -197,6 +221,14 @@ void tegra_idle_lp2_last(void)
cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
/*
* Resume L2 cache if it wasn't re-enabled early during resume,
* which is the case for Tegra30 that has to re-enable the cache
* via firmware call. In other cases cache is already enabled and
* hence re-enabling is a no-op. This is always a no-op on Tegra114+.
*/
outer_resume();
restore_cpu_complex();
cpu_cluster_pm_exit();
}
@ -215,6 +247,15 @@ enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
static int tegra_sleep_core(unsigned long v2p)
{
/*
* Cache have to be disabled with MMU-on if cache maintenance is done
* via Trusted Foundations firmware. This is a no-op on Tegra114+.
*/
if (trusted_foundations_registered())
outer_disable();
call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
setup_mm_for_reboot();
tegra_sleep_core_finish(v2p);
@ -342,6 +383,14 @@ static int tegra_suspend_enter(suspend_state_t state)
cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
/*
* Resume L2 cache if it wasn't re-enabled early during resume,
* which is the case for Tegra30 that has to re-enable the cache
* via firmware call. In other cases cache is already enabled and
* hence re-enabling is a no-op.
*/
outer_resume();
switch (mode) {
case TEGRA_SUSPEND_LP1:
tegra_suspend_exit_lp1();

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@ -20,6 +20,7 @@
#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
@ -76,6 +77,7 @@ ENTRY(tegra_resume)
orr r1, r1, #1
str r1, [r0]
#endif
bl tegra_resume_trusted_foundations
#ifdef CONFIG_CACHE_L2X0
/* L2 cache resume & re-enable */
@ -88,6 +90,30 @@ end_ca9_scu_l2_resume:
b cpu_resume
ENDPROC(tegra_resume)
/*
* tegra_resume_trusted_foundations
*
* Trusted Foundations firmware initialization.
*
* Doesn't return if firmware presents.
* Corrupted registers: r1, r2
*/
ENTRY(tegra_resume_trusted_foundations)
/* Check whether Trusted Foundations firmware presents. */
mov32 r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
ldr r1, =__tegra_cpu_reset_handler_data_offset + \
RESET_DATA(TF_PRESENT)
ldr r1, [r2, r1]
cmp r1, #0
reteq lr
.arch_extension sec
/* First call after suspend wakes firmware. No arguments required. */
smc #0
b cpu_resume
ENDPROC(tegra_resume_trusted_foundations)
#endif
.align L1_CACHE_SHIFT

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@ -49,8 +49,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
/* Disable the D-cache */
mrc p15, 0, r2, c1, c0, 0
tst r2, #CR_C @ see tegra_sleep_cpu()
bic r2, r2, #CR_C
mcr p15, 0, r2, c1, c0, 0
mcrne p15, 0, r2, c1, c0, 0
isb
/* Flush the D-cache */
@ -132,10 +133,13 @@ ENTRY(tegra_shut_off_mmu)
#ifdef CONFIG_CACHE_L2X0
/* Disable L2 cache */
check_cpu_part_num 0xc09, r9, r10
movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
moveq r3, #0
streq r3, [r2, #L2X0_CTRL]
retne r0
mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000
ldr r3, [r2, #L2X0_CTRL]
tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu()
mov r3, #0
strne r3, [r2, #L2X0_CTRL]
#endif
ret r0
ENDPROC(tegra_shut_off_mmu)