Merge branch 'kvm-updates/2.6.35' of git://git.kernel.org/pub/scm/virt/kvm/kvm
* 'kvm-updates/2.6.35' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: read apic->irr with ioapic lock held KVM: ia64: Add missing spin_unlock in kvm_arch_hardware_enable() KVM: Fix order passed to iommu_unmap KVM: MMU: Remove user access when allowing kernel access to gpte.w=0 page KVM: MMU: invalidate and flush on spte small->large page size change KVM: SVM: Implement workaround for Erratum 383 KVM: SVM: Handle MCEs early in the vmexit process KVM: powerpc: fix init/exit annotation
This commit is contained in:
Linus Torvalds
commit
7908a9e5fc
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@ -144,6 +144,7 @@ int kvm_arch_hardware_enable(void *garbage)
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VP_INIT_ENV : VP_INIT_ENV_INITALIZE,
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__pa(kvm_vm_buffer), KVM_VM_BUFFER_BASE, &tmp_base);
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if (status != 0) {
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spin_unlock(&vp_lock);
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printk(KERN_WARNING"kvm: Failed to Enable VT Support!!!!\n");
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return -EINVAL;
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}
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@ -164,7 +164,7 @@ static int __init kvmppc_e500_init(void)
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return kvm_init(NULL, sizeof(struct kvmppc_vcpu_e500), 0, THIS_MODULE);
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}
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static void __init kvmppc_e500_exit(void)
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static void __exit kvmppc_e500_exit(void)
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{
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kvmppc_booke_exit();
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}
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@ -110,6 +110,7 @@
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#define MSR_AMD64_PATCH_LOADER 0xc0010020
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#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
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@ -1815,6 +1815,9 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
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spte |= PT_WRITABLE_MASK;
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if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
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spte &= ~PT_USER_MASK;
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/*
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* Optimization: for pte sync, if spte was writable the hash
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* lookup is unnecessary (and expensive). Write protection
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@ -1870,6 +1873,8 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
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child = page_header(pte & PT64_BASE_ADDR_MASK);
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mmu_page_remove_parent_pte(child, sptep);
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__set_spte(sptep, shadow_trap_nonpresent_pte);
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kvm_flush_remote_tlbs(vcpu->kvm);
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} else if (pfn != spte_to_pfn(*sptep)) {
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pgprintk("hfn old %lx new %lx\n",
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spte_to_pfn(*sptep), pfn);
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@ -28,6 +28,7 @@
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#include <linux/ftrace_event.h>
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#include <linux/slab.h>
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#include <asm/tlbflush.h>
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#include <asm/desc.h>
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#include <asm/virtext.h>
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@ -56,6 +57,8 @@ MODULE_LICENSE("GPL");
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#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
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static bool erratum_383_found __read_mostly;
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static const u32 host_save_user_msrs[] = {
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#ifdef CONFIG_X86_64
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MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
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@ -374,6 +377,31 @@ static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
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svm->vmcb->control.event_inj_err = error_code;
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}
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static void svm_init_erratum_383(void)
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{
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u32 low, high;
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int err;
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u64 val;
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/* Only Fam10h is affected */
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if (boot_cpu_data.x86 != 0x10)
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return;
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/* Use _safe variants to not break nested virtualization */
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val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
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if (err)
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return;
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val |= (1ULL << 47);
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low = lower_32_bits(val);
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high = upper_32_bits(val);
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native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
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erratum_383_found = true;
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}
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static int has_svm(void)
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{
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const char *msg;
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@ -429,6 +457,8 @@ static int svm_hardware_enable(void *garbage)
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wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
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svm_init_erratum_383();
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return 0;
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}
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@ -1410,8 +1440,59 @@ static int nm_interception(struct vcpu_svm *svm)
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return 1;
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}
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static int mc_interception(struct vcpu_svm *svm)
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static bool is_erratum_383(void)
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{
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int err, i;
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u64 value;
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if (!erratum_383_found)
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return false;
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value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
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if (err)
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return false;
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/* Bit 62 may or may not be set for this mce */
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value &= ~(1ULL << 62);
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if (value != 0xb600000000010015ULL)
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return false;
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/* Clear MCi_STATUS registers */
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for (i = 0; i < 6; ++i)
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native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
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value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
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if (!err) {
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u32 low, high;
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value &= ~(1ULL << 2);
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low = lower_32_bits(value);
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high = upper_32_bits(value);
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native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
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}
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/* Flush tlb to evict multi-match entries */
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__flush_tlb_all();
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return true;
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}
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static void svm_handle_mce(struct vcpu_svm *svm)
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{
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if (is_erratum_383()) {
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/*
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* Erratum 383 triggered. Guest state is corrupt so kill the
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* guest.
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*/
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pr_err("KVM: Guest triggered AMD Erratum 383\n");
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set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
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return;
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}
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/*
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* On an #MC intercept the MCE handler is not called automatically in
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* the host. So do it by hand here.
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@ -1420,6 +1501,11 @@ static int mc_interception(struct vcpu_svm *svm)
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"int $0x12\n");
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/* not sure if we ever come back to this point */
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return;
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}
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static int mc_interception(struct vcpu_svm *svm)
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{
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return 1;
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}
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@ -3088,6 +3174,14 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
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vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
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vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
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}
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/*
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* We need to handle MC intercepts here before the vcpu has a chance to
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* change the physical cpu
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*/
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if (unlikely(svm->vmcb->control.exit_code ==
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SVM_EXIT_EXCP_BASE + MC_VECTOR))
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svm_handle_mce(svm);
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}
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#undef R
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@ -192,12 +192,13 @@ static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
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{
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u32 old_irr = ioapic->irr;
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u32 old_irr;
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u32 mask = 1 << irq;
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union kvm_ioapic_redirect_entry entry;
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int ret = 1;
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spin_lock(&ioapic->lock);
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old_irr = ioapic->irr;
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if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
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entry = ioapic->redirtbl[irq];
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level ^= entry.fields.polarity;
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@ -271,7 +271,7 @@ static void kvm_iommu_put_pages(struct kvm *kvm,
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pfn = phys >> PAGE_SHIFT;
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/* Unmap address from IO address space */
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order = iommu_unmap(domain, gfn_to_gpa(gfn), PAGE_SIZE);
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order = iommu_unmap(domain, gfn_to_gpa(gfn), 0);
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unmap_pages = 1ULL << order;
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/* Unpin all pages we just unmapped to not leak any memory */
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