ASoC: Intel: cht_bsw_rt5645: Add quirk for boards using pmc_plt_clk_0
[ Upstream commitadebb11139
] As of commit648e921888
("clk: x86: Stop marking clocks as CLK_IS_CRITICAL"), the cht_bsw_rt5645 driver needs to enable the clock it's using for the codec's mclk. It does this from commit7735bce05a
("ASoC: Intel: boards: use devm_clk_get() unconditionally"), enabling pmc_plt_clk_3. However, Strago family Chromebooks use pmc_plt_clk_0 for the codec mclk, resulting in white noise with some digital microphones. Add a DMI-based quirk for Strago family Chromebooks to use pmc_plt_clk_0 instead - mirroring the changes made to cht_bsw_max98090_ti in commita182ecd380
("ASoC: intel: cht_bsw_max98090_ti: Add quirk for boards using pmc_plt_clk_0") and making use of the existing dmi_check_system() call and related infrastructure added in commit22af29114e
("ASoC: Intel: cht-bsw-rt5645: add quirks for SSP0/AIF1/AIF2 routing"). Signed-off-by: Sam McNally <sammc@chromium.org> Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20190917054933.209335-1-sammc@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -48,6 +48,7 @@ struct cht_mc_private {
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#define CHT_RT5645_SSP2_AIF2 BIT(16) /* default is using AIF1 */
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#define CHT_RT5645_SSP0_AIF1 BIT(17)
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#define CHT_RT5645_SSP0_AIF2 BIT(18)
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#define CHT_RT5645_PMC_PLT_CLK_0 BIT(19)
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static unsigned long cht_rt5645_quirk = 0;
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@ -59,6 +60,8 @@ static void log_quirks(struct device *dev)
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dev_info(dev, "quirk SSP0_AIF1 enabled");
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if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)
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dev_info(dev, "quirk SSP0_AIF2 enabled");
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if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0)
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dev_info(dev, "quirk PMC_PLT_CLK_0 enabled");
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}
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static int platform_clock_control(struct snd_soc_dapm_widget *w,
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@ -226,15 +229,21 @@ static int cht_aif1_hw_params(struct snd_pcm_substream *substream,
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return 0;
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}
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/* uncomment when we have a real quirk
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static int cht_rt5645_quirk_cb(const struct dmi_system_id *id)
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{
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cht_rt5645_quirk = (unsigned long)id->driver_data;
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return 1;
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}
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*/
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static const struct dmi_system_id cht_rt5645_quirk_table[] = {
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{
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/* Strago family Chromebooks */
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.callback = cht_rt5645_quirk_cb,
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.matches = {
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DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
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},
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.driver_data = (void *)CHT_RT5645_PMC_PLT_CLK_0,
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},
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{
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},
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};
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@ -526,6 +535,7 @@ static int snd_cht_mc_probe(struct platform_device *pdev)
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int dai_index = 0;
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int ret_val = 0;
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int i;
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const char *mclk_name;
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drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
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if (!drv)
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@ -662,11 +672,15 @@ static int snd_cht_mc_probe(struct platform_device *pdev)
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if (ret_val)
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return ret_val;
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drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
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if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0)
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mclk_name = "pmc_plt_clk_0";
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else
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mclk_name = "pmc_plt_clk_3";
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drv->mclk = devm_clk_get(&pdev->dev, mclk_name);
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if (IS_ERR(drv->mclk)) {
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dev_err(&pdev->dev,
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"Failed to get MCLK from pmc_plt_clk_3: %ld\n",
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PTR_ERR(drv->mclk));
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dev_err(&pdev->dev, "Failed to get MCLK from %s: %ld\n",
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mclk_name, PTR_ERR(drv->mclk));
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return PTR_ERR(drv->mclk);
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}
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