powerpc fixes for 4.4 #3
- opal-irqchip: Fix double endian conversion from Alistair Popple - cxl: Set endianess of kernel contexts from Frederic Barrat - sbc8641: drop bogus PHY IRQ entries from DTS file from Paul Gortmaker - Revert "powerpc/eeh: Don't unfreeze PHB PE after reset" from Andrew Donnellan -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWbIyYAAoJEFHr6jzI4aWA30QP+wUIWYwPsceIguT2IQLFN6mj buPS/wukpcSiqltAFtpf2aAe+LgTPt2P6geZfIdrd8QsS8wgO4ncpW8NGxyNIRNr sBZONQIwPMkrOMAQeCvz7wEQk5pfIT5IqY0qP6HqIwBpSr80+zHRSr+RAwYT0VHn sHoCObSumc099dvj+YUetKzF5L3bTCLK+GVytB471OL7ORmc5EOnrwFSG6HBO/KC yiJQ1VjCm7tNfaXL9BmBfpePyGBCFySXjb5vB8rtS2pXjg7Ugnnp5pGUCBtM05ar mMmhaxTv4QffcJKh7XtwKPwCcSDVcF4nmtL/3F/TfvT8IkuHbageORp1wnda+5uL MF6QEOfWWETTXzd6lFib+Z5WoC/XBiPTKg1rx+vpEqyeuPVm/mkwcsYpVoU69z+w zY5Bzs6tIkTBTg5qQXQM6dckamWHpKa4xjiVyHJbnPyJcsR4fHpD3W0rUY9NwZu9 siqRM0rlabq9fNdsfN8f8XZBZ9z4dNBtTDulDgLgaQK4J17H/9/jWrz8TYPg3cfH iFK2ilv8zJpLQEFWmubsyO1QZeJe7GbMQcCmnZH2wK94XtbFHDjaMFwRpZ7ibPnl GzgmRLqboWTVqwlOFtRZvY7dH7r9lVQD2nOhHHO1d471RQB7PoWlmdEZzRWHqP39 DiGMymogq3IYjPhXL/dx =bYj2 -----END PGP SIGNATURE----- Merge tag 'powerpc-4.4-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: - opal-irqchip: Fix double endian conversion from Alistair Popple - cxl: Set endianess of kernel contexts from Frederic Barrat - sbc8641: drop bogus PHY IRQ entries from DTS file from Paul Gortmaker - Revert "powerpc/eeh: Don't unfreeze PHB PE after reset" from Andrew Donnellan * tag 'powerpc-4.4-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: Revert "powerpc/eeh: Don't unfreeze PHB PE after reset" powerpc/sbc8641: drop bogus PHY IRQ entries from DTS file cxl: Set endianess of kernel contexts powerpc/opal-irqchip: Fix double endian conversion
This commit is contained in:
commit
79dbddaf8e
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@ -227,23 +227,15 @@
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reg = <0x520 0x20>;
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reg = <0x520 0x20>;
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phy0: ethernet-phy@1f {
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phy0: ethernet-phy@1f {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <0x1f>;
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reg = <0x1f>;
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};
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};
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phy1: ethernet-phy@0 {
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phy1: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <0>;
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reg = <0>;
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};
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};
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phy2: ethernet-phy@1 {
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phy2: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <1>;
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reg = <1>;
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};
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};
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phy3: ethernet-phy@2 {
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phy3: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <2>;
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reg = <2>;
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};
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};
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tbi0: tbi-phy@11 {
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tbi0: tbi-phy@11 {
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@ -590,16 +590,10 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
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eeh_ops->configure_bridge(pe);
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eeh_ops->configure_bridge(pe);
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eeh_pe_restore_bars(pe);
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eeh_pe_restore_bars(pe);
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/*
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/* Clear frozen state */
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* If it's PHB PE, the frozen state on all available PEs should have
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rc = eeh_clear_pe_frozen_state(pe, false);
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* been cleared by the PHB reset. Otherwise, we unfreeze the PE and its
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if (rc)
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* child PEs because they might be in frozen state.
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return rc;
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*/
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if (!(pe->type & EEH_PE_PHB)) {
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rc = eeh_clear_pe_frozen_state(pe, false);
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if (rc)
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return rc;
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}
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/* Give the system 5 seconds to finish running the user-space
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/* Give the system 5 seconds to finish running the user-space
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* hotplug shutdown scripts, e.g. ifdown for ethernet. Yes,
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* hotplug shutdown scripts, e.g. ifdown for ethernet. Yes,
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@ -43,11 +43,34 @@ static unsigned int opal_irq_count;
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static unsigned int *opal_irqs;
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static unsigned int *opal_irqs;
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static void opal_handle_irq_work(struct irq_work *work);
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static void opal_handle_irq_work(struct irq_work *work);
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static __be64 last_outstanding_events;
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static u64 last_outstanding_events;
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static struct irq_work opal_event_irq_work = {
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static struct irq_work opal_event_irq_work = {
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.func = opal_handle_irq_work,
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.func = opal_handle_irq_work,
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};
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};
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void opal_handle_events(uint64_t events)
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{
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int virq, hwirq = 0;
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u64 mask = opal_event_irqchip.mask;
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if (!in_irq() && (events & mask)) {
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last_outstanding_events = events;
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irq_work_queue(&opal_event_irq_work);
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return;
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}
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while (events & mask) {
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hwirq = fls64(events) - 1;
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if (BIT_ULL(hwirq) & mask) {
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virq = irq_find_mapping(opal_event_irqchip.domain,
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hwirq);
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if (virq)
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generic_handle_irq(virq);
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}
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events &= ~BIT_ULL(hwirq);
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}
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}
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static void opal_event_mask(struct irq_data *d)
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static void opal_event_mask(struct irq_data *d)
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{
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{
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clear_bit(d->hwirq, &opal_event_irqchip.mask);
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clear_bit(d->hwirq, &opal_event_irqchip.mask);
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@ -55,12 +78,12 @@ static void opal_event_mask(struct irq_data *d)
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static void opal_event_unmask(struct irq_data *d)
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static void opal_event_unmask(struct irq_data *d)
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{
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{
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__be64 events;
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set_bit(d->hwirq, &opal_event_irqchip.mask);
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set_bit(d->hwirq, &opal_event_irqchip.mask);
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opal_poll_events(&last_outstanding_events);
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opal_poll_events(&events);
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if (last_outstanding_events & opal_event_irqchip.mask)
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opal_handle_events(be64_to_cpu(events));
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/* Need to retrigger the interrupt */
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irq_work_queue(&opal_event_irq_work);
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}
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}
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static int opal_event_set_type(struct irq_data *d, unsigned int flow_type)
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static int opal_event_set_type(struct irq_data *d, unsigned int flow_type)
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@ -96,29 +119,6 @@ static int opal_event_map(struct irq_domain *d, unsigned int irq,
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return 0;
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return 0;
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}
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}
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void opal_handle_events(uint64_t events)
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{
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int virq, hwirq = 0;
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u64 mask = opal_event_irqchip.mask;
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if (!in_irq() && (events & mask)) {
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last_outstanding_events = events;
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irq_work_queue(&opal_event_irq_work);
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return;
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}
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while (events & mask) {
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hwirq = fls64(events) - 1;
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if (BIT_ULL(hwirq) & mask) {
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virq = irq_find_mapping(opal_event_irqchip.domain,
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hwirq);
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if (virq)
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generic_handle_irq(virq);
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}
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events &= ~BIT_ULL(hwirq);
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}
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}
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static irqreturn_t opal_interrupt(int irq, void *data)
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static irqreturn_t opal_interrupt(int irq, void *data)
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{
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{
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__be64 events;
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__be64 events;
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@ -131,7 +131,7 @@ static irqreturn_t opal_interrupt(int irq, void *data)
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static void opal_handle_irq_work(struct irq_work *work)
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static void opal_handle_irq_work(struct irq_work *work)
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{
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{
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opal_handle_events(be64_to_cpu(last_outstanding_events));
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opal_handle_events(last_outstanding_events);
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}
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}
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static int opal_event_match(struct irq_domain *h, struct device_node *node,
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static int opal_event_match(struct irq_domain *h, struct device_node *node,
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@ -497,6 +497,7 @@ static u64 calculate_sr(struct cxl_context *ctx)
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{
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{
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u64 sr = 0;
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u64 sr = 0;
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set_endian(sr);
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if (ctx->master)
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if (ctx->master)
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sr |= CXL_PSL_SR_An_MP;
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sr |= CXL_PSL_SR_An_MP;
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if (mfspr(SPRN_LPCR) & LPCR_TC)
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if (mfspr(SPRN_LPCR) & LPCR_TC)
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@ -506,7 +507,6 @@ static u64 calculate_sr(struct cxl_context *ctx)
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sr |= CXL_PSL_SR_An_HV;
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sr |= CXL_PSL_SR_An_HV;
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} else {
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} else {
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sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
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sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
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set_endian(sr);
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sr &= ~(CXL_PSL_SR_An_HV);
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sr &= ~(CXL_PSL_SR_An_HV);
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if (!test_tsk_thread_flag(current, TIF_32BIT))
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if (!test_tsk_thread_flag(current, TIF_32BIT))
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sr |= CXL_PSL_SR_An_SF;
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sr |= CXL_PSL_SR_An_SF;
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