clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
The third parent of CSI_MCLK is PLL_PERIPH1, not PLL_PERIPH0.
Fix it.
Fixes: 0577e4853b
("clk: sunxi-ng: Add H3 clocks")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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@ -476,7 +476,7 @@ static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
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static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
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0x134, 16, 4, 24, 3, BIT(31), 0);
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static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
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static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
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static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
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0x134, 0, 5, 8, 3, BIT(15), 0);
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