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Allwinner core changes for 3.14 

This mostly adds the reset controller initialisation for the A31 and the SMP
 operations for this SoC.
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Merge tag 'sunxi-core-for-3.14' of https://github.com/mripard/linux into next/drivers

From Maxime Ripard:
Allwinner core changes for 3.14

This mostly adds the reset controller initialisation for the A31 and the SMP
operations for this SoC.

* tag 'sunxi-core-for-3.14' of https://github.com/mripard/linux:
  ARM: sun6i: Add SMP support for the Allwinner A31
  dt-bindings: fix example of allwinner interrupt controller
  ARM: sunxi: Register the A31 reset IP in init_time
  ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-01-03 21:43:05 -08:00
parent a7dedb4fea 73346794b4
commit 7bfc397fe7
7 changed files with 169 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
View File

@ -14,5 +14,5 @@ intc: interrupt-controller {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
};

1
arch/arm/mach-sunxi/Kconfig
View File

@ -1,5 +1,6 @@
config ARCH_SUNXI
bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select ARCH_REQUIRE_GPIOLIB
select ARM_GIC
select CLKSRC_MMIO

1
arch/arm/mach-sunxi/Makefile
View File

@ -1 +1,2 @@
obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o

19
arch/arm/mach-sunxi/common.h Normal file
View File

@ -0,0 +1,19 @@
/*
* Core functions for Allwinner SoCs
*
* Copyright (C) 2013 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ARCH_SUNXI_COMMON_H_
#define __ARCH_SUNXI_COMMON_H_
void sun6i_secondary_startup(void);
extern struct smp_operations sun6i_smp_ops;
#endif /* __ARCH_SUNXI_COMMON_H_ */

9
arch/arm/mach-sunxi/headsmp.S Normal file
View File

@ -0,0 +1,9 @@
#include <linux/linkage.h>
#include <linux/init.h>
.section ".text.head", "ax"
ENTRY(sun6i_secondary_startup)
msr cpsr_fsxc, #0xd3
b secondary_startup
ENDPROC(sun6i_secondary_startup)

124
arch/arm/mach-sunxi/platsmp.c Normal file
View File

@ -0,0 +1,124 @@
/*
* SMP support for Allwinner SoCs
*
* Copyright (C) 2013 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* Based on code
* Copyright (C) 2012-2013 Allwinner Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/memory.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include "common.h"
#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
#define CPUCFG_GEN_CTRL_REG 0x184
#define CPUCFG_PRIVATE0_REG 0x1a4
#define CPUCFG_PRIVATE1_REG 0x1a8
#define CPUCFG_DBG_CTL0_REG 0x1e0
#define CPUCFG_DBG_CTL1_REG 0x1e4
#define PRCM_CPU_PWROFF_REG 0x100
#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
static void __iomem *cpucfg_membase;
static void __iomem *prcm_membase;
static DEFINE_SPINLOCK(cpu_lock);
static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
if (!node) {
pr_err("Missing A31 PRCM node in the device tree\n");
return;
}
prcm_membase = of_iomap(node, 0);
if (!prcm_membase) {
pr_err("Couldn't map A31 PRCM registers\n");
return;
}
node = of_find_compatible_node(NULL, NULL,
"allwinner,sun6i-a31-cpuconfig");
if (!node) {
pr_err("Missing A31 CPU config node in the device tree\n");
return;
}
cpucfg_membase = of_iomap(node, 0);
if (!cpucfg_membase)
pr_err("Couldn't map A31 CPU config registers\n");
}
static int sun6i_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
u32 reg;
int i;
if (!(prcm_membase && cpucfg_membase))
return -EFAULT;
spin_lock(&cpu_lock);
/* Set CPU boot address */
writel(virt_to_phys(sun6i_secondary_startup),
cpucfg_membase + CPUCFG_PRIVATE0_REG);
/* Assert the CPU core in reset */
writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
/* Assert the L1 cache in reset */
reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
/* Disable external debug access */
reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
/* Power up the CPU */
for (i = 0; i <= 8; i++)
writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
mdelay(10);
/* Clear CPU power-off gating */
reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
mdelay(1);
/* Deassert the CPU core reset */
writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
/* Enable back the external debug accesses */
reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
spin_unlock(&cpu_lock);
return 0;
}
struct smp_operations sun6i_smp_ops __initdata = {
.smp_prepare_cpus = sun6i_smp_prepare_cpus,
.smp_boot_secondary = sun6i_smp_boot_secondary,
};

14
arch/arm/mach-sunxi/sunxi.c
View File

@ -10,6 +10,8 @@
* warranty of any kind, whether express or implied.
*/
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
@ -23,6 +25,8 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include "common.h"
#define SUN4I_WATCHDOG_CTRL_REG 0x00
#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
#define SUN4I_WATCHDOG_MODE_REG 0x04
@ -132,10 +136,20 @@ static const char * const sun6i_board_dt_compat[] = {
NULL,
};
extern void __init sun6i_reset_init(void);
static void __init sun6i_timer_init(void)
{
of_clk_init(NULL);
sun6i_reset_init();
clocksource_of_init();
}
DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
.init_machine = sunxi_dt_init,
.init_time = sun6i_timer_init,
.dt_compat = sun6i_board_dt_compat,
.restart = sun6i_restart,
.smp = smp_ops(sun6i_smp_ops),
MACHINE_END
static const char * const sun7i_board_dt_compat[] = {