OMAP4: clock: Add dummy clock nodes for interface clocks
On OMAP4 platform the iclk control is completly under hardware control and no software control is available. This difference w.r.t previous OMAP's needs all the common driver accross OMAP's , cpu_is_xxxx() checks. To avoid poulluting the drivers dummy clock nodes are created (The autogeneration script has been updated accordingly). Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: made OMAP1 dummy_ck common and edited patch to reuse that] Signed-off-by: Paul Walmsley <paul@pwsan.com>
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@ -38,20 +38,6 @@ struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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* Omap1 specific clock functions
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*-------------------------------------------------------------------------*/
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static int clk_omap1_dummy_enable(struct clk *clk)
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{
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return 0;
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}
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static void clk_omap1_dummy_disable(struct clk *clk)
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{
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}
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const struct clkops clkops_dummy = {
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.enable = clk_omap1_dummy_enable,
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.disable = clk_omap1_dummy_disable,
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};
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unsigned long omap1_uart_recalc(struct clk *clk)
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{
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unsigned int val = __raw_readl(clk->enable_reg);
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@ -27,12 +27,6 @@
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* Omap1 clocks
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*-------------------------------------------------------------------------*/
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/* XXX is this necessary? */
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static struct clk dummy_ck = {
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.name = "dummy",
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.ops = &clkops_dummy,
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};
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static struct clk ck_ref = {
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.name = "ck_ref",
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.ops = &clkops_null,
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@ -127,6 +127,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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extern u8 cpu_mask;
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extern const struct clkops clkops_omap2_dflt_wait;
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extern const struct clkops clkops_dummy;
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extern const struct clkops clkops_omap2_dflt;
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extern struct clk_functions omap2_clk_functions;
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@ -2645,6 +2645,41 @@ static struct omap_clk omap44xx_clks[] = {
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CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
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CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
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CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
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CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
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CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
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CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
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CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
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CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
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CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
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CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
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CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
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CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
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CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X),
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CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
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CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
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CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcspi.1", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcspi.2", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcspi.3", "ick", &dummy_ck, CK_443X),
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CLK("omap-mcspi.4", "ick", &dummy_ck, CK_443X),
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CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
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CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
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CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
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CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
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CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
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};
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int __init omap4xxx_clk_init(void)
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@ -357,6 +357,16 @@ const struct clkops clkops_null = {
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.disable = clkll_disable_null,
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};
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/*
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* Dummy clock
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*
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* Used for clock aliases that are needed on some OMAPs, but not others
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*/
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struct clk dummy_ck = {
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.name = "dummy",
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.ops = &clkops_null,
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};
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#ifdef CONFIG_CPU_FREQ
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void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
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{
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@ -186,6 +186,8 @@ extern struct clk *omap_clk_get_by_name(const char *name);
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extern const struct clkops clkops_null;
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extern struct clk dummy_ck;
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/* Clock flags */
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
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#define CLOCK_IDLE_CONTROL (1 << 1)
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