[ARM] MXC: Switch MX1 to clkdev support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
6d73665f05
commit
7dae1134cd
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@ -18,11 +18,14 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/math64.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <mach/clock.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk)
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}
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static struct clk clk16m = {
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.name = "CLK16M",
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.get_rate = clk16m_get_rate,
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.enable = _clk_enable,
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.enable_reg = CCM_CSCR,
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@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk)
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}
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static struct clk clk32 = {
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.name = "CLK32",
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.get_rate = clk32_get_rate,
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};
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@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk)
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}
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static struct clk clk32_premult = {
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.name = "CLK32_premultiplier",
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.parent = &clk32,
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.get_rate = clk32_premult_get_rate,
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};
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@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
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}
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static struct clk prem_clk = {
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.name = "prem_clk",
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.set_parent = prem_clk_set_parent,
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};
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@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk)
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}
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static struct clk system_clk = {
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.name = "system_clk",
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.parent = &prem_clk,
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.get_rate = system_clk_get_rate,
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};
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@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk)
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}
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static struct clk mcu_clk = {
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.name = "mcu_clk",
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.parent = &clk32_premult,
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.get_rate = mcu_clk_get_rate,
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};
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@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk)
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}
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static struct clk fclk = {
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.name = "fclk",
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.parent = &mcu_clk,
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.get_rate = fclk_get_rate,
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};
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@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate)
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}
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static struct clk hclk = {
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.name = "hclk",
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.parent = &system_clk,
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.get_rate = hclk_get_rate,
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.round_rate = hclk_round_rate,
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@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate)
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}
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static struct clk clk48m = {
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.name = "CLK48M",
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.parent = &system_clk,
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.get_rate = clk48m_get_rate,
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.round_rate = clk48m_round_rate,
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@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate)
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static struct clk perclk[] = {
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{
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.name = "perclk",
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.id = 0,
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.parent = &system_clk,
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.get_rate = perclk1_get_rate,
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.round_rate = perclk1_round_rate,
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.set_rate = perclk1_set_rate,
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}, {
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.name = "perclk",
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.id = 1,
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.parent = &system_clk,
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.get_rate = perclk2_get_rate,
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.round_rate = perclk2_round_rate,
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.set_rate = perclk2_set_rate,
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}, {
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.name = "perclk",
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.id = 2,
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.parent = &system_clk,
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.get_rate = perclk3_get_rate,
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@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent)
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}
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static struct clk clko_clk = {
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.name = "clko_clk",
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.set_parent = clko_set_parent,
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};
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static struct clk dma_clk = {
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.name = "dma",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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@ -473,7 +462,6 @@ static struct clk dma_clk = {
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};
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static struct clk csi_clk = {
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.name = "csi_clk",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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@ -484,7 +472,6 @@ static struct clk csi_clk = {
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};
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static struct clk mma_clk = {
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.name = "mma_clk",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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@ -495,7 +482,6 @@ static struct clk mma_clk = {
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};
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static struct clk usbd_clk = {
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.name = "usbd_clk",
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.parent = &clk48m,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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@ -506,99 +492,85 @@ static struct clk usbd_clk = {
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};
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static struct clk gpt_clk = {
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.name = "gpt_clk",
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.parent = &perclk[0],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk uart_clk = {
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.name = "uart",
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.parent = &perclk[0],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk i2c_clk = {
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.name = "i2c_clk",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk spi_clk = {
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.name = "spi_clk",
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.parent = &perclk[1],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk sdhc_clk = {
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.name = "sdhc_clk",
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.parent = &perclk[1],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.parent = &perclk[1],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk mshc_clk = {
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.name = "mshc_clk",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk ssi_clk = {
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.name = "ssi_clk",
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.parent = &perclk[2],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk rtc_clk = {
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.name = "rtc_clk",
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.parent = &clk32,
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};
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static struct clk *mxc_clks[] = {
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&clk16m,
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&clk32,
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&clk32_premult,
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&prem_clk,
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&system_clk,
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&mcu_clk,
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&fclk,
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&hclk,
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&clk48m,
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&perclk[0],
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&perclk[1],
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&perclk[2],
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&clko_clk,
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&dma_clk,
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&csi_clk,
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&mma_clk,
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&usbd_clk,
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&gpt_clk,
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&uart_clk,
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&i2c_clk,
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&spi_clk,
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&sdhc_clk,
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&lcdc_clk,
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&mshc_clk,
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&ssi_clk,
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&rtc_clk,
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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.dev_id = d, \
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.con_id = n, \
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.clk = &c, \
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},
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static struct clk_lookup lookups[] __initdata = {
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_REGISTER_CLOCK(NULL, "dma", dma_clk)
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_REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
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_REGISTER_CLOCK(NULL, "mma", mma_clk)
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_REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
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_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
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_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
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_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
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_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
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_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
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_REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
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_REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
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_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
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_REGISTER_CLOCK(NULL, "mshc", mshc_clk)
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_REGISTER_CLOCK(NULL, "ssi", ssi_clk)
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_REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
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};
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int __init mx1_clocks_init(unsigned long fref)
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{
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struct clk **clkp;
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unsigned int reg;
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int i;
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/* disable clocks we are able to */
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__raw_writel(0, SCM_GCCR);
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@ -620,8 +592,8 @@ int __init mx1_clocks_init(unsigned long fref)
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reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
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clko_clk.parent = (struct clk *)clko_clocks[reg];
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for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
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clk_register(*clkp);
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for (i = 0; i < ARRAY_SIZE(lookups); i++)
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clkdev_add(&lookups[i]);
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clk_enable(&hclk);
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clk_enable(&fclk);
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@ -9,6 +9,7 @@ choice
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config ARCH_MX1
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bool "MX1-based"
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select CPU_ARM920T
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select COMMON_CLKDEV
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help
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This enables support for systems based on the Freescale i.MX1 family
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