mfd: ti_am335x_tscadc: Don't read back REG_SE
The purpose of reg_se_cache has been defeated. It should avoid the read-back of the register to avoid the latency and the fact that the bits are reset to 0 after the individual conversation took place. The reason why this is required like this to work, is that read-back of the register removes the bits of the ADC so they do not start another conversation after the register is re-written from the TSC side for the update. To avoid the not required read-back I introduce a "set once" variant which does not update the cache mask. After the conversation completes, the bit is removed from the SE register anyway and we don't plan a new conversation "any time soon". The current set function is renamed to set_cache to distinguish the two operations. This is a small preparation for a larger sync-rework. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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@ -181,7 +181,7 @@ static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
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enb |= (get_adc_step_bit(adc_dev, bit) << 1);
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adc_dev->buffer_en_ch_steps = enb;
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am335x_tsc_se_set(adc_dev->mfd_tscadc, enb);
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am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb);
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tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES
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| IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW);
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@ -332,7 +332,7 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
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return -EBUSY;
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step_en = get_adc_step_mask(adc_dev);
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am335x_tsc_se_set(adc_dev->mfd_tscadc, step_en);
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am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
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/* Wait for ADC sequencer to complete sampling */
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while (tiadc_readl(adc_dev, REG_ADCFSM) & SEQ_STATUS) {
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@ -198,7 +198,7 @@ static void titsc_step_config(struct titsc *ts_dev)
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/* The steps1 … end and bit 0 for TS_Charge */
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stepenable = (1 << (end_step + 2)) - 1;
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ts_dev->step_mask = stepenable;
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am335x_tsc_se_set(ts_dev->mfd_tscadc, ts_dev->step_mask);
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am335x_tsc_se_set_cache(ts_dev->mfd_tscadc, ts_dev->step_mask);
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}
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static void titsc_read_coordinates(struct titsc *ts_dev,
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@ -322,7 +322,7 @@ static irqreturn_t titsc_irq(int irq, void *dev)
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if (irqclr) {
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titsc_writel(ts_dev, REG_IRQSTATUS, irqclr);
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am335x_tsc_se_set(ts_dev->mfd_tscadc, ts_dev->step_mask);
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am335x_tsc_se_set_cache(ts_dev->mfd_tscadc, ts_dev->step_mask);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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@ -53,24 +53,32 @@ static void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc)
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
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}
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void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val)
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void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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tsadc->reg_se_cache = tscadc_readl(tsadc, REG_SE);
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tsadc->reg_se_cache |= val;
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am335x_tsc_se_update(tsadc);
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set);
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
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void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache | val);
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
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void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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tsadc->reg_se_cache = tscadc_readl(tsadc, REG_SE);
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tsadc->reg_se_cache &= ~val;
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am335x_tsc_se_update(tsadc);
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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@ -176,7 +176,8 @@ static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
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return *tscadc_dev;
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}
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void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
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#endif
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