KVM: PPC: Use PACA backed shadow vcpu
We're being horribly racy right now. All the entry and exit code hijacks random fields from the PACA that could easily be used by different code in case we get interrupted, for example by a #MC or even page fault. After discussing this with Ben, we figured it's best to reserve some more space in the PACA and just shove off some vcpu state to there. That way we can drastically improve the readability of the code, make it less racy and less complex. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Alexander Graf
Marcelo Tosatti
parent
992b5b29b5
commit
7e57cba060
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@ -23,6 +23,7 @@
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s_64_asm.h>
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struct kvmppc_slb {
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u64 esid;
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@ -69,6 +70,7 @@ struct kvmppc_sid_map {
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struct kvmppc_vcpu_book3s {
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struct kvm_vcpu vcpu;
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struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
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struct kvmppc_sid_map sid_map[SID_MAP_NUM];
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struct kvmppc_slb slb[64];
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struct {
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@ -20,6 +20,8 @@
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#ifndef __ASM_KVM_BOOK3S_ASM_H__
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#define __ASM_KVM_BOOK3S_ASM_H__
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#ifdef __ASSEMBLY__
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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#include <asm/kvm_asm.h>
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@ -55,4 +57,21 @@ kvmppc_resume_\intno:
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#endif /* CONFIG_KVM_BOOK3S_64_HANDLER */
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#else /*__ASSEMBLY__ */
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struct kvmppc_book3s_shadow_vcpu {
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ulong gpr[14];
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u32 cr;
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u32 xer;
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ulong host_r1;
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ulong host_r2;
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ulong handler;
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ulong scratch0;
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ulong scratch1;
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ulong vmhandler;
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ulong rmhandler;
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};
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#endif /*__ASSEMBLY__ */
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#endif /* __ASM_KVM_BOOK3S_ASM_H__ */
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@ -175,10 +175,13 @@ struct kvm_vcpu_arch {
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ulong gpr[32];
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ulong pc;
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u32 cr;
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ulong ctr;
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ulong lr;
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#ifdef CONFIG_BOOKE
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ulong xer;
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u32 cr;
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#endif
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ulong msr;
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#ifdef CONFIG_PPC64
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@ -98,34 +98,42 @@ extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu);
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#ifdef CONFIG_PPC_BOOK3S
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/* We assume we're always acting on the current vcpu */
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static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
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{
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vcpu->arch.gpr[num] = val;
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if ( num < 14 )
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get_paca()->shadow_vcpu.gpr[num] = val;
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else
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vcpu->arch.gpr[num] = val;
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}
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static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
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{
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return vcpu->arch.gpr[num];
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if ( num < 14 )
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return get_paca()->shadow_vcpu.gpr[num];
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else
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return vcpu->arch.gpr[num];
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}
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static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
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{
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vcpu->arch.cr = val;
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get_paca()->shadow_vcpu.cr = val;
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}
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static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.cr;
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return get_paca()->shadow_vcpu.cr;
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}
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static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val)
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{
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vcpu->arch.xer = val;
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get_paca()->shadow_vcpu.xer = val;
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}
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static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.xer;
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return get_paca()->shadow_vcpu.xer;
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}
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#else
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@ -19,6 +19,9 @@
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#include <asm/mmu.h>
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#include <asm/page.h>
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#include <asm/exception-64e.h>
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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#include <asm/kvm_book3s_64_asm.h>
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#endif
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register struct paca_struct *local_paca asm("r13");
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@ -135,6 +138,8 @@ struct paca_struct {
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u64 esid;
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u64 vsid;
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} kvm_slb[64]; /* guest SLB */
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/* We use this to store guest state in */
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struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
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u8 kvm_slb_max; /* highest used guest slb entry */
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u8 kvm_in_guest; /* are we inside the guest? */
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#endif
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@ -194,6 +194,32 @@ int main(void)
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DEFINE(PACA_KVM_IN_GUEST, offsetof(struct paca_struct, kvm_in_guest));
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DEFINE(PACA_KVM_SLB, offsetof(struct paca_struct, kvm_slb));
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DEFINE(PACA_KVM_SLB_MAX, offsetof(struct paca_struct, kvm_slb_max));
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DEFINE(PACA_KVM_CR, offsetof(struct paca_struct, shadow_vcpu.cr));
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DEFINE(PACA_KVM_XER, offsetof(struct paca_struct, shadow_vcpu.xer));
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DEFINE(PACA_KVM_R0, offsetof(struct paca_struct, shadow_vcpu.gpr[0]));
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DEFINE(PACA_KVM_R1, offsetof(struct paca_struct, shadow_vcpu.gpr[1]));
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DEFINE(PACA_KVM_R2, offsetof(struct paca_struct, shadow_vcpu.gpr[2]));
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DEFINE(PACA_KVM_R3, offsetof(struct paca_struct, shadow_vcpu.gpr[3]));
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DEFINE(PACA_KVM_R4, offsetof(struct paca_struct, shadow_vcpu.gpr[4]));
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DEFINE(PACA_KVM_R5, offsetof(struct paca_struct, shadow_vcpu.gpr[5]));
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DEFINE(PACA_KVM_R6, offsetof(struct paca_struct, shadow_vcpu.gpr[6]));
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DEFINE(PACA_KVM_R7, offsetof(struct paca_struct, shadow_vcpu.gpr[7]));
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DEFINE(PACA_KVM_R8, offsetof(struct paca_struct, shadow_vcpu.gpr[8]));
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DEFINE(PACA_KVM_R9, offsetof(struct paca_struct, shadow_vcpu.gpr[9]));
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DEFINE(PACA_KVM_R10, offsetof(struct paca_struct, shadow_vcpu.gpr[10]));
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DEFINE(PACA_KVM_R11, offsetof(struct paca_struct, shadow_vcpu.gpr[11]));
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DEFINE(PACA_KVM_R12, offsetof(struct paca_struct, shadow_vcpu.gpr[12]));
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DEFINE(PACA_KVM_R13, offsetof(struct paca_struct, shadow_vcpu.gpr[13]));
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DEFINE(PACA_KVM_HOST_R1, offsetof(struct paca_struct, shadow_vcpu.host_r1));
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DEFINE(PACA_KVM_HOST_R2, offsetof(struct paca_struct, shadow_vcpu.host_r2));
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DEFINE(PACA_KVM_VMHANDLER, offsetof(struct paca_struct,
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shadow_vcpu.vmhandler));
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DEFINE(PACA_KVM_RMHANDLER, offsetof(struct paca_struct,
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shadow_vcpu.rmhandler));
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DEFINE(PACA_KVM_SCRATCH0, offsetof(struct paca_struct,
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shadow_vcpu.scratch0));
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DEFINE(PACA_KVM_SCRATCH1, offsetof(struct paca_struct,
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shadow_vcpu.scratch1));
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#endif
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#endif /* CONFIG_PPC64 */
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@ -389,8 +415,6 @@ int main(void)
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DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid));
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DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr));
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DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
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DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
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DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
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DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
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DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
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DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.msr));
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@ -415,7 +439,10 @@ int main(void)
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DEFINE(VCPU_TRAMPOLINE_ENTER, offsetof(struct kvm_vcpu, arch.trampoline_enter));
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DEFINE(VCPU_HIGHMEM_HANDLER, offsetof(struct kvm_vcpu, arch.highmem_handler));
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DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
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#endif
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#else
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DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
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DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
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#endif /* CONFIG_PPC64 */
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#endif
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#ifdef CONFIG_44x
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DEFINE(PGD_T_LOG2, PGD_T_LOG2);
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@ -66,12 +66,16 @@ void kvmppc_core_load_guest_debugstate(struct kvm_vcpu *vcpu)
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void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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{
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memcpy(get_paca()->kvm_slb, to_book3s(vcpu)->slb_shadow, sizeof(get_paca()->kvm_slb));
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memcpy(&get_paca()->shadow_vcpu, &to_book3s(vcpu)->shadow_vcpu,
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sizeof(get_paca()->shadow_vcpu));
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get_paca()->kvm_slb_max = to_book3s(vcpu)->slb_shadow_max;
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}
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void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
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{
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memcpy(to_book3s(vcpu)->slb_shadow, get_paca()->kvm_slb, sizeof(get_paca()->kvm_slb));
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memcpy(&to_book3s(vcpu)->shadow_vcpu, &get_paca()->shadow_vcpu,
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sizeof(get_paca()->shadow_vcpu));
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to_book3s(vcpu)->slb_shadow_max = get_paca()->kvm_slb_max;
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}
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@ -28,11 +28,6 @@
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#define ULONG_SIZE 8
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#define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
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.macro mfpaca tmp_reg, src_reg, offset, vcpu_reg
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ld \tmp_reg, (PACA_EXMC+\offset)(r13)
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std \tmp_reg, VCPU_GPR(\src_reg)(\vcpu_reg)
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.endm
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.macro DISABLE_INTERRUPTS
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mfmsr r0
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rldicl r0,r0,48,1
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@ -92,37 +87,30 @@ kvm_start_entry:
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/* Load non-volatile guest state from the vcpu */
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VCPU_LOAD_NVGPRS(r4)
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/* Save R1/R2 in the PACA */
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std r1, PACA_KVM_HOST_R1(r13)
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std r2, PACA_KVM_HOST_R2(r13)
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/* XXX swap in/out on load? */
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ld r3, VCPU_HIGHMEM_HANDLER(r4)
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std r3, PACA_KVM_VMHANDLER(r13)
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ld r3, VCPU_TRAMPOLINE_ENTER(r4)
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std r3, PACA_KVM_RMHANDLER(r13)
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kvm_start_lightweight:
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ld r9, VCPU_PC(r4) /* r9 = vcpu->arch.pc */
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ld r10, VCPU_SHADOW_MSR(r4) /* r10 = vcpu->arch.shadow_msr */
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DISABLE_INTERRUPTS
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/* Save R1/R2 in the PACA */
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std r1, PACAR1(r13)
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std r2, (PACA_EXMC+EX_SRR0)(r13)
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ld r3, VCPU_HIGHMEM_HANDLER(r4)
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std r3, PACASAVEDMSR(r13)
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ld r3, VCPU_TRAMPOLINE_ENTER(r4)
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mtsrr0 r3
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LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR))
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mtsrr1 r3
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/* Load guest state in the respective registers */
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lwz r3, VCPU_CR(r4) /* r3 = vcpu->arch.cr */
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stw r3, (PACA_EXMC + EX_CCR)(r13)
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/* Load some guest state in the respective registers */
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ld r3, VCPU_CTR(r4) /* r3 = vcpu->arch.ctr */
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mtctr r3 /* CTR = r3 */
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ld r3, VCPU_LR(r4) /* r3 = vcpu->arch.lr */
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mtlr r3 /* LR = r3 */
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ld r3, VCPU_XER(r4) /* r3 = vcpu->arch.xer */
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std r3, (PACA_EXMC + EX_R3)(r13)
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DISABLE_INTERRUPTS
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/* Some guests may need to have dcbz set to 32 byte length.
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*
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@ -142,34 +130,21 @@ kvm_start_lightweight:
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mtspr SPRN_HID5,r3
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no_dcbz32_on:
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/* Load guest GPRs */
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ld r3, VCPU_GPR(r9)(r4)
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std r3, (PACA_EXMC + EX_R9)(r13)
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ld r3, VCPU_GPR(r10)(r4)
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std r3, (PACA_EXMC + EX_R10)(r13)
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ld r3, VCPU_GPR(r11)(r4)
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std r3, (PACA_EXMC + EX_R11)(r13)
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ld r3, VCPU_GPR(r12)(r4)
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std r3, (PACA_EXMC + EX_R12)(r13)
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ld r3, VCPU_GPR(r13)(r4)
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std r3, (PACA_EXMC + EX_R13)(r13)
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ld r0, VCPU_GPR(r0)(r4)
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ld r1, VCPU_GPR(r1)(r4)
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ld r2, VCPU_GPR(r2)(r4)
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ld r3, VCPU_GPR(r3)(r4)
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ld r5, VCPU_GPR(r5)(r4)
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ld r6, VCPU_GPR(r6)(r4)
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ld r7, VCPU_GPR(r7)(r4)
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ld r8, VCPU_GPR(r8)(r4)
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ld r4, VCPU_GPR(r4)(r4)
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/* This sets the Magic value for the trampoline */
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/* XXX this needs to move into a safe function, so we can
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be sure we don't get any interrupts */
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li r11, 1
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stb r11, PACA_KVM_IN_GUEST(r13)
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ld r3, PACA_KVM_RMHANDLER(r13)
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mtsrr0 r3
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LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR))
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mtsrr1 r3
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/* Jump to SLB patching handlder and into our guest */
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RFI
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@ -185,60 +160,31 @@ kvmppc_handler_highmem:
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/*
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* Register usage at this point:
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*
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* R00 = guest R13
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* R01 = host R1
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* R02 = host R2
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* R10 = guest PC
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* R11 = guest MSR
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* R12 = exit handler id
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* R13 = PACA
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* PACA.exmc.R9 = guest R1
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* PACA.exmc.R10 = guest R10
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* PACA.exmc.R11 = guest R11
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* PACA.exmc.R12 = guest R12
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* PACA.exmc.R13 = guest R2
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* PACA.exmc.DAR = guest DAR
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* PACA.exmc.DSISR = guest DSISR
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* PACA.exmc.LR = guest instruction
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* PACA.exmc.CCR = guest CR
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* PACA.exmc.SRR0 = guest R0
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* R0 = guest last inst
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* R1 = host R1
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* R2 = host R2
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* R3 = guest PC
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* R4 = guest MSR
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* R5 = guest DAR
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* R6 = guest DSISR
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* R13 = PACA
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* PACA.KVM.* = guest *
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*
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*/
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std r3, (PACA_EXMC+EX_R3)(r13)
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/* save the exit id in R3 */
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mr r3, r12
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/* R12 = vcpu */
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ld r12, GPR4(r1)
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/* R7 = vcpu */
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ld r7, GPR4(r1)
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/* Now save the guest state */
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std r0, VCPU_GPR(r13)(r12)
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std r4, VCPU_GPR(r4)(r12)
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std r5, VCPU_GPR(r5)(r12)
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std r6, VCPU_GPR(r6)(r12)
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std r7, VCPU_GPR(r7)(r12)
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std r8, VCPU_GPR(r8)(r12)
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std r9, VCPU_GPR(r9)(r12)
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stw r0, VCPU_LAST_INST(r7)
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/* get registers from PACA */
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mfpaca r5, r0, EX_SRR0, r12
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mfpaca r5, r3, EX_R3, r12
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mfpaca r5, r1, EX_R9, r12
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mfpaca r5, r10, EX_R10, r12
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mfpaca r5, r11, EX_R11, r12
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mfpaca r5, r12, EX_R12, r12
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mfpaca r5, r2, EX_R13, r12
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std r3, VCPU_PC(r7)
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std r4, VCPU_SHADOW_MSR(r7)
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std r5, VCPU_FAULT_DEAR(r7)
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std r6, VCPU_FAULT_DSISR(r7)
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lwz r5, (PACA_EXMC+EX_LR)(r13)
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stw r5, VCPU_LAST_INST(r12)
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lwz r5, (PACA_EXMC+EX_CCR)(r13)
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stw r5, VCPU_CR(r12)
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ld r5, VCPU_HFLAGS(r12)
|
||||
ld r5, VCPU_HFLAGS(r7)
|
||||
rldicl. r5, r5, 0, 63 /* CR = ((r5 & 1) == 0) */
|
||||
beq no_dcbz32_off
|
||||
|
||||
|
|
@ -248,58 +194,42 @@ kvmppc_handler_highmem:
|
|||
|
||||
no_dcbz32_off:
|
||||
|
||||
std r14, VCPU_GPR(r14)(r12)
|
||||
std r15, VCPU_GPR(r15)(r12)
|
||||
std r16, VCPU_GPR(r16)(r12)
|
||||
std r17, VCPU_GPR(r17)(r12)
|
||||
std r18, VCPU_GPR(r18)(r12)
|
||||
std r19, VCPU_GPR(r19)(r12)
|
||||
std r20, VCPU_GPR(r20)(r12)
|
||||
std r21, VCPU_GPR(r21)(r12)
|
||||
std r22, VCPU_GPR(r22)(r12)
|
||||
std r23, VCPU_GPR(r23)(r12)
|
||||
std r24, VCPU_GPR(r24)(r12)
|
||||
std r25, VCPU_GPR(r25)(r12)
|
||||
std r26, VCPU_GPR(r26)(r12)
|
||||
std r27, VCPU_GPR(r27)(r12)
|
||||
std r28, VCPU_GPR(r28)(r12)
|
||||
std r29, VCPU_GPR(r29)(r12)
|
||||
std r30, VCPU_GPR(r30)(r12)
|
||||
std r31, VCPU_GPR(r31)(r12)
|
||||
std r14, VCPU_GPR(r14)(r7)
|
||||
std r15, VCPU_GPR(r15)(r7)
|
||||
std r16, VCPU_GPR(r16)(r7)
|
||||
std r17, VCPU_GPR(r17)(r7)
|
||||
std r18, VCPU_GPR(r18)(r7)
|
||||
std r19, VCPU_GPR(r19)(r7)
|
||||
std r20, VCPU_GPR(r20)(r7)
|
||||
std r21, VCPU_GPR(r21)(r7)
|
||||
std r22, VCPU_GPR(r22)(r7)
|
||||
std r23, VCPU_GPR(r23)(r7)
|
||||
std r24, VCPU_GPR(r24)(r7)
|
||||
std r25, VCPU_GPR(r25)(r7)
|
||||
std r26, VCPU_GPR(r26)(r7)
|
||||
std r27, VCPU_GPR(r27)(r7)
|
||||
std r28, VCPU_GPR(r28)(r7)
|
||||
std r29, VCPU_GPR(r29)(r7)
|
||||
std r30, VCPU_GPR(r30)(r7)
|
||||
std r31, VCPU_GPR(r31)(r7)
|
||||
|
||||
/* Save guest PC (R10) */
|
||||
std r10, VCPU_PC(r12)
|
||||
|
||||
/* Save guest msr (R11) */
|
||||
std r11, VCPU_SHADOW_MSR(r12)
|
||||
|
||||
/* Save guest CTR (in R12) */
|
||||
/* Save guest CTR */
|
||||
mfctr r5
|
||||
std r5, VCPU_CTR(r12)
|
||||
std r5, VCPU_CTR(r7)
|
||||
|
||||
/* Save guest LR */
|
||||
mflr r5
|
||||
std r5, VCPU_LR(r12)
|
||||
std r5, VCPU_LR(r7)
|
||||
|
||||
/* Save guest XER */
|
||||
mfxer r5
|
||||
std r5, VCPU_XER(r12)
|
||||
|
||||
/* Save guest DAR */
|
||||
ld r5, (PACA_EXMC+EX_DAR)(r13)
|
||||
std r5, VCPU_FAULT_DEAR(r12)
|
||||
|
||||
/* Save guest DSISR */
|
||||
lwz r5, (PACA_EXMC+EX_DSISR)(r13)
|
||||
std r5, VCPU_FAULT_DSISR(r12)
|
||||
/* XXX convert to safe function call */
|
||||
|
||||
/* Restore host msr -> SRR1 */
|
||||
ld r7, VCPU_HOST_MSR(r12)
|
||||
mtsrr1 r7
|
||||
ld r6, VCPU_HOST_MSR(r7)
|
||||
mtsrr1 r6
|
||||
|
||||
/* Restore host IP -> SRR0 */
|
||||
ld r6, VCPU_HOST_RETIP(r12)
|
||||
mtsrr0 r6
|
||||
ld r5, VCPU_HOST_RETIP(r7)
|
||||
mtsrr0 r5
|
||||
|
||||
/*
|
||||
* For some interrupts, we need to call the real Linux
|
||||
|
|
@ -311,9 +241,9 @@ no_dcbz32_off:
|
|||
* r3 = address of interrupt handler (exit reason)
|
||||
*/
|
||||
|
||||
cmpwi r3, BOOK3S_INTERRUPT_EXTERNAL
|
||||
cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
|
||||
beq call_linux_handler
|
||||
cmpwi r3, BOOK3S_INTERRUPT_DECREMENTER
|
||||
cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER
|
||||
beq call_linux_handler
|
||||
|
||||
/* Back to Interruptable Mode! (goto kvm_return_point) */
|
||||
|
|
@ -334,12 +264,12 @@ call_linux_handler:
|
|||
* R7 VCPU_HOST_MSR
|
||||
*/
|
||||
|
||||
mtlr r3
|
||||
mtlr r12
|
||||
|
||||
ld r5, VCPU_TRAMPOLINE_LOWMEM(r12)
|
||||
mtsrr0 r5
|
||||
LOAD_REG_IMMEDIATE(r5, MSR_KERNEL & ~(MSR_IR | MSR_DR))
|
||||
mtsrr1 r5
|
||||
ld r4, VCPU_TRAMPOLINE_LOWMEM(r7)
|
||||
mtsrr0 r4
|
||||
LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR))
|
||||
mtsrr1 r3
|
||||
|
||||
RFI
|
||||
|
||||
|
|
@ -350,7 +280,7 @@ kvm_return_point:
|
|||
/* go back into the guest */
|
||||
|
||||
/* Pass the exit number as 3rd argument to kvmppc_handle_exit */
|
||||
mr r5, r3
|
||||
mr r5, r12
|
||||
|
||||
/* Restore r3 (kvm_run) and r4 (vcpu) */
|
||||
REST_2GPRS(3, r1)
|
||||
|
|
|
|||
|
|
@ -45,37 +45,21 @@ kvmppc_trampoline_\intno:
|
|||
* To distinguish, we check a magic byte in the PACA
|
||||
*/
|
||||
mfspr r13, SPRN_SPRG_PACA /* r13 = PACA */
|
||||
std r12, (PACA_EXMC + EX_R12)(r13)
|
||||
std r12, PACA_KVM_SCRATCH0(r13)
|
||||
mfcr r12
|
||||
stw r12, (PACA_EXMC + EX_CCR)(r13)
|
||||
stw r12, PACA_KVM_SCRATCH1(r13)
|
||||
lbz r12, PACA_KVM_IN_GUEST(r13)
|
||||
cmpwi r12, 0
|
||||
bne ..kvmppc_handler_hasmagic_\intno
|
||||
/* No KVM guest? Then jump back to the Linux handler! */
|
||||
lwz r12, (PACA_EXMC + EX_CCR)(r13)
|
||||
lwz r12, PACA_KVM_SCRATCH1(r13)
|
||||
mtcr r12
|
||||
ld r12, (PACA_EXMC + EX_R12)(r13)
|
||||
ld r12, PACA_KVM_SCRATCH0(r13)
|
||||
mfspr r13, SPRN_SPRG_SCRATCH0 /* r13 = original r13 */
|
||||
b kvmppc_resume_\intno /* Get back original handler */
|
||||
|
||||
/* Now we know we're handling a KVM guest */
|
||||
..kvmppc_handler_hasmagic_\intno:
|
||||
/* Unset guest state */
|
||||
li r12, 0
|
||||
stb r12, PACA_KVM_IN_GUEST(r13)
|
||||
|
||||
std r1, (PACA_EXMC+EX_R9)(r13)
|
||||
std r10, (PACA_EXMC+EX_R10)(r13)
|
||||
std r11, (PACA_EXMC+EX_R11)(r13)
|
||||
std r2, (PACA_EXMC+EX_R13)(r13)
|
||||
|
||||
mfsrr0 r10
|
||||
mfsrr1 r11
|
||||
|
||||
/* Restore R1/R2 so we can handle faults */
|
||||
ld r1, PACAR1(r13)
|
||||
ld r2, (PACA_EXMC+EX_SRR0)(r13)
|
||||
|
||||
/* Let's store which interrupt we're handling */
|
||||
li r12, \intno
|
||||
|
||||
|
|
@ -106,16 +90,16 @@ INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_VSX
|
|||
*
|
||||
* Input Registers:
|
||||
*
|
||||
* R6 = SRR0
|
||||
* R7 = SRR1
|
||||
* R5 = SRR0
|
||||
* R6 = SRR1
|
||||
* LR = real-mode IP
|
||||
*
|
||||
*/
|
||||
.global kvmppc_handler_lowmem_trampoline
|
||||
kvmppc_handler_lowmem_trampoline:
|
||||
|
||||
mtsrr0 r6
|
||||
mtsrr1 r7
|
||||
mtsrr0 r5
|
||||
mtsrr1 r6
|
||||
blr
|
||||
kvmppc_handler_lowmem_trampoline_end:
|
||||
|
||||
|
|
|
|||
|
|
@ -51,24 +51,18 @@ kvmppc_handler_trampoline_enter:
|
|||
*
|
||||
* MSR = ~IR|DR
|
||||
* R13 = PACA
|
||||
* R1 = host R1
|
||||
* R2 = host R2
|
||||
* R9 = guest IP
|
||||
* R10 = guest MSR
|
||||
* R11 = free
|
||||
* R12 = free
|
||||
* PACA[PACA_EXMC + EX_R9] = guest R9
|
||||
* PACA[PACA_EXMC + EX_R10] = guest R10
|
||||
* PACA[PACA_EXMC + EX_R11] = guest R11
|
||||
* PACA[PACA_EXMC + EX_R12] = guest R12
|
||||
* PACA[PACA_EXMC + EX_R13] = guest R13
|
||||
* PACA[PACA_EXMC + EX_CCR] = guest CR
|
||||
* PACA[PACA_EXMC + EX_R3] = guest XER
|
||||
* all other GPRS = free
|
||||
* PACA[KVM_CR] = guest CR
|
||||
* PACA[KVM_XER] = guest XER
|
||||
*/
|
||||
|
||||
mtsrr0 r9
|
||||
mtsrr1 r10
|
||||
|
||||
mtspr SPRN_SPRG_SCRATCH0, r0
|
||||
|
||||
/* Remove LPAR shadow entries */
|
||||
|
||||
#if SLB_NUM_BOLTED == 3
|
||||
|
|
@ -131,20 +125,27 @@ slb_do_enter:
|
|||
|
||||
/* Enter guest */
|
||||
|
||||
mfspr r0, SPRN_SPRG_SCRATCH0
|
||||
ld r0, (PACA_KVM_R0)(r13)
|
||||
ld r1, (PACA_KVM_R1)(r13)
|
||||
ld r2, (PACA_KVM_R2)(r13)
|
||||
ld r3, (PACA_KVM_R3)(r13)
|
||||
ld r4, (PACA_KVM_R4)(r13)
|
||||
ld r5, (PACA_KVM_R5)(r13)
|
||||
ld r6, (PACA_KVM_R6)(r13)
|
||||
ld r7, (PACA_KVM_R7)(r13)
|
||||
ld r8, (PACA_KVM_R8)(r13)
|
||||
ld r9, (PACA_KVM_R9)(r13)
|
||||
ld r10, (PACA_KVM_R10)(r13)
|
||||
ld r12, (PACA_KVM_R12)(r13)
|
||||
|
||||
ld r9, (PACA_EXMC+EX_R9)(r13)
|
||||
ld r10, (PACA_EXMC+EX_R10)(r13)
|
||||
ld r12, (PACA_EXMC+EX_R12)(r13)
|
||||
|
||||
lwz r11, (PACA_EXMC+EX_CCR)(r13)
|
||||
lwz r11, (PACA_KVM_CR)(r13)
|
||||
mtcr r11
|
||||
|
||||
ld r11, (PACA_EXMC+EX_R3)(r13)
|
||||
ld r11, (PACA_KVM_XER)(r13)
|
||||
mtxer r11
|
||||
|
||||
ld r11, (PACA_EXMC+EX_R11)(r13)
|
||||
ld r13, (PACA_EXMC+EX_R13)(r13)
|
||||
ld r11, (PACA_KVM_R11)(r13)
|
||||
ld r13, (PACA_KVM_R13)(r13)
|
||||
|
||||
RFI
|
||||
kvmppc_handler_trampoline_enter_end:
|
||||
|
|
@ -162,28 +163,58 @@ kvmppc_handler_trampoline_exit:
|
|||
|
||||
/* Register usage at this point:
|
||||
*
|
||||
* SPRG_SCRATCH0 = guest R13
|
||||
* R01 = host R1
|
||||
* R02 = host R2
|
||||
* R10 = guest PC
|
||||
* R11 = guest MSR
|
||||
* R12 = exit handler id
|
||||
* R13 = PACA
|
||||
* PACA.exmc.CCR = guest CR
|
||||
* PACA.exmc.R9 = guest R1
|
||||
* PACA.exmc.R10 = guest R10
|
||||
* PACA.exmc.R11 = guest R11
|
||||
* PACA.exmc.R12 = guest R12
|
||||
* PACA.exmc.R13 = guest R2
|
||||
* SPRG_SCRATCH0 = guest R13
|
||||
* R12 = exit handler id
|
||||
* R13 = PACA
|
||||
* PACA.KVM.SCRATCH0 = guest R12
|
||||
* PACA.KVM.SCRATCH1 = guest CR
|
||||
*
|
||||
*/
|
||||
|
||||
/* Save registers */
|
||||
|
||||
std r0, (PACA_EXMC+EX_SRR0)(r13)
|
||||
std r9, (PACA_EXMC+EX_R3)(r13)
|
||||
std r10, (PACA_EXMC+EX_LR)(r13)
|
||||
std r11, (PACA_EXMC+EX_DAR)(r13)
|
||||
std r0, PACA_KVM_R0(r13)
|
||||
std r1, PACA_KVM_R1(r13)
|
||||
std r2, PACA_KVM_R2(r13)
|
||||
std r3, PACA_KVM_R3(r13)
|
||||
std r4, PACA_KVM_R4(r13)
|
||||
std r5, PACA_KVM_R5(r13)
|
||||
std r6, PACA_KVM_R6(r13)
|
||||
std r7, PACA_KVM_R7(r13)
|
||||
std r8, PACA_KVM_R8(r13)
|
||||
std r9, PACA_KVM_R9(r13)
|
||||
std r10, PACA_KVM_R10(r13)
|
||||
std r11, PACA_KVM_R11(r13)
|
||||
|
||||
/* Restore R1/R2 so we can handle faults */
|
||||
ld r1, PACA_KVM_HOST_R1(r13)
|
||||
ld r2, PACA_KVM_HOST_R2(r13)
|
||||
|
||||
/* Save guest PC and MSR in GPRs */
|
||||
mfsrr0 r3
|
||||
mfsrr1 r4
|
||||
|
||||
/* Get scratch'ed off registers */
|
||||
mfspr r9, SPRN_SPRG_SCRATCH0
|
||||
std r9, PACA_KVM_R13(r13)
|
||||
|
||||
ld r8, PACA_KVM_SCRATCH0(r13)
|
||||
std r8, PACA_KVM_R12(r13)
|
||||
|
||||
lwz r7, PACA_KVM_SCRATCH1(r13)
|
||||
stw r7, PACA_KVM_CR(r13)
|
||||
|
||||
/* Save more register state */
|
||||
|
||||
mfxer r6
|
||||
stw r6, PACA_KVM_XER(r13)
|
||||
|
||||
mfdar r5
|
||||
mfdsisr r6
|
||||
|
||||
/* Unset guest state */
|
||||
li r9, 0
|
||||
stb r9, PACA_KVM_IN_GUEST(r13)
|
||||
|
||||
/*
|
||||
* In order for us to easily get the last instruction,
|
||||
|
|
@ -207,7 +238,8 @@ ld_last_inst:
|
|||
ori r11, r9, MSR_DR /* Enable paging for data */
|
||||
mtmsr r11
|
||||
/* 2) fetch the instruction */
|
||||
lwz r0, 0(r10)
|
||||
/* XXX implement PACA_KVM_IN_GUEST=2 path to safely jump over this */
|
||||
lwz r0, 0(r3)
|
||||
/* 3) disable paging again */
|
||||
mtmsr r9
|
||||
|
||||
|
|
@ -233,29 +265,27 @@ no_ld_last_inst:
|
|||
|
||||
slb_do_exit:
|
||||
|
||||
/* Restore registers */
|
||||
|
||||
ld r11, (PACA_EXMC+EX_DAR)(r13)
|
||||
ld r10, (PACA_EXMC+EX_LR)(r13)
|
||||
ld r9, (PACA_EXMC+EX_R3)(r13)
|
||||
|
||||
/* Save last inst */
|
||||
stw r0, (PACA_EXMC+EX_LR)(r13)
|
||||
|
||||
/* Save DAR and DSISR before going to paged mode */
|
||||
mfdar r0
|
||||
std r0, (PACA_EXMC+EX_DAR)(r13)
|
||||
mfdsisr r0
|
||||
stw r0, (PACA_EXMC+EX_DSISR)(r13)
|
||||
/* Register usage at this point:
|
||||
*
|
||||
* R0 = guest last inst
|
||||
* R1 = host R1
|
||||
* R2 = host R2
|
||||
* R3 = guest PC
|
||||
* R4 = guest MSR
|
||||
* R5 = guest DAR
|
||||
* R6 = guest DSISR
|
||||
* R12 = exit handler id
|
||||
* R13 = PACA
|
||||
* PACA.KVM.* = guest *
|
||||
*
|
||||
*/
|
||||
|
||||
/* RFI into the highmem handler */
|
||||
mfmsr r0
|
||||
ori r0, r0, MSR_IR|MSR_DR|MSR_RI /* Enable paging */
|
||||
mtsrr1 r0
|
||||
ld r0, PACASAVEDMSR(r13) /* Highmem handler address */
|
||||
mtsrr0 r0
|
||||
|
||||
mfspr r0, SPRN_SPRG_SCRATCH0
|
||||
mfmsr r7
|
||||
ori r7, r7, MSR_IR|MSR_DR|MSR_RI /* Enable paging */
|
||||
mtsrr1 r7
|
||||
ld r8, PACA_KVM_VMHANDLER(r13) /* Highmem handler address */
|
||||
mtsrr0 r8
|
||||
|
||||
RFI
|
||||
kvmppc_handler_trampoline_exit_end:
|
||||
|
|
|
|||
Loading…
Reference in New Issue