Remove indirect read write api support.
The firmware of production devices does not support this interface so this is dead code. Signed-off-by: Sreedhara DS <sreedhara.ds@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Matthew Garrett <mjg@redhat.com>
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@ -34,20 +34,6 @@ int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);
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/* Update single register based on the mask */
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/* Update single register based on the mask */
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int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);
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int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);
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/*
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* Indirect register read
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* Can be used when SCCB(System Controller Configuration Block) register
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* HRIM(Honor Restricted IPC Messages) is set (bit 23)
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*/
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int intel_scu_ipc_register_read(u32 addr, u32 *data);
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/*
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* Indirect register write
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* Can be used when SCCB(System Controller Configuration Block) register
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* HRIM(Honor Restricted IPC Messages) is set (bit 23)
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*/
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int intel_scu_ipc_register_write(u32 addr, u32 data);
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/* Issue commands to the SCU with or without data */
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/* Issue commands to the SCU with or without data */
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int intel_scu_ipc_simple_command(int cmd, int sub);
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int intel_scu_ipc_simple_command(int cmd, int sub);
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int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
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int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
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@ -115,24 +115,6 @@ static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
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writel(data, ipcdev.ipc_base + 0x80 + offset);
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writel(data, ipcdev.ipc_base + 0x80 + offset);
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}
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}
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/*
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* IPC destination Pointer (Write Only):
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* Use content as pointer for destination write
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*/
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static inline void ipc_write_dptr(u32 data) /* Write dptr data */
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{
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writel(data, ipcdev.ipc_base + 0x0C);
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}
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/*
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* IPC Source Pointer (Write Only):
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* Use content as pointer for read location
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*/
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static inline void ipc_write_sptr(u32 data) /* Write dptr data */
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{
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writel(data, ipcdev.ipc_base + 0x08);
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}
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/*
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/*
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* Status Register (Read Only):
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* Status Register (Read Only):
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* Driver will read this register to get the ready/busy status of the IPC
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* Driver will read this register to get the ready/busy status of the IPC
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@ -413,70 +395,6 @@ int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
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}
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}
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EXPORT_SYMBOL(intel_scu_ipc_update_register);
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EXPORT_SYMBOL(intel_scu_ipc_update_register);
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/**
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* intel_scu_ipc_register_read - 32bit indirect read
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* @addr: register address
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* @value: 32bit value return
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*
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* Performs IA 32 bit indirect read, returns 0 on success, or an
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* error code.
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*
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* Can be used when SCCB(System Controller Configuration Block) register
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* HRIM(Honor Restricted IPC Messages) is set (bit 23)
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*
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* This function may sleep. Locking for SCU accesses is handled for
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* the caller.
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*/
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int intel_scu_ipc_register_read(u32 addr, u32 *value)
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{
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u32 err = 0;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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ipc_write_sptr(addr);
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ipc_command(4 << 16 | IPC_CMD_INDIRECT_RD);
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err = busy_loop();
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*value = ipc_data_readl(0);
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mutex_unlock(&ipclock);
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return err;
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}
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EXPORT_SYMBOL(intel_scu_ipc_register_read);
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/**
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* intel_scu_ipc_register_write - 32bit indirect write
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* @addr: register address
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* @value: 32bit value to write
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*
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* Performs IA 32 bit indirect write, returns 0 on success, or an
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* error code.
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*
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* Can be used when SCCB(System Controller Configuration Block) register
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* HRIM(Honor Restricted IPC Messages) is set (bit 23)
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*
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* This function may sleep. Locking for SCU accesses is handled for
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* the caller.
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*/
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int intel_scu_ipc_register_write(u32 addr, u32 value)
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{
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u32 err = 0;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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ipc_write_dptr(addr);
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ipc_data_writel(value, 0);
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ipc_command(4 << 16 | IPC_CMD_INDIRECT_WR);
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err = busy_loop();
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mutex_unlock(&ipclock);
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return err;
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}
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EXPORT_SYMBOL(intel_scu_ipc_register_write);
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/**
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/**
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* intel_scu_ipc_simple_command - send a simple command
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* intel_scu_ipc_simple_command - send a simple command
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* @cmd: command
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* @cmd: command
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