clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC
There are two USB3 host controllers on Hi3798CV200 SoC. This commit adds missing clocks for them. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -186,6 +186,23 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
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CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
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CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
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{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
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{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
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CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
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CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
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/* USB3 */
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{ HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
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{ HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
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{ HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
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{ HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
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{ HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
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{ HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
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{ HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
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{ HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
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};
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};
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static struct hisi_clock_data *hi3798cv200_clk_register(
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static struct hisi_clock_data *hi3798cv200_clk_register(
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@ -62,6 +62,14 @@
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#define HISTB_USB2_PHY1_REF_CLK 40
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#define HISTB_USB2_PHY1_REF_CLK 40
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#define HISTB_USB2_PHY2_REF_CLK 41
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#define HISTB_USB2_PHY2_REF_CLK 41
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#define HISTB_COMBPHY0_CLK 42
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#define HISTB_COMBPHY0_CLK 42
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#define HISTB_USB3_BUS_CLK 43
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#define HISTB_USB3_UTMI_CLK 44
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#define HISTB_USB3_PIPE_CLK 45
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#define HISTB_USB3_SUSPEND_CLK 46
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#define HISTB_USB3_BUS_CLK1 47
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#define HISTB_USB3_UTMI_CLK1 48
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#define HISTB_USB3_PIPE_CLK1 49
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#define HISTB_USB3_SUSPEND_CLK1 50
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/* clocks provided by mcu CRG */
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/* clocks provided by mcu CRG */
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#define HISTB_MCE_CLK 1
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#define HISTB_MCE_CLK 1
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