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@ -1,5 +1,5 @@
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/*
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* linux/arch/arm/mach-omap2/clock2xxx_data.c
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* linux/arch/arm/mach-omap2/clock2430_data.c
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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@ -28,8 +28,10 @@
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#include "cm-regbits-24xx.h"
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#include "sdrc.h"
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/*-------------------------------------------------------------------------
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* 24xx clock tree.
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#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
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/*
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* 2430 clock tree.
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*
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* NOTE:In many cases here we are assigning a 'default' parent. In many
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* cases the parent is selectable. The get/set parent calls will also
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@ -46,7 +48,7 @@
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* domains. Many get their interface clocks from the L4 domain, but get
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* functional clocks from fixed sources or other core domain derived
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* clocks.
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*-------------------------------------------------------------------------*/
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*/
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/* Base external input clocks */
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static struct clk func_32k_ck = {
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@ -313,10 +315,10 @@ static struct clk sys_clkout_src = {
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.ops = &clkops_omap2_dflt,
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.parent = &func_54m_ck,
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.clkdm_name = "wkup_clkdm",
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.enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
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.enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
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.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
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.clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
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.clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
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.clksel = common_clkout_src_clksel,
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.recalc = &omap2_clksel_recalc,
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@ -343,7 +345,7 @@ static struct clk sys_clkout = {
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.ops = &clkops_null,
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.parent = &sys_clkout_src,
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.clkdm_name = "wkup_clkdm",
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.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
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.clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
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.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
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.clksel = sys_clkout_clksel,
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.recalc = &omap2_clksel_recalc,
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@ -351,48 +353,12 @@ static struct clk sys_clkout = {
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.set_rate = &omap2_clksel_set_rate
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};
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/* In 2430, new in 2420 ES2 */
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static struct clk sys_clkout2_src = {
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.name = "sys_clkout2_src",
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.ops = &clkops_omap2_dflt,
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.parent = &func_54m_ck,
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.clkdm_name = "wkup_clkdm",
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.enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
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.enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
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.clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
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.clksel = common_clkout_src_clksel,
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.recalc = &omap2_clksel_recalc,
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.round_rate = &omap2_clksel_round_rate,
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.set_rate = &omap2_clksel_set_rate
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};
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static const struct clksel sys_clkout2_clksel[] = {
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{ .parent = &sys_clkout2_src, .rates = common_clkout_rates },
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{ .parent = NULL }
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};
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/* In 2430, new in 2420 ES2 */
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static struct clk sys_clkout2 = {
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.name = "sys_clkout2",
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.ops = &clkops_null,
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.parent = &sys_clkout2_src,
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.clkdm_name = "wkup_clkdm",
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.clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
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.clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
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.clksel = sys_clkout2_clksel,
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.recalc = &omap2_clksel_recalc,
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.round_rate = &omap2_clksel_round_rate,
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.set_rate = &omap2_clksel_set_rate
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};
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static struct clk emul_ck = {
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.name = "emul_ck",
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.ops = &clkops_omap2_dflt,
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.parent = &func_54m_ck,
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.clkdm_name = "wkup_clkdm",
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.enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
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.enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
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.enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
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.recalc = &followparent_recalc,
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@ -411,9 +377,6 @@ static struct clk emul_ck = {
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static const struct clksel_rate mpu_core_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
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{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
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{ .div = 4, .val = 4, .flags = RATE_IN_242X },
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{ .div = 6, .val = 6, .flags = RATE_IN_242X },
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{ .div = 8, .val = 8, .flags = RATE_IN_242X },
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{ .div = 0 },
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};
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@ -436,10 +399,9 @@ static struct clk mpu_ck = { /* Control cpu */
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};
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/*
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* DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
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* DSP (2430-IVA2.1) clock domain
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* Clocks:
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* 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
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* 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
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*
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* Won't be too specific here. The core clock comes into this block
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* it is divided then tee'ed. One branch goes directly to xyz enable
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@ -451,9 +413,6 @@ static const struct clksel_rate dsp_fck_core_rates[] = {
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{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
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{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
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{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
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{ .div = 6, .val = 6, .flags = RATE_IN_242X },
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{ .div = 8, .val = 8, .flags = RATE_IN_242X },
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{ .div = 12, .val = 12, .flags = RATE_IN_242X },
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{ .div = 0 },
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};
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@ -501,15 +460,6 @@ static struct clk dsp_irate_ick = {
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.recalc = &omap2_clksel_recalc,
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};
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/* 2420 only */
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static struct clk dsp_ick = {
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.name = "dsp_ick", /* apparently ipi and isp */
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.ops = &clkops_omap2_dflt_wait,
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.parent = &dsp_irate_ick,
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.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
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.enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
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};
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/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
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static struct clk iva2_1_ick = {
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.name = "iva2_1_ick",
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@ -519,37 +469,6 @@ static struct clk iva2_1_ick = {
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.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
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};
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/*
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* The IVA1 is an ARM7 core on the 2420 that has nothing to do with
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* the C54x, but which is contained in the DSP powerdomain. Does not
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* exist on later OMAPs.
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*/
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static struct clk iva1_ifck = {
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.name = "iva1_ifck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &core_ck,
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.flags = DELAYED_APP,
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.clkdm_name = "iva1_clkdm",
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.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
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.enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
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.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
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.clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
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.clksel = dsp_fck_clksel,
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.recalc = &omap2_clksel_recalc,
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};
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/* IVA1 mpu/int/i/f clocks are /2 of parent */
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static struct clk iva1_mpu_int_ifck = {
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.name = "iva1_mpu_int_ifck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &iva1_ifck,
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.clkdm_name = "iva1_clkdm",
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.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
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.enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
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.fixed_div = 2,
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.recalc = &omap_fixed_divisor_recalc,
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};
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/*
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* L3 clock domain
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* L3 clocks are used for both interface and functional clocks to
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@ -571,12 +490,8 @@ static struct clk iva1_mpu_int_ifck = {
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*/
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static const struct clksel_rate core_l3_core_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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{ .div = 2, .val = 2, .flags = RATE_IN_242X },
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{ .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
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{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
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{ .div = 8, .val = 8, .flags = RATE_IN_242X },
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{ .div = 12, .val = 12, .flags = RATE_IN_242X },
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{ .div = 16, .val = 16, .flags = RATE_IN_242X },
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{ .div = 0 }
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};
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@ -671,8 +586,6 @@ static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
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{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
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{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
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{ .div = 5, .val = 5, .flags = RATE_IN_243X },
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{ .div = 6, .val = 6, .flags = RATE_IN_242X },
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{ .div = 8, .val = 8, .flags = RATE_IN_242X },
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{ .div = 0 }
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};
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@ -1580,26 +1493,6 @@ static struct clk wdt4_fck = {
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.recalc = &followparent_recalc,
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};
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static struct clk wdt3_ick = {
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.name = "wdt3_ick",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &l4_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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.enable_bit = OMAP2420_EN_WDT3_SHIFT,
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.recalc = &followparent_recalc,
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};
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static struct clk wdt3_fck = {
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.name = "wdt3_fck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &func_32k_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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.enable_bit = OMAP2420_EN_WDT3_SHIFT,
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.recalc = &followparent_recalc,
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};
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static struct clk mspro_ick = {
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.name = "mspro_ick",
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.ops = &clkops_omap2_dflt_wait,
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@ -1620,26 +1513,6 @@ static struct clk mspro_fck = {
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.recalc = &followparent_recalc,
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};
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static struct clk mmc_ick = {
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.name = "mmc_ick",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &l4_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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.enable_bit = OMAP2420_EN_MMC_SHIFT,
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.recalc = &followparent_recalc,
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};
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static struct clk mmc_fck = {
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.name = "mmc_fck",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &func_96m_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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.enable_bit = OMAP2420_EN_MMC_SHIFT,
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.recalc = &followparent_recalc,
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};
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static struct clk fac_ick = {
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.name = "fac_ick",
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.ops = &clkops_omap2_dflt_wait,
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@ -1660,26 +1533,6 @@ static struct clk fac_fck = {
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.recalc = &followparent_recalc,
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};
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static struct clk eac_ick = {
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.name = "eac_ick",
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.ops = &clkops_omap2_dflt_wait,
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.parent = &l4_ck,
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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.enable_bit = OMAP2420_EN_EAC_SHIFT,
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.recalc = &followparent_recalc,
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};
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static struct clk eac_fck = {
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.name = "eac_fck",
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.ops = &clkops_omap2_dflt_wait,
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|
|
.parent = &func_96m_ck,
|
|
|
|
|
.clkdm_name = "core_l4_clkdm",
|
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
|
.enable_bit = OMAP2420_EN_EAC_SHIFT,
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk hdq_ick = {
|
|
|
|
|
.name = "hdq_ick",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
@ -1700,6 +1553,10 @@ static struct clk hdq_fck = {
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* XXX This is marked as a 2420-only define, but it claims to be present
|
|
|
|
|
* on 2430 also. Double-check.
|
|
|
|
|
*/
|
|
|
|
|
static struct clk i2c2_ick = {
|
|
|
|
|
.name = "i2c2_ick",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
@ -1710,16 +1567,6 @@ static struct clk i2c2_ick = {
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk i2c2_fck = {
|
|
|
|
|
.name = "i2c2_fck",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
|
.parent = &func_12m_ck,
|
|
|
|
|
.clkdm_name = "core_l4_clkdm",
|
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
|
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk i2chs2_fck = {
|
|
|
|
|
.name = "i2chs2_fck",
|
|
|
|
|
.ops = &clkops_omap2430_i2chs_wait,
|
|
|
|
@ -1730,6 +1577,10 @@ static struct clk i2chs2_fck = {
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* XXX This is marked as a 2420-only define, but it claims to be present
|
|
|
|
|
* on 2430 also. Double-check.
|
|
|
|
|
*/
|
|
|
|
|
static struct clk i2c1_ick = {
|
|
|
|
|
.name = "i2c1_ick",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
@ -1740,16 +1591,6 @@ static struct clk i2c1_ick = {
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk i2c1_fck = {
|
|
|
|
|
.name = "i2c1_fck",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
|
.parent = &func_12m_ck,
|
|
|
|
|
.clkdm_name = "core_l4_clkdm",
|
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
|
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk i2chs1_fck = {
|
|
|
|
|
.name = "i2chs1_fck",
|
|
|
|
|
.ops = &clkops_omap2430_i2chs_wait,
|
|
|
|
@ -1785,58 +1626,6 @@ static struct clk sdma_ick = {
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk vlynq_ick = {
|
|
|
|
|
.name = "vlynq_ick",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
|
.parent = &core_l3_ck,
|
|
|
|
|
.clkdm_name = "core_l3_clkdm",
|
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
|
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
|
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct clksel_rate vlynq_fck_96m_rates[] = {
|
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
|
|
|
|
|
{ .div = 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct clksel_rate vlynq_fck_core_rates[] = {
|
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 3, .val = 3, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 6, .val = 6, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 8, .val = 8, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 9, .val = 9, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 12, .val = 12, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
|
|
|
|
|
{ .div = 18, .val = 18, .flags = RATE_IN_242X },
|
|
|
|
|
{ .div = 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct clksel vlynq_fck_clksel[] = {
|
|
|
|
|
{ .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
|
|
|
|
|
{ .parent = &core_ck, .rates = vlynq_fck_core_rates },
|
|
|
|
|
{ .parent = NULL }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk vlynq_fck = {
|
|
|
|
|
.name = "vlynq_fck",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
|
.parent = &func_96m_ck,
|
|
|
|
|
.flags = DELAYED_APP,
|
|
|
|
|
.clkdm_name = "core_l3_clkdm",
|
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
|
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
|
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
|
|
|
|
|
.clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
|
|
|
|
|
.clksel = vlynq_fck_clksel,
|
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
|
|
.set_rate = &omap2_clksel_set_rate
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct clk sdrc_ick = {
|
|
|
|
|
.name = "sdrc_ick",
|
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
@ -2035,149 +1824,134 @@ static struct clk virt_prcm_set = {
|
|
|
|
|
* clkdev integration
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static struct omap_clk omap24xx_clks[] = {
|
|
|
|
|
static struct omap_clk omap2430_clks[] = {
|
|
|
|
|
/* external root sources */
|
|
|
|
|
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "osc_ck", &osc_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "sys_ck", &sys_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "alt_ck", &alt_ck, CK_243X),
|
|
|
|
|
/* internal analog sources */
|
|
|
|
|
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
|
|
|
|
|
/* internal prcm root sources */
|
|
|
|
|
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
|
|
|
|
|
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
|
|
|
|
|
CLK(NULL, "emul_ck", &emul_ck, CK_242X),
|
|
|
|
|
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "core_ck", &core_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
|
|
|
|
|
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
|
|
|
|
|
CLK(NULL, "emul_ck", &emul_ck, CK_243X),
|
|
|
|
|
/* mpu domain clocks */
|
|
|
|
|
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
|
|
|
|
|
/* dsp domain clocks */
|
|
|
|
|
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
|
|
|
|
|
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
|
|
|
|
|
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
|
|
|
|
|
/* GFX domain clocks */
|
|
|
|
|
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
|
|
|
|
|
/* Modem domain clocks */
|
|
|
|
|
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
|
|
|
|
|
/* DSS domain clocks */
|
|
|
|
|
CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omapdss", "ick", &dss_ick, CK_243X),
|
|
|
|
|
CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X),
|
|
|
|
|
CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X),
|
|
|
|
|
CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X),
|
|
|
|
|
/* L3 domain clocks */
|
|
|
|
|
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
|
|
|
|
|
/* L4 domain clocks */
|
|
|
|
|
CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "l4_ck", &l4_ck, CK_243X),
|
|
|
|
|
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
|
|
|
|
|
/* virtual meta-group clock */
|
|
|
|
|
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
|
|
|
|
|
/* general l4 interface ck, multi-parent functional clk */
|
|
|
|
|
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
|
|
|
|
|
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
|
|
|
|
|
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
|
|
|
|
|
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X),
|
|
|
|
|
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
|
|
|
|
|
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X),
|
|
|
|
|
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
|
|
|
|
|
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
|
|
|
|
|
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
|
|
|
|
|
CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
|
|
|
|
|
CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
|
|
|
|
|
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
|
|
|
|
|
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
|
|
|
|
|
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
|
|
|
|
|
CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
|
|
|
|
|
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
|
|
|
|
|
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
|
|
|
|
|
CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
|
|
|
|
|
CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "fac_ick", &fac_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
|
|
|
|
|
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
|
|
|
|
|
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
|
|
|
|
|
CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X),
|
|
|
|
|
CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
|
|
|
|
|
CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
|
|
|
|
|
CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X),
|
|
|
|
|
CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
|
|
|
|
|
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
|
|
|
|
|
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
|
|
|
|
|
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
|
|
|
|
|
CLK(NULL, "des_ick", &des_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "sha_ick", &sha_ick, CK_243X),
|
|
|
|
|
CLK("omap_rng", "ick", &rng_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "aes_ick", &aes_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
|
|
|
|
|
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
|
|
|
|
|
CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
|
|
|
|
|
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
|
|
|
|
|
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
|
|
|
|
@ -2194,28 +1968,21 @@ static struct omap_clk omap24xx_clks[] = {
|
|
|
|
|
* init code
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
int __init omap2xxx_clk_init(void)
|
|
|
|
|
int __init omap2430_clk_init(void)
|
|
|
|
|
{
|
|
|
|
|
const struct prcm_config *prcm;
|
|
|
|
|
struct omap_clk *c;
|
|
|
|
|
u32 clkrate;
|
|
|
|
|
u16 cpu_clkflg;
|
|
|
|
|
|
|
|
|
|
if (cpu_is_omap242x()) {
|
|
|
|
|
prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
|
|
|
|
|
cpu_mask = RATE_IN_242X;
|
|
|
|
|
cpu_clkflg = CK_242X;
|
|
|
|
|
rate_table = omap2420_rate_table;
|
|
|
|
|
} else if (cpu_is_omap2430()) {
|
|
|
|
|
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
|
|
|
|
|
cpu_mask = RATE_IN_243X;
|
|
|
|
|
cpu_clkflg = CK_243X;
|
|
|
|
|
rate_table = omap2430_rate_table;
|
|
|
|
|
}
|
|
|
|
|
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
|
|
|
|
|
cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
|
|
|
|
|
cpu_mask = RATE_IN_243X;
|
|
|
|
|
rate_table = omap2430_rate_table;
|
|
|
|
|
|
|
|
|
|
clk_init(&omap2_clk_functions);
|
|
|
|
|
|
|
|
|
|
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
|
|
|
|
|
for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
|
|
|
|
|
c++)
|
|
|
|
|
clk_preinit(c->lk.clk);
|
|
|
|
|
|
|
|
|
|
osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
|
|
|
|
@ -2223,12 +1990,12 @@ int __init omap2xxx_clk_init(void)
|
|
|
|
|
sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
|
|
|
|
|
propagate_rate(&sys_ck);
|
|
|
|
|
|
|
|
|
|
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
|
|
|
|
|
if (c->cpu & cpu_clkflg) {
|
|
|
|
|
clkdev_add(&c->lk);
|
|
|
|
|
clk_register(c->lk.clk);
|
|
|
|
|
omap2_init_clk_clkdm(c->lk.clk);
|
|
|
|
|
}
|
|
|
|
|
for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
|
|
|
|
|
c++) {
|
|
|
|
|
clkdev_add(&c->lk);
|
|
|
|
|
clk_register(c->lk.clk);
|
|
|
|
|
omap2_init_clk_clkdm(c->lk.clk);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check the MPU rate set by bootloader */
|
|
|
|
|
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
|
|
|
|
@ -2244,10 +2011,9 @@ int __init omap2xxx_clk_init(void)
|
|
|
|
|
|
|
|
|
|
recalculate_root_clocks();
|
|
|
|
|
|
|
|
|
|
printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
|
|
|
|
|
"%ld.%01ld/%ld/%ld MHz\n",
|
|
|
|
|
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
|
|
|
|
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
|
|
|
|
pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
|
|
|
|
|
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
|
|
|
|
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Only enable those clocks we will need, let the drivers
|