C6X: clocks
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs feeding into the cores or peripheral clock domains. The hardware is very similar to arm/mach-davinci clocks. This is still a work in progress which needs to be updated once device tree clock binding changes shake out. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Mark Salter
parent
e94e668251
commit
81ec988981
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#ifndef _ASM_CLKDEV_H
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#define _ASM_CLKDEV_H
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#include <linux/slab.h>
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struct clk;
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static inline int __clk_get(struct clk *clk)
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{
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return 1;
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}
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static inline void __clk_put(struct clk *clk)
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{
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}
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static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
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{
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return kzalloc(size, GFP_KERNEL);
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}
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#endif /* _ASM_CLKDEV_H */
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/*
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* TI C64X clock definitions
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*
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* Copyright (C) 2010, 2011 Texas Instruments.
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* Contributed by: Mark Salter <msalter@redhat.com>
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*
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* Copied heavily from arm/mach-davinci/clock.h, so:
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_C6X_CLOCK_H
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#define _ASM_C6X_CLOCK_H
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#ifndef __ASSEMBLER__
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#include <linux/list.h>
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/* PLL/Reset register offsets */
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#define PLLCTL 0x100
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#define PLLM 0x110
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#define PLLPRE 0x114
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#define PLLDIV1 0x118
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#define PLLDIV2 0x11c
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#define PLLDIV3 0x120
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#define PLLPOST 0x128
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#define PLLCMD 0x138
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#define PLLSTAT 0x13c
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#define PLLALNCTL 0x140
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#define PLLDCHANGE 0x144
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#define PLLCKEN 0x148
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#define PLLCKSTAT 0x14c
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#define PLLSYSTAT 0x150
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#define PLLDIV4 0x160
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#define PLLDIV5 0x164
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#define PLLDIV6 0x168
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#define PLLDIV7 0x16c
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#define PLLDIV8 0x170
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#define PLLDIV9 0x174
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#define PLLDIV10 0x178
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#define PLLDIV11 0x17c
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#define PLLDIV12 0x180
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#define PLLDIV13 0x184
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#define PLLDIV14 0x188
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#define PLLDIV15 0x18c
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#define PLLDIV16 0x190
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/* PLLM register bits */
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#define PLLM_PLLM_MASK 0xff
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#define PLLM_VAL(x) ((x) - 1)
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/* PREDIV register bits */
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#define PLLPREDIV_EN BIT(15)
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#define PLLPREDIV_VAL(x) ((x) - 1)
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/* PLLCTL register bits */
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#define PLLCTL_PLLEN BIT(0)
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#define PLLCTL_PLLPWRDN BIT(1)
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#define PLLCTL_PLLRST BIT(3)
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#define PLLCTL_PLLDIS BIT(4)
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#define PLLCTL_PLLENSRC BIT(5)
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#define PLLCTL_CLKMODE BIT(8)
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/* PLLCMD register bits */
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#define PLLCMD_GOSTAT BIT(0)
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/* PLLSTAT register bits */
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#define PLLSTAT_GOSTAT BIT(0)
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/* PLLDIV register bits */
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#define PLLDIV_EN BIT(15)
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#define PLLDIV_RATIO_MASK 0x1f
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#define PLLDIV_RATIO(x) ((x) - 1)
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struct pll_data;
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struct clk {
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struct list_head node;
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struct module *owner;
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const char *name;
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unsigned long rate;
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int usecount;
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u32 flags;
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struct clk *parent;
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struct list_head children; /* list of children */
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struct list_head childnode; /* parent's child list node */
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struct pll_data *pll_data;
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u32 div;
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unsigned long (*recalc) (struct clk *);
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int (*set_rate) (struct clk *clk, unsigned long rate);
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int (*round_rate) (struct clk *clk, unsigned long rate);
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};
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/* Clock flags: SoC-specific flags start at BIT(16) */
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#define ALWAYS_ENABLED BIT(1)
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#define CLK_PLL BIT(2) /* PLL-derived clock */
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#define PRE_PLL BIT(3) /* source is before PLL mult/div */
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#define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
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#define FIXED_RATE_PLL BIT(5) /* fixed ouput rate PLL */
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#define MAX_PLL_SYSCLKS 16
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struct pll_data {
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void __iomem *base;
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u32 num;
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u32 flags;
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u32 input_rate;
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u32 bypass_delay; /* in loops */
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u32 reset_delay; /* in loops */
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u32 lock_delay; /* in loops */
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struct clk sysclks[MAX_PLL_SYSCLKS + 1];
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};
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/* pll_data flag bit */
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#define PLL_HAS_PRE BIT(0)
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#define PLL_HAS_MUL BIT(1)
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#define PLL_HAS_POST BIT(2)
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#define CLK(dev, con, ck) \
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{ \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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} \
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extern void c6x_clks_init(struct clk_lookup *clocks);
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extern int clk_register(struct clk *clk);
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extern void clk_unregister(struct clk *clk);
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extern void c64x_setup_clocks(void);
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extern struct pll_data c6x_soc_pll1;
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extern struct clk clkin1;
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extern struct clk c6x_core_clk;
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extern struct clk c6x_i2c_clk;
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extern struct clk c6x_watchdog_clk;
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extern struct clk c6x_mcbsp1_clk;
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extern struct clk c6x_mcbsp2_clk;
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extern struct clk c6x_mdio_clk;
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#endif
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#endif /* _ASM_C6X_CLOCK_H */
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/*
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* Clock and PLL control for C64x+ devices
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*
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* Copyright (C) 2010, 2011 Texas Instruments.
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* Contributed by: Mark Salter <msalter@redhat.com>
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*
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* Copied heavily from arm/mach-davinci/clock.c, so:
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <asm/clock.h>
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#include <asm/soc.h>
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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static DEFINE_SPINLOCK(clockfw_lock);
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static void __clk_enable(struct clk *clk)
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{
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if (clk->parent)
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__clk_enable(clk->parent);
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clk->usecount++;
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}
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static void __clk_disable(struct clk *clk)
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{
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if (WARN_ON(clk->usecount == 0))
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return;
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--clk->usecount;
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (clk->round_rate)
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return clk->round_rate(clk, rate);
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_round_rate);
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/* Propagate rate to children */
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static void propagate_rate(struct clk *root)
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{
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struct clk *clk;
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list_for_each_entry(clk, &root->children, childnode) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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}
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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int ret = -EINVAL;
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if (clk == NULL || IS_ERR(clk))
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return ret;
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if (clk->set_rate)
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ret = clk->set_rate(clk, rate);
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spin_lock_irqsave(&clockfw_lock, flags);
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if (ret == 0) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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/* Cannot change parent on enabled clock */
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if (WARN_ON(clk->usecount))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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clk->parent = parent;
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list_del_init(&clk->childnode);
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list_add(&clk->childnode, &clk->parent->children);
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mutex_unlock(&clocks_mutex);
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spin_lock_irqsave(&clockfw_lock, flags);
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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int clk_register(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (WARN(clk->parent && !clk->parent->rate,
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"CLK: %s parent %s has no rate!\n",
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clk->name, clk->parent->name))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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list_add_tail(&clk->node, &clocks);
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if (clk->parent)
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list_add_tail(&clk->childnode, &clk->parent->children);
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mutex_unlock(&clocks_mutex);
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/* If rate is already set, use it */
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if (clk->rate)
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return 0;
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/* Else, see if there is a way to calculate it */
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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/* Otherwise, default to parent rate */
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else if (clk->parent)
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clk->rate = clk->parent->rate;
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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void clk_unregister(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return;
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mutex_lock(&clocks_mutex);
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list_del(&clk->node);
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list_del(&clk->childnode);
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mutex_unlock(&clocks_mutex);
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}
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EXPORT_SYMBOL(clk_unregister);
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static u32 pll_read(struct pll_data *pll, int reg)
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{
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return soc_readl(pll->base + reg);
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}
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static unsigned long clk_sysclk_recalc(struct clk *clk)
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{
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u32 v, plldiv = 0;
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struct pll_data *pll;
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unsigned long rate = clk->rate;
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if (WARN_ON(!clk->parent))
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return rate;
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rate = clk->parent->rate;
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/* the parent must be a PLL */
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if (WARN_ON(!clk->parent->pll_data))
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return rate;
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pll = clk->parent->pll_data;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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rate = pll->input_rate;
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if (!clk->div) {
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pr_debug("%s: (no divider) rate = %lu KHz\n",
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clk->name, rate / 1000);
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return rate;
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}
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if (clk->flags & FIXED_DIV_PLL) {
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rate /= clk->div;
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pr_debug("%s: (fixed divide by %d) rate = %lu KHz\n",
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clk->name, clk->div, rate / 1000);
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return rate;
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}
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v = pll_read(pll, clk->div);
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if (v & PLLDIV_EN)
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plldiv = (v & PLLDIV_RATIO_MASK) + 1;
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if (plldiv == 0)
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plldiv = 1;
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rate /= plldiv;
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pr_debug("%s: (divide by %d) rate = %lu KHz\n",
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clk->name, plldiv, rate / 1000);
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return rate;
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}
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static unsigned long clk_leafclk_recalc(struct clk *clk)
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{
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if (WARN_ON(!clk->parent))
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return clk->rate;
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pr_debug("%s: (parent %s) rate = %lu KHz\n",
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clk->name, clk->parent->name, clk->parent->rate / 1000);
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return clk->parent->rate;
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}
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static unsigned long clk_pllclk_recalc(struct clk *clk)
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{
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u32 ctrl, mult = 0, prediv = 0, postdiv = 0;
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u8 bypass;
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struct pll_data *pll = clk->pll_data;
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unsigned long rate = clk->rate;
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if (clk->flags & FIXED_RATE_PLL)
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return rate;
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ctrl = pll_read(pll, PLLCTL);
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rate = pll->input_rate = clk->parent->rate;
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if (ctrl & PLLCTL_PLLEN)
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bypass = 0;
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else
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bypass = 1;
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if (pll->flags & PLL_HAS_MUL) {
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mult = pll_read(pll, PLLM);
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mult = (mult & PLLM_PLLM_MASK) + 1;
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}
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if (pll->flags & PLL_HAS_PRE) {
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prediv = pll_read(pll, PLLPRE);
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if (prediv & PLLDIV_EN)
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prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
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else
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prediv = 0;
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}
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if (pll->flags & PLL_HAS_POST) {
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postdiv = pll_read(pll, PLLPOST);
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if (postdiv & PLLDIV_EN)
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postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
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else
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postdiv = 1;
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}
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if (!bypass) {
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if (prediv)
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rate /= prediv;
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if (mult)
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rate *= mult;
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if (postdiv)
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rate /= postdiv;
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pr_debug("PLL%d: input = %luMHz, pre[%d] mul[%d] post[%d] "
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"--> %luMHz output.\n",
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pll->num, clk->parent->rate / 1000000,
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prediv, mult, postdiv, rate / 1000000);
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} else
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pr_debug("PLL%d: input = %luMHz, bypass mode.\n",
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pll->num, clk->parent->rate / 1000000);
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return rate;
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}
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static void __init __init_clk(struct clk *clk)
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{
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INIT_LIST_HEAD(&clk->node);
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INIT_LIST_HEAD(&clk->children);
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INIT_LIST_HEAD(&clk->childnode);
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if (!clk->recalc) {
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/* Check if clock is a PLL */
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if (clk->pll_data)
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clk->recalc = clk_pllclk_recalc;
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/* Else, if it is a PLL-derived clock */
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else if (clk->flags & CLK_PLL)
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clk->recalc = clk_sysclk_recalc;
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|
||||
/* Otherwise, it is a leaf clock (PSC clock) */
|
||||
else if (clk->parent)
|
||||
clk->recalc = clk_leafclk_recalc;
|
||||
}
|
||||
}
|
||||
|
||||
void __init c6x_clks_init(struct clk_lookup *clocks)
|
||||
{
|
||||
struct clk_lookup *c;
|
||||
struct clk *clk;
|
||||
size_t num_clocks = 0;
|
||||
|
||||
for (c = clocks; c->clk; c++) {
|
||||
clk = c->clk;
|
||||
|
||||
__init_clk(clk);
|
||||
clk_register(clk);
|
||||
num_clocks++;
|
||||
|
||||
/* Turn on clocks that Linux doesn't otherwise manage */
|
||||
if (clk->flags & ALWAYS_ENABLED)
|
||||
clk_enable(clk);
|
||||
}
|
||||
|
||||
clkdev_add_table(clocks, num_clocks);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
#define CLKNAME_MAX 10 /* longest clock name */
|
||||
#define NEST_DELTA 2
|
||||
#define NEST_MAX 4
|
||||
|
||||
static void
|
||||
dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
|
||||
{
|
||||
char *state;
|
||||
char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
|
||||
struct clk *clk;
|
||||
unsigned i;
|
||||
|
||||
if (parent->flags & CLK_PLL)
|
||||
state = "pll";
|
||||
else
|
||||
state = "";
|
||||
|
||||
/* <nest spaces> name <pad to end> */
|
||||
memset(buf, ' ', sizeof(buf) - 1);
|
||||
buf[sizeof(buf) - 1] = 0;
|
||||
i = strlen(parent->name);
|
||||
memcpy(buf + nest, parent->name,
|
||||
min(i, (unsigned)(sizeof(buf) - 1 - nest)));
|
||||
|
||||
seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
|
||||
buf, parent->usecount, state, clk_get_rate(parent));
|
||||
/* REVISIT show device associations too */
|
||||
|
||||
/* cost is now small, but not linear... */
|
||||
list_for_each_entry(clk, &parent->children, childnode) {
|
||||
dump_clock(s, nest + NEST_DELTA, clk);
|
||||
}
|
||||
}
|
||||
|
||||
static int c6x_ck_show(struct seq_file *m, void *v)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
/*
|
||||
* Show clock tree; We trust nonzero usecounts equate to PSC enables...
|
||||
*/
|
||||
mutex_lock(&clocks_mutex);
|
||||
list_for_each_entry(clk, &clocks, node)
|
||||
if (!clk->parent)
|
||||
dump_clock(m, 0, clk);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int c6x_ck_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, c6x_ck_show, NULL);
|
||||
}
|
||||
|
||||
static const struct file_operations c6x_ck_operations = {
|
||||
.open = c6x_ck_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int __init c6x_clk_debugfs_init(void)
|
||||
{
|
||||
debugfs_create_file("c6x_clocks", S_IFREG | S_IRUGO, NULL, NULL,
|
||||
&c6x_ck_operations);
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(c6x_clk_debugfs_init);
|
||||
#endif /* CONFIG_DEBUG_FS */
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
/*
|
||||
* Port on Texas Instruments TMS320C6x architecture
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated
|
||||
* Author: Mark Salter <msalter@redhat.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <asm/clock.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
/*
|
||||
* Common SoC clock support.
|
||||
*/
|
||||
|
||||
/* Default input for PLL1 */
|
||||
struct clk clkin1 = {
|
||||
.name = "clkin1",
|
||||
.node = LIST_HEAD_INIT(clkin1.node),
|
||||
.children = LIST_HEAD_INIT(clkin1.children),
|
||||
.childnode = LIST_HEAD_INIT(clkin1.childnode),
|
||||
};
|
||||
|
||||
struct pll_data c6x_soc_pll1 = {
|
||||
.num = 1,
|
||||
.sysclks = {
|
||||
{
|
||||
.name = "pll1",
|
||||
.parent = &clkin1,
|
||||
.pll_data = &c6x_soc_pll1,
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk1",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk2",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk3",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk4",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk5",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk6",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk7",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk8",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk9",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk10",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk11",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk12",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk13",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk14",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk15",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
{
|
||||
.name = "pll1_sysclk16",
|
||||
.parent = &c6x_soc_pll1.sysclks[0],
|
||||
.flags = CLK_PLL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* CPU core clock */
|
||||
struct clk c6x_core_clk = {
|
||||
.name = "core",
|
||||
};
|
||||
|
||||
/* miscellaneous IO clocks */
|
||||
struct clk c6x_i2c_clk = {
|
||||
.name = "i2c",
|
||||
};
|
||||
|
||||
struct clk c6x_watchdog_clk = {
|
||||
.name = "watchdog",
|
||||
};
|
||||
|
||||
struct clk c6x_mcbsp1_clk = {
|
||||
.name = "mcbsp1",
|
||||
};
|
||||
|
||||
struct clk c6x_mcbsp2_clk = {
|
||||
.name = "mcbsp2",
|
||||
};
|
||||
|
||||
struct clk c6x_mdio_clk = {
|
||||
.name = "mdio",
|
||||
};
|
||||
|
||||
|
||||
#ifdef CONFIG_SOC_TMS320C6455
|
||||
static struct clk_lookup c6455_clks[] = {
|
||||
CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
|
||||
CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
|
||||
CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
|
||||
CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
|
||||
CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
|
||||
CLK(NULL, "core", &c6x_core_clk),
|
||||
CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
|
||||
CLK("watchdog", NULL, &c6x_watchdog_clk),
|
||||
CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
|
||||
CLK("", NULL, NULL)
|
||||
};
|
||||
|
||||
|
||||
static void __init c6455_setup_clocks(struct device_node *node)
|
||||
{
|
||||
struct pll_data *pll = &c6x_soc_pll1;
|
||||
struct clk *sysclks = pll->sysclks;
|
||||
|
||||
pll->flags = PLL_HAS_PRE | PLL_HAS_MUL;
|
||||
|
||||
sysclks[2].flags |= FIXED_DIV_PLL;
|
||||
sysclks[2].div = 3;
|
||||
sysclks[3].flags |= FIXED_DIV_PLL;
|
||||
sysclks[3].div = 6;
|
||||
sysclks[4].div = PLLDIV4;
|
||||
sysclks[5].div = PLLDIV5;
|
||||
|
||||
c6x_core_clk.parent = &sysclks[0];
|
||||
c6x_i2c_clk.parent = &sysclks[3];
|
||||
c6x_watchdog_clk.parent = &sysclks[3];
|
||||
c6x_mdio_clk.parent = &sysclks[3];
|
||||
|
||||
c6x_clks_init(c6455_clks);
|
||||
}
|
||||
#endif /* CONFIG_SOC_TMS320C6455 */
|
||||
|
||||
#ifdef CONFIG_SOC_TMS320C6457
|
||||
static struct clk_lookup c6457_clks[] = {
|
||||
CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
|
||||
CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
|
||||
CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
|
||||
CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
|
||||
CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
|
||||
CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
|
||||
CLK(NULL, "core", &c6x_core_clk),
|
||||
CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
|
||||
CLK("watchdog", NULL, &c6x_watchdog_clk),
|
||||
CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
|
||||
CLK("", NULL, NULL)
|
||||
};
|
||||
|
||||
static void __init c6457_setup_clocks(struct device_node *node)
|
||||
{
|
||||
struct pll_data *pll = &c6x_soc_pll1;
|
||||
struct clk *sysclks = pll->sysclks;
|
||||
|
||||
pll->flags = PLL_HAS_MUL | PLL_HAS_POST;
|
||||
|
||||
sysclks[1].flags |= FIXED_DIV_PLL;
|
||||
sysclks[1].div = 1;
|
||||
sysclks[2].flags |= FIXED_DIV_PLL;
|
||||
sysclks[2].div = 3;
|
||||
sysclks[3].flags |= FIXED_DIV_PLL;
|
||||
sysclks[3].div = 6;
|
||||
sysclks[4].div = PLLDIV4;
|
||||
sysclks[5].div = PLLDIV5;
|
||||
|
||||
c6x_core_clk.parent = &sysclks[1];
|
||||
c6x_i2c_clk.parent = &sysclks[3];
|
||||
c6x_watchdog_clk.parent = &sysclks[5];
|
||||
c6x_mdio_clk.parent = &sysclks[5];
|
||||
|
||||
c6x_clks_init(c6457_clks);
|
||||
}
|
||||
#endif /* CONFIG_SOC_TMS320C6455 */
|
||||
|
||||
#ifdef CONFIG_SOC_TMS320C6472
|
||||
static struct clk_lookup c6472_clks[] = {
|
||||
CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
|
||||
CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
|
||||
CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
|
||||
CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
|
||||
CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
|
||||
CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
|
||||
CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
|
||||
CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
|
||||
CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
|
||||
CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
|
||||
CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
|
||||
CLK(NULL, "core", &c6x_core_clk),
|
||||
CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
|
||||
CLK("watchdog", NULL, &c6x_watchdog_clk),
|
||||
CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
|
||||
CLK("", NULL, NULL)
|
||||
};
|
||||
|
||||
/* assumptions used for delay loop calculations */
|
||||
#define MIN_CLKIN1_KHz 15625
|
||||
#define MAX_CORE_KHz 700000
|
||||
#define MIN_PLLOUT_KHz MIN_CLKIN1_KHz
|
||||
|
||||
static void __init c6472_setup_clocks(struct device_node *node)
|
||||
{
|
||||
struct pll_data *pll = &c6x_soc_pll1;
|
||||
struct clk *sysclks = pll->sysclks;
|
||||
int i;
|
||||
|
||||
pll->flags = PLL_HAS_MUL;
|
||||
|
||||
for (i = 1; i <= 6; i++) {
|
||||
sysclks[i].flags |= FIXED_DIV_PLL;
|
||||
sysclks[i].div = 1;
|
||||
}
|
||||
|
||||
sysclks[7].flags |= FIXED_DIV_PLL;
|
||||
sysclks[7].div = 3;
|
||||
sysclks[8].flags |= FIXED_DIV_PLL;
|
||||
sysclks[8].div = 6;
|
||||
sysclks[9].flags |= FIXED_DIV_PLL;
|
||||
sysclks[9].div = 2;
|
||||
sysclks[10].div = PLLDIV10;
|
||||
|
||||
c6x_core_clk.parent = &sysclks[get_coreid() + 1];
|
||||
c6x_i2c_clk.parent = &sysclks[8];
|
||||
c6x_watchdog_clk.parent = &sysclks[8];
|
||||
c6x_mdio_clk.parent = &sysclks[5];
|
||||
|
||||
c6x_clks_init(c6472_clks);
|
||||
}
|
||||
#endif /* CONFIG_SOC_TMS320C6472 */
|
||||
|
||||
|
||||
#ifdef CONFIG_SOC_TMS320C6474
|
||||
static struct clk_lookup c6474_clks[] = {
|
||||
CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
|
||||
CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
|
||||
CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
|
||||
CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
|
||||
CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
|
||||
CLK(NULL, "pll1_sysclk12", &c6x_soc_pll1.sysclks[12]),
|
||||
CLK(NULL, "pll1_sysclk13", &c6x_soc_pll1.sysclks[13]),
|
||||
CLK(NULL, "core", &c6x_core_clk),
|
||||
CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
|
||||
CLK("mcbsp.1", NULL, &c6x_mcbsp1_clk),
|
||||
CLK("mcbsp.2", NULL, &c6x_mcbsp2_clk),
|
||||
CLK("watchdog", NULL, &c6x_watchdog_clk),
|
||||
CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
|
||||
CLK("", NULL, NULL)
|
||||
};
|
||||
|
||||
static void __init c6474_setup_clocks(struct device_node *node)
|
||||
{
|
||||
struct pll_data *pll = &c6x_soc_pll1;
|
||||
struct clk *sysclks = pll->sysclks;
|
||||
|
||||
pll->flags = PLL_HAS_MUL;
|
||||
|
||||
sysclks[7].flags |= FIXED_DIV_PLL;
|
||||
sysclks[7].div = 1;
|
||||
sysclks[9].flags |= FIXED_DIV_PLL;
|
||||
sysclks[9].div = 3;
|
||||
sysclks[10].flags |= FIXED_DIV_PLL;
|
||||
sysclks[10].div = 6;
|
||||
|
||||
sysclks[11].div = PLLDIV11;
|
||||
|
||||
sysclks[12].flags |= FIXED_DIV_PLL;
|
||||
sysclks[12].div = 2;
|
||||
|
||||
sysclks[13].div = PLLDIV13;
|
||||
|
||||
c6x_core_clk.parent = &sysclks[7];
|
||||
c6x_i2c_clk.parent = &sysclks[10];
|
||||
c6x_watchdog_clk.parent = &sysclks[10];
|
||||
c6x_mcbsp1_clk.parent = &sysclks[10];
|
||||
c6x_mcbsp2_clk.parent = &sysclks[10];
|
||||
|
||||
c6x_clks_init(c6474_clks);
|
||||
}
|
||||
#endif /* CONFIG_SOC_TMS320C6474 */
|
||||
|
||||
static struct of_device_id c6x_clkc_match[] __initdata = {
|
||||
#ifdef CONFIG_SOC_TMS320C6455
|
||||
{ .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_TMS320C6457
|
||||
{ .compatible = "ti,c6457-pll", .data = c6457_setup_clocks },
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_TMS320C6472
|
||||
{ .compatible = "ti,c6472-pll", .data = c6472_setup_clocks },
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_TMS320C6474
|
||||
{ .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
|
||||
#endif
|
||||
{ .compatible = "ti,c64x+pll" },
|
||||
{}
|
||||
};
|
||||
|
||||
void __init c64x_setup_clocks(void)
|
||||
{
|
||||
void (*__setup_clocks)(struct device_node *np);
|
||||
struct pll_data *pll = &c6x_soc_pll1;
|
||||
struct device_node *node;
|
||||
const struct of_device_id *id;
|
||||
int err;
|
||||
u32 val;
|
||||
|
||||
node = of_find_matching_node(NULL, c6x_clkc_match);
|
||||
if (!node)
|
||||
return;
|
||||
|
||||
pll->base = of_iomap(node, 0);
|
||||
if (!pll->base)
|
||||
goto out;
|
||||
|
||||
err = of_property_read_u32(node, "clock-frequency", &val);
|
||||
if (err || val == 0) {
|
||||
pr_err("%s: no clock-frequency found! Using %dMHz\n",
|
||||
node->full_name, (int)val / 1000000);
|
||||
val = 25000000;
|
||||
}
|
||||
clkin1.rate = val;
|
||||
|
||||
err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val);
|
||||
if (err)
|
||||
val = 5000;
|
||||
pll->bypass_delay = val;
|
||||
|
||||
err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val);
|
||||
if (err)
|
||||
val = 30000;
|
||||
pll->reset_delay = val;
|
||||
|
||||
err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val);
|
||||
if (err)
|
||||
val = 30000;
|
||||
pll->lock_delay = val;
|
||||
|
||||
/* id->data is a pointer to SoC-specific setup */
|
||||
id = of_match_node(c6x_clkc_match, node);
|
||||
if (id && id->data) {
|
||||
__setup_clocks = id->data;
|
||||
__setup_clocks(node);
|
||||
}
|
||||
|
||||
out:
|
||||
of_node_put(node);
|
||||
}
|
||||
Loading…
Reference in New Issue