ixgbe: Cleanup configuration of FCoE registers
This change makes it so we always use the FCoE redirection table. We just set all 8 entries to the same value in the case of only having one queue for FCoE. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -618,6 +618,7 @@ void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
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struct ixgbe_fcoe *fcoe = &adapter->fcoe;
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struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
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unsigned int cpu;
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u32 etqf;
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if (!fcoe->pool) {
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spin_lock_init(&fcoe->lock);
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@ -665,40 +666,43 @@ void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
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}
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}
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/* Enable L2 eth type filter for FCoE */
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IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE),
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(ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN));
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/* Enable L2 eth type filter for FIP */
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IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FIP),
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(ETH_P_FIP | IXGBE_ETQF_FILTER_EN));
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if (adapter->ring_feature[RING_F_FCOE].indices) {
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/* Use multiple rx queues for FCoE by redirection table */
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for (i = 0; i < IXGBE_FCRETA_SIZE; i++) {
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fcoe_i = f->offset + i % f->indices;
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fcoe_i &= IXGBE_FCRETA_ENTRY_MASK;
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fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
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IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q);
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}
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IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA);
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IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0);
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} else {
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/* Use single rx queue for FCoE */
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fcoe_i = f->offset;
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fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
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IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0);
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IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE),
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IXGBE_ETQS_QUEUE_EN |
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(fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
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/* Enable L2 EtherType filter for FCoE, necessary for FCoE Rx CRC */
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etqf = ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN;
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if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
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etqf |= IXGBE_ETQF_POOL_ENABLE;
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etqf |= VMDQ_P(0) << IXGBE_ETQF_POOL_SHIFT;
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}
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/* send FIP frames to the first FCoE queue */
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fcoe_i = f->offset;
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fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
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IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE), etqf);
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IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0);
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/* Use one or more Rx queues for FCoE by redirection table */
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for (i = 0; i < IXGBE_FCRETA_SIZE; i++) {
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fcoe_i = f->offset + (i % f->indices);
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fcoe_i &= IXGBE_FCRETA_ENTRY_MASK;
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fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
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IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q);
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}
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IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA);
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/* Enable L2 EtherType filter for FIP */
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etqf = ETH_P_FIP | IXGBE_ETQF_FILTER_EN;
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if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
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etqf |= IXGBE_ETQF_POOL_ENABLE;
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etqf |= VMDQ_P(0) << IXGBE_ETQF_POOL_SHIFT;
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}
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IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FIP), etqf);
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/* Send FIP frames to the first FCoE queue */
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fcoe_q = adapter->rx_ring[f->offset]->reg_idx;
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IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP),
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IXGBE_ETQS_QUEUE_EN |
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(fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
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IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, IXGBE_FCRXCTRL_FCCRCBO |
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/* Configure FCoE Rx control */
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IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
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IXGBE_FCRXCTRL_FCCRCBO |
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(FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT));
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return;
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out_pcpu_noddp_extra_buff_alloc_fail:
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free_percpu(fcoe->pcpu_noddp);
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@ -1452,6 +1452,7 @@ enum {
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#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
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#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
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#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
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#define IXGBE_ETQF_POOL_SHIFT 20
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#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
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#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
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