ARM: tegra: Core code changes for v3.20
This contains a couple of preparatory patches for 64-bit support. A new feature is implemented in the power-management controller which allows it to switch off the SoC if it overheats. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJUwm1UAAoJEN0jrNd/PrOhcHgP/3DS5OrGHUUg8yokvWG5suA7 Bfj0b4t64/k+ZJL3C3vZJxlgXqBkOFLjPgCFagGlliEJtbVvOQLqGwtdypTwoMpa Y1pje+45cCl5KZvDN4D0i1dJDGZqV82Xck6FE7xyJev9FmwADvUFNQB91BykM8rw 42FW20Q0dUpFNMTeOWWBW84+D0JEC79wP/FWjWzKgxJQ6ydLwX8DWk5U5AmzX7A/ Gv/fJlaFp4ti+leRWIqkkNRy72mSZwvizprmgVTX4k3BJt7PagfUjB1r12+pDpLJ dxsJSjEqgnJK00JlmiJLSZkzXtvGu2OSmgt7Sa3k/1vIQXERMv5AWr9QgkXyUv/E SnzoRRb3q6xfyjs6KWEpSd6jDAqbkbpb2MGUoixbfg5bLWEL86j87uclA765DzYn 3f9w6VT5CrzSGVnvbUEClUl9tTPn/fHbZVFvK1qYBGGk3/En32bU2iCMwOTPkeoN coUEpMDpZDS6yXYGkDNxYFMhtbY7MkMiN3ZKnV7IB4cJVL3doJArj2BTL8fCXKXT OKjmov2cWktxU64UYj1gzVVoA/l9MnxCBx1N5l59kP+ZdgFJ9BrQL/9ELpNtWEeo GwDkcFI86iZVg0Go47Ue0gDcKCLG2cuo/cJoaQ2Krmuv3Rv7JuTxrLbPjIruLRDd WQf2t3pFUyvYrY1KyLEJ =uibw -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc Merge "ARM: tegra: Core code changes for v3.20" from Thierry Reding: This contains a couple of preparatory patches for 64-bit support. A new feature is implemented in the power-management controller which allows it to switch off the SoC if it overheats. * tag 'tegra-for-3.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc: tegra: Add thermal reset (thermtrip) support to PMC ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree of: Add descriptions of thermtrip properties to Tegra PMC bindings soc/tegra: pmc: Add Tegra132 support soc/tegra: fuse: Add Tegra132 support soc/tegra: fuse: Constify tegra_fuse_info structures soc/tegra: Add Tegra132 support clocksource: Build Tegra timer on 32-bit ARM only soc/tegra: pmc: restrict compilation of suspend-related support to ARM Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
82483ad67e
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@ -47,6 +47,23 @@ Required properties when nvidia,suspend-mode=<0>:
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Hardware-triggered thermal reset:
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On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
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hardware-triggered thermal reset will be enabled.
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Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
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described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
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Tegra K1 Technical Reference Manual.
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- nvidia,bus-addr : Bus address of the PMU on the I2C bus
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- nvidia,reg-addr : I2C register address to write poweroff command to
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- nvidia,reg-data : Poweroff command to write to PMU
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Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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Example:
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/ SoC dts including file
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@ -68,6 +85,15 @@ pmc@7000f400 {
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/ Tegra board dts file
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{
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...
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pmc@7000f400 {
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i2c-thermtrip {
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nvidia,i2c-controller-id = <4>;
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nvidia,bus-addr = <0x40>;
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nvidia,reg-addr = <0x36>;
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nvidia,reg-data = <0x2>;
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};
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};
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...
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clocks {
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compatible = "simple-bus";
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@ -1673,6 +1673,13 @@
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nvidia,core-pwr-off-time = <61036>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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i2c-thermtrip {
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nvidia,i2c-controller-id = <4>;
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nvidia,bus-addr = <0x40>;
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nvidia,reg-addr = <0x36>;
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nvidia,reg-data = <0x2>;
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};
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};
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/* Serial ATA */
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@ -27,6 +27,7 @@ config ARCH_TEGRA_2x_SOC
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select PINCTRL_TEGRA20
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PL310_ERRATA_769419 if CACHE_L2X0
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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@ -37,6 +38,7 @@ config ARCH_TEGRA_3x_SOC
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select ARM_ERRATA_764369 if SMP
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select PINCTRL_TEGRA30
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select PL310_ERRATA_769419 if CACHE_L2X0
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T30 processor family, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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@ -47,6 +49,7 @@ config ARCH_TEGRA_114_SOC
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select ARM_L1_CACHE_SHIFT_6
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA114
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T114 processor family, based on the
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ARM CortexA15MP CPU
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@ -56,6 +59,7 @@ config ARCH_TEGRA_124_SOC
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select ARM_L1_CACHE_SHIFT_6
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA124
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T124 processor family, based on the
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ARM CortexA15MP CPU
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@ -47,6 +47,9 @@ config SUN5I_HSTIMER
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select CLKSRC_MMIO
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bool
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config TEGRA_TIMER
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bool
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config VT8500_TIMER
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bool
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@ -27,7 +27,7 @@ obj-$(CONFIG_ARCH_U300) += timer-u300.o
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obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
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obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
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obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o
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obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
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obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o
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obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
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obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o
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obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm_kona_timer.o
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@ -81,6 +81,7 @@ static const struct of_device_id car_match[] __initconst = {
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{ .compatible = "nvidia,tegra30-car", },
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{ .compatible = "nvidia,tegra114-car", },
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{ .compatible = "nvidia,tegra124-car", },
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{ .compatible = "nvidia,tegra132-car", },
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{},
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};
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@ -56,7 +56,7 @@ struct tegra_fuse_info {
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static void __iomem *fuse_base;
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static struct clk *fuse_clk;
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static struct tegra_fuse_info *fuse_info;
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static const struct tegra_fuse_info *fuse_info;
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u32 tegra30_fuse_readl(const unsigned int offset)
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{
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@ -78,18 +78,18 @@ u32 tegra30_fuse_readl(const unsigned int offset)
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return val;
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}
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static struct tegra_fuse_info tegra30_info = {
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static const struct tegra_fuse_info tegra30_info = {
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.size = 0x2a4,
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.spare_bit = 0x144,
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.speedo_idx = SPEEDO_TEGRA30,
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};
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static struct tegra_fuse_info tegra114_info = {
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static const struct tegra_fuse_info tegra114_info = {
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.size = 0x2a0,
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.speedo_idx = SPEEDO_TEGRA114,
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};
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static struct tegra_fuse_info tegra124_info = {
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static const struct tegra_fuse_info tegra124_info = {
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.size = 0x300,
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.speedo_idx = SPEEDO_TEGRA124,
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};
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@ -182,6 +182,7 @@ static void __init legacy_fuse_init(void)
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fuse_info = &tegra114_info;
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break;
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case TEGRA124:
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case TEGRA132:
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fuse_info = &tegra124_info;
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break;
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default:
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@ -70,6 +70,10 @@
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#define PMC_SCRATCH41 0x140
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#define PMC_SENSOR_CTRL 0x1b0
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#define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
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#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
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#define IO_DPD_REQ 0x1b8
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#define IO_DPD_REQ_CODE_IDLE (0 << 30)
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#define IO_DPD_REQ_CODE_OFF (1 << 30)
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@ -81,6 +85,18 @@
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#define IO_DPD2_STATUS 0x1c4
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#define SEL_DPD_TIM 0x1c8
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#define PMC_SCRATCH54 0x258
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#define PMC_SCRATCH54_DATA_SHIFT 8
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#define PMC_SCRATCH54_ADDR_SHIFT 0
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#define PMC_SCRATCH55 0x25c
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#define PMC_SCRATCH55_RESET_TEGRA (1 << 31)
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#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
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#define PMC_SCRATCH55_PINMUX_SHIFT 24
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#define PMC_SCRATCH55_16BITOP (1 << 15)
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#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
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#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
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#define GPU_RG_CNTRL 0x2d4
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struct tegra_pmc_soc {
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@ -88,6 +104,9 @@ struct tegra_pmc_soc {
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const char *const *powergates;
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unsigned int num_cpu_powergates;
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const u8 *cpu_powergates;
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bool has_tsense_reset;
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bool has_gpu_clamps;
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};
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/**
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@ -110,6 +129,7 @@ struct tegra_pmc_soc {
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* @powergates_lock: mutex for power gate register access
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*/
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struct tegra_pmc {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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@ -225,11 +245,11 @@ int tegra_powergate_remove_clamping(int id)
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return -EINVAL;
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/*
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* The Tegra124 GPU has a separate register (with different semantics)
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* to remove clamps.
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* On Tegra124 and later, the clamps for the GPU are controlled by a
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* separate register (with different semantics).
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*/
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if (tegra_get_chip_id() == TEGRA124) {
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if (id == TEGRA_POWERGATE_3D) {
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if (id == TEGRA_POWERGATE_3D) {
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if (pmc->soc->has_gpu_clamps) {
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tegra_pmc_writel(0, GPU_RG_CNTRL);
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return 0;
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}
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@ -703,6 +723,83 @@ static void tegra_pmc_init(struct tegra_pmc *pmc)
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tegra_pmc_writel(value, PMC_CNTRL);
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}
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void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
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{
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static const char disabled[] = "emergency thermal reset disabled";
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u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
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struct device *dev = pmc->dev;
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struct device_node *np;
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u32 value, checksum;
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if (!pmc->soc->has_tsense_reset)
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goto out;
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np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
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if (!np) {
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dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
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goto out;
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}
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if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
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dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
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goto out;
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}
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if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
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dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
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goto out;
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}
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if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
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dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
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goto out;
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}
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if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
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dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
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goto out;
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}
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if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
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pinmux = 0;
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value = tegra_pmc_readl(PMC_SENSOR_CTRL);
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value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
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tegra_pmc_writel(value, PMC_SENSOR_CTRL);
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value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
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(reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
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tegra_pmc_writel(value, PMC_SCRATCH54);
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value = PMC_SCRATCH55_RESET_TEGRA;
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value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
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value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
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value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
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/*
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* Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
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* contain the checksum and are currently zero, so they are not added.
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*/
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checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
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+ ((value >> 24) & 0xff);
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checksum &= 0xff;
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checksum = 0x100 - checksum;
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value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
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tegra_pmc_writel(value, PMC_SCRATCH55);
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value = tegra_pmc_readl(PMC_SENSOR_CTRL);
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value |= PMC_SENSOR_CTRL_ENABLE_RST;
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tegra_pmc_writel(value, PMC_SENSOR_CTRL);
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dev_info(pmc->dev, "emergency thermal reset enabled\n");
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out:
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of_node_put(np);
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return;
|
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}
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|
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static int tegra_pmc_probe(struct platform_device *pdev)
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{
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void __iomem *base = pmc->base;
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|
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@ -728,8 +825,12 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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return err;
|
||||
}
|
||||
|
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pmc->dev = &pdev->dev;
|
||||
|
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tegra_pmc_init(pmc);
|
||||
|
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tegra_pmc_init_tsense_reset(pmc);
|
||||
|
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if (IS_ENABLED(CONFIG_DEBUG_FS)) {
|
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err = tegra_powergate_debugfs_init();
|
||||
if (err < 0)
|
||||
|
|
@ -739,7 +840,7 @@ static int tegra_pmc_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
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#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
|
||||
static int tegra_pmc_suspend(struct device *dev)
|
||||
{
|
||||
tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
|
||||
|
|
@ -753,10 +854,11 @@ static int tegra_pmc_resume(struct device *dev)
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
|
||||
|
||||
#endif
|
||||
|
||||
static const char * const tegra20_powergates[] = {
|
||||
[TEGRA_POWERGATE_CPU] = "cpu",
|
||||
[TEGRA_POWERGATE_3D] = "3d",
|
||||
|
|
@ -772,6 +874,8 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
|
|||
.powergates = tegra20_powergates,
|
||||
.num_cpu_powergates = 0,
|
||||
.cpu_powergates = NULL,
|
||||
.has_tsense_reset = false,
|
||||
.has_gpu_clamps = false,
|
||||
};
|
||||
|
||||
static const char * const tegra30_powergates[] = {
|
||||
|
|
@ -803,6 +907,8 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
|
|||
.powergates = tegra30_powergates,
|
||||
.num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
|
||||
.cpu_powergates = tegra30_cpu_powergates,
|
||||
.has_tsense_reset = true,
|
||||
.has_gpu_clamps = false,
|
||||
};
|
||||
|
||||
static const char * const tegra114_powergates[] = {
|
||||
|
|
@ -838,6 +944,8 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
|
|||
.powergates = tegra114_powergates,
|
||||
.num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
|
||||
.cpu_powergates = tegra114_cpu_powergates,
|
||||
.has_tsense_reset = true,
|
||||
.has_gpu_clamps = false,
|
||||
};
|
||||
|
||||
static const char * const tegra124_powergates[] = {
|
||||
|
|
@ -879,6 +987,8 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
|
|||
.powergates = tegra124_powergates,
|
||||
.num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
|
||||
.cpu_powergates = tegra124_cpu_powergates,
|
||||
.has_tsense_reset = true,
|
||||
.has_gpu_clamps = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_pmc_match[] = {
|
||||
|
|
@ -894,7 +1004,9 @@ static struct platform_driver tegra_pmc_driver = {
|
|||
.name = "tegra-pmc",
|
||||
.suppress_bind_attrs = true,
|
||||
.of_match_table = tegra_pmc_match,
|
||||
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
|
||||
.pm = &tegra_pmc_pm_ops,
|
||||
#endif
|
||||
},
|
||||
.probe = tegra_pmc_probe,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#define TEGRA30 0x30
|
||||
#define TEGRA114 0x35
|
||||
#define TEGRA124 0x40
|
||||
#define TEGRA132 0x13
|
||||
|
||||
#define TEGRA_FUSE_SKU_CALIB_0 0xf0
|
||||
#define TEGRA30_FUSE_SATA_CALIB 0x124
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ enum tegra_suspend_mode {
|
|||
TEGRA_MAX_SUSPEND_MODE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
|
||||
enum tegra_suspend_mode
|
||||
tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue