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Add interconnect target module dts data for omaps for v4.21 

This big set of changes adds SoC specific l4 interconnect target module
 device tree data for am335x, am437x, omap5 and dra7 SoCs. We also move
 existing devices to the right location in the l4 interconnect hierarcy.
 This is similar to what we've already done for omap4 l4 interconnects
 earlier, and follows what is documented in the ti-sysc driver dts binding
 in Documentation/devicetree/bindings/bus/ti-sysc.txt.
 
 These changes will essentially replace the struct ti_sysc and clock
 entries in the arch/arm/mach-omap2/omap_hwmod_*_data.c files. Then a few
 merge windows later, we can start dropping the built-in platform data
 from the omap_hwmod_*_data.c files in favor of the device tree data only.
 For now, we verify the device tree data module data against the built-in
 data and warn about changes to prevent regressions.
 
 With the device tree data, we are also probing devices with the ti-sysc
 interconnect target module instead of omap_device. This fixes up the
 handling for multiple device instances in a single interconnect target
 module that has caused trouble earlier. A custom wrapper driver has been
 needed earlier for such cases.
 
 And as the device tree data is organized by the l4 interconnect instances,
 we will be able to use genpd later on. This is because each interconnect
 instance is also often also a single power domain.
 
 This series of changes has been brewing for several months now. I did not
 want to send a pull request earlier as people were still seeing device
 specific issues until recently though. However, it turned out that all the
 issues were quite trivial to fix. I had missed adding device tree ranges
 for the l3 data port used on some devices, and I had missed converting the
 device addresses for a few devices. And some devices like needed fixes for
 deferred probe handling such as the EHCI PHY for built-in case on omap5.
 
 Anyways, in case of trouble, we can easily just revert changes for a
 single device if needed.
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Merge tag 'omap-for-v4.21/dt-ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Add interconnect target module dts data for omaps for v4.21

This big set of changes adds SoC specific l4 interconnect target module
device tree data for am335x, am437x, omap5 and dra7 SoCs. We also move
existing devices to the right location in the l4 interconnect hierarcy.
This is similar to what we've already done for omap4 l4 interconnects
earlier, and follows what is documented in the ti-sysc driver dts binding
in Documentation/devicetree/bindings/bus/ti-sysc.txt.

These changes will essentially replace the struct ti_sysc and clock
entries in the arch/arm/mach-omap2/omap_hwmod_*_data.c files. Then a few
merge windows later, we can start dropping the built-in platform data
from the omap_hwmod_*_data.c files in favor of the device tree data only.
For now, we verify the device tree data module data against the built-in
data and warn about changes to prevent regressions.

With the device tree data, we are also probing devices with the ti-sysc
interconnect target module instead of omap_device. This fixes up the
handling for multiple device instances in a single interconnect target
module that has caused trouble earlier. A custom wrapper driver has been
needed earlier for such cases.

And as the device tree data is organized by the l4 interconnect instances,
we will be able to use genpd later on. This is because each interconnect
instance is also often also a single power domain.

This series of changes has been brewing for several months now. I did not
want to send a pull request earlier as people were still seeing device
specific issues until recently though. However, it turned out that all the
issues were quite trivial to fix. I had missed adding device tree ranges
for the l3 data port used on some devices, and I had missed converting the
device addresses for a few devices. And some devices like needed fixes for
deferred probe handling such as the EHCI PHY for built-in case on omap5.

Anyways, in case of trouble, we can easily just revert changes for a
single device if needed.

* tag 'omap-for-v4.21/dt-ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Cosmetic fix for omap5 USB node names
  ARM: dts: Fix wrong address for omap5 sata phy
  ARM: dts: Add missing ranges for dra7 mcasp l3 ports
  ARM: dts: Fix ranges for am335x epwmss
  ARM: dts: Fix hsi gdd range for omap4
  ARM: dts: Add am335x mcasp with l3 data port ranges
  ARM: dts: Add missing ranges for am437x mcasp l3 ports
  ARM: dts: dra7: Move the ti,no-idle quirk on proper gmac node
  ARM: dts: Revert am335x mcasp ti-sysc changes
  ARM: dts: omap5: Add l4 interconnect hierarchy and ti-sysc data
  ARM: dts: Use dra7 mcasp compatible for mcasp instances
  ARM: dts: dra7: Move l4 child devices to probe them with ti-sysc
  ARM: dts: dra7: Add l4 interconnect hierarchy and ti-sysc data
  ARM: dts: am335x: Move l4 child devices to probe them with ti-sysc
  ARM: dts: am335x: Add l4 interconnect hierarchy and ti-sysc data
  ARM: dts: am437x: Move l4 child devices to probe them with ti-sysc
  ARM: dts: am437x: Add l4 interconnect hierarchy and ti-sysc data
  ARM: dts: dra7: convert to use new clkctrl layout
  ARM: dts: am43xx: convert to use new clkctrl layout
  ARM: dts: am33xx: convert to use new clkctrl layout

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2018-12-20 16:34:06 +01:00
parent bc8bd33891 c7a851b705
commit 826833df4e
25 changed files with 12029 additions and 3680 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -419,6 +419,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-boneblue.dts
View File

@ -515,7 +515,7 @@
&rtc {
system-power-controller;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-cm-t335.dts
View File

@ -393,7 +393,7 @@ status = "okay";
&epwmss0 {
status = "okay";
ecap0: ecap@48300100 {
ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;

4
arch/arm/boot/dts/am335x-evm.dts
View File

@ -519,7 +519,7 @@
&epwmss0 {
status = "okay";
ecap0: ecap@48300100 {
ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
@ -797,6 +797,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

4
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -540,7 +540,7 @@
&epwmss2 {
status = "okay";
ecap2: ecap@48304100 {
ecap2: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap2_pins>;
@ -738,6 +738,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

2
arch/arm/boot/dts/am335x-osd3358-sm-red.dts
View File

@ -456,6 +456,6 @@
};
&rtc {
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

4
arch/arm/boot/dts/am335x-shc.dts
View File

@ -138,7 +138,7 @@
&epwmss1 {
status = "okay";
ehrpwm1: pwm@48302200 {
ehrpwm1: pwm@200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
status = "okay";
@ -205,7 +205,7 @@
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
cpsw_emac0: slave@4a100200 {
cpsw_emac0: slave@200 {
phy-mode = "mii";
phy-handle = <&ethernetphy0>;
};

110
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -334,49 +334,49 @@
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@ -407,7 +407,7 @@
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@ -477,7 +477,7 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
@ -539,86 +539,140 @@
};
&prcm {
l4_per_cm: l4_per_cm@0 {
per_cm: per-cm@0 {
compatible = "ti,omap4-cm";
reg = <0x0 0x200>;
reg = <0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x200>;
ranges = <0 0x0 0x400>;
l4_per_clkctrl: clk@14 {
l4ls_clkctrl: l4ls-clkctrl@38 {
compatible = "ti,clkctrl";
reg = <0x14 0x13c>;
reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
#clock-cells = <2>;
};
l3s_clkctrl: l3s-clkctrl@1c {
compatible = "ti,clkctrl";
reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
#clock-cells = <2>;
};
l3_clkctrl: l3-clkctrl@24 {
compatible = "ti,clkctrl";
reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
#clock-cells = <2>;
};
l4hs_clkctrl: l4hs-clkctrl@120 {
compatible = "ti,clkctrl";
reg = <0x120 0x4>;
#clock-cells = <2>;
};
pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
compatible = "ti,clkctrl";
reg = <0xe8 0x4>;
#clock-cells = <2>;
};
cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x18>;
#clock-cells = <2>;
};
lcdc_clkctrl: lcdc-clkctrl@18 {
compatible = "ti,clkctrl";
reg = <0x18 0x4>;
#clock-cells = <2>;
};
clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
compatible = "ti,clkctrl";
reg = <0x14c 0x4>;
#clock-cells = <2>;
};
};
l4_wkup_cm: l4_wkup_cm@400 {
wkup_cm: wkup-cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
l4_wkup_clkctrl: clk@4 {
l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x4 0xd4>;
reg = <0x0 0x10>, <0xb4 0x24>;
#clock-cells = <2>;
};
l3_aon_clkctrl: l3-aon-clkctrl@14 {
compatible = "ti,clkctrl";
reg = <0x14 0x4>;
#clock-cells = <2>;
};
l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
compatible = "ti,clkctrl";
reg = <0xb0 0x4>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@600 {
mpu_cm: mpu-cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
mpu_clkctrl: clk@4 {
mpu_clkctrl: mpu-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@800 {
l4_rtc_cm: l4-rtc-cm@800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
l4_rtc_clkctrl: clk@0 {
l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@900 {
gfx_l3_cm: gfx-l3-cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
gfx_l3_clkctrl: clk@4 {
gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
l4_cefuse_cm: l4_cefuse_cm@a00 {
l4_cefuse_cm: l4-cefuse-cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
l4_cefuse_clkctrl: clk@20 {
l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
reg = <0x0 0x24>;
#clock-cells = <2>;
};
};

2132
arch/arm/boot/dts/am33xx-l4.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

623
arch/arm/boot/dts/am33xx.dtsi
View File

@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>
@ -166,87 +167,23 @@
ranges;
ti,hwmods = "l3_main";
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am3-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@210000 {
compatible = "ti,am3-scm", "simple-bus";
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
scm_conf: scm_conf@0 {
compatible = "syscon", "simple-bus";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x800>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <32>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains {
};
};
};
l4_per: interconnect@48000000 {
};
l4_fw: interconnect@47c00000 {
};
l4_fast: interconnect@4a000000 {
};
l4_mpuss: interconnect@4b140000 {
};
intc: interrupt-controller@48200000 {
@ -297,166 +234,6 @@
interrupt-names = "edma3_tcerrint";
};
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x44e07000 0x1000>;
interrupts = <96>;
};
gpio1: gpio@4804c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4804c000 0x1000>;
interrupts = <98>;
};
gpio2: gpio@481ac000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x481ac000 0x1000>;
interrupts = <32>;
};
gpio3: gpio@481ae000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x481ae000 0x1000>;
interrupts = <62>;
};
uart0: serial@44e09000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
reg = <0x44e09000 0x2000>;
interrupts = <72>;
status = "disabled";
dmas = <&edma 26 0>, <&edma 27 0>;
dma-names = "tx", "rx";
};
uart1: serial@48022000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
reg = <0x48022000 0x2000>;
interrupts = <73>;
status = "disabled";
dmas = <&edma 28 0>, <&edma 29 0>;
dma-names = "tx", "rx";
};
uart2: serial@48024000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
reg = <0x48024000 0x2000>;
interrupts = <74>;
status = "disabled";
dmas = <&edma 30 0>, <&edma 31 0>;
dma-names = "tx", "rx";
};
uart3: serial@481a6000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
reg = <0x481a6000 0x2000>;
interrupts = <44>;
status = "disabled";
};
uart4: serial@481a8000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
reg = <0x481a8000 0x2000>;
interrupts = <45>;
status = "disabled";
};
uart5: serial@481aa000 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
reg = <0x481aa000 0x2000>;
interrupts = <46>;
status = "disabled";
};
i2c0: i2c@44e0b000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
reg = <0x44e0b000 0x1000>;
interrupts = <70>;
status = "disabled";
};
i2c1: i2c@4802a000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
reg = <0x4802a000 0x1000>;
interrupts = <71>;
status = "disabled";
};
i2c2: i2c@4819c000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
reg = <0x4819c000 0x1000>;
interrupts = <30>;
status = "disabled";
};
mmc1: mmc@48060000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
ti,needs-special-hs-handling;
dmas = <&edma_xbar 24 0 0
&edma_xbar 25 0 0>;
dma-names = "tx", "rx";
interrupts = <64>;
reg = <0x48060000 0x1000>;
status = "disabled";
};
mmc2: mmc@481d8000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&edma 2 0
&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <28>;
reg = <0x481d8000 0x1000>;
status = "disabled";
};
mmc3: mmc@47810000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc3";
@ -466,157 +243,6 @@
status = "disabled";
};
hwspinlock: spinlock@480ca000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x480ca000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
wdt2: wdt@44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
reg = <0x44e35000 0x1000>;
interrupts = <91>;
};
dcan0: can@481cc000 {
compatible = "ti,am3352-d_can";
ti,hwmods = "d_can0";
reg = <0x481cc000 0x2000>;
clocks = <&dcan0_fck>;
clock-names = "fck";
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <52>;
status = "disabled";
};
dcan1: can@481d0000 {
compatible = "ti,am3352-d_can";
ti,hwmods = "d_can1";
reg = <0x481d0000 0x2000>;
clocks = <&dcan1_fck>;
clock-names = "fck";
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <55>;
status = "disabled";
};
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
};
};
timer1: timer@44e31000 {
compatible = "ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
compatible = "ti,am335x-timer";
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
compatible = "ti,am335x-timer";
reg = <0x48042000 0x400>;
interrupts = <69>;
ti,hwmods = "timer3";
};
timer4: timer@48044000 {
compatible = "ti,am335x-timer";
reg = <0x48044000 0x400>;
interrupts = <92>;
ti,hwmods = "timer4";
ti,timer-pwm;
};
timer5: timer@48046000 {
compatible = "ti,am335x-timer";
reg = <0x48046000 0x400>;
interrupts = <93>;
ti,hwmods = "timer5";
ti,timer-pwm;
};
timer6: timer@48048000 {
compatible = "ti,am335x-timer";
reg = <0x48048000 0x400>;
interrupts = <94>;
ti,hwmods = "timer6";
ti,timer-pwm;
};
timer7: timer@4804a000 {
compatible = "ti,am335x-timer";
reg = <0x4804a000 0x400>;
interrupts = <95>;
ti,hwmods = "timer7";
ti,timer-pwm;
};
rtc: rtc@44e3e000 {
compatible = "ti,am3352-rtc", "ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <75
76>;
ti,hwmods = "rtc";
clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
spi0: spi@48030000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48030000 0x400>;
interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
dmas = <&edma 16 0
&edma 17 0
&edma 18 0
&edma 19 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
spi1: spi@481a0000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x481a0000 0x400>;
interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
dmas = <&edma 42 0
&edma 43 0
&edma 44 0
&edma 45 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
usb: usb@47400000 {
compatible = "ti,am33xx-usb";
reg = <0x47400000 0x1000>;
@ -747,163 +373,6 @@
};
};
epwmss0: epwmss@48300000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
0x48300180 0x48300180 0x80 /* EQEP */
0x48300200 0x48300200 0x80>; /* EHRPWM */
ecap0: ecap@48300100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <31>;
interrupt-names = "ecap0";
status = "disabled";
};
ehrpwm0: pwm@48300200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss1: epwmss@48302000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48302000 0x10>;
ti,hwmods = "epwmss1";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48302100 0x48302100 0x80 /* ECAP */
0x48302180 0x48302180 0x80 /* EQEP */
0x48302200 0x48302200 0x80>; /* EHRPWM */
ecap1: ecap@48302100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <47>;
interrupt-names = "ecap1";
status = "disabled";
};
ehrpwm1: pwm@48302200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss2: epwmss@48304000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48304000 0x10>;
ti,hwmods = "epwmss2";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48304100 0x48304100 0x80 /* ECAP */
0x48304180 0x48304180 0x80 /* EQEP */
0x48304200 0x48304200 0x80>; /* EHRPWM */
ecap2: ecap@48304100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <61>;
interrupt-names = "ecap2";
status = "disabled";
};
ehrpwm2: pwm@48304200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
mac: ethernet@4a100000 {
compatible = "ti,am335x-cpsw","ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x4a100000 0x800
0x4a101200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
* c0_tx_pend
* c0_misc_pend
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@4a101000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x4a101000 0x100>;
status = "disabled";
};
cpsw_emac0: slave@4a100200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@4a100300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@44e10650 {
compatible = "ti,am3352-cpsw-phy-sel";
reg= <0x44e10650 0x4>;
reg-names = "gmii-sel";
};
};
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
@ -924,40 +393,6 @@
};
};
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
interrupts = <4>;
ti,hwmods = "elm";
status = "disabled";
};
lcdc: lcdc@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
interrupts = <36>;
ti,hwmods = "lcdc";
status = "disabled";
};
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
};
am335x_adc: adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
@ -1005,42 +440,8 @@
<&edma 5 0>;
dma-names = "tx", "rx";
};
mcasp0: mcasp@48038000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp0";
reg = <0x48038000 0x2000>,
<0x46000000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
<0x46400000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <82>, <83>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10 2>,
<&edma 11 2>;
dma-names = "tx", "rx";
};
rng: rng@48310000 {
compatible = "ti,omap4-rng";
ti,hwmods = "rng";
reg = <0x48310000 0x2000>;
interrupts = <111>;
};
};
};
#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"

876
arch/arm/boot/dts/am4372.dtsi
View File

@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>
@ -159,12 +160,7 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am4-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x287000>;
l4_wkup: interconnect@44c00000 {
wkup_m3: wkup_m3@100000 {
compatible = "ti,am4372-wkup-m3";
reg = <0x100000 0x4000>,
@ -173,75 +169,10 @@
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm", "simple-bus";
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@210000 {
compatible = "ti,am4-scm", "simple-bus";
reg = <0x210000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x210000 0x4000>;
am43xx_pinmux: pinmux@800 {
compatible = "ti,am437-padconf",
"pinctrl-single";
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am4372-wkup-m3-ipc";
reg = <0x1324 0x44>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <64>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains {
};
};
};
l4_per: interconnect@48000000 {
};
l4_fast: interconnect@4a000000 {
};
emif: emif@4c000000 {
@ -297,333 +228,6 @@
interrupt-names = "edma3_tcerrint";
};
uart0: serial@44e09000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x44e09000 0x2000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
};
uart1: serial@48022000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x48022000 0x2000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
status = "disabled";
};
uart2: serial@48024000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x48024000 0x2000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
status = "disabled";
};
uart3: serial@481a6000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x481a6000 0x2000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
status = "disabled";
};
uart4: serial@481a8000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x481a8000 0x2000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
status = "disabled";
};
uart5: serial@481aa000 {
compatible = "ti,am4372-uart","ti,omap2-uart";
reg = <0x481aa000 0x2000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
status = "disabled";
};
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
};
};
timer1: timer@44e31000 {
compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,hwmods = "timer1";
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48040000 0x400>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48042000 0x400>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
status = "disabled";
};
timer4: timer@48044000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48044000 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer4";
status = "disabled";
};
timer5: timer@48046000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48046000 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer5";
status = "disabled";
};
timer6: timer@48048000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48048000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer6";
status = "disabled";
};
timer7: timer@4804a000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x4804a000 0x400>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,hwmods = "timer7";
status = "disabled";
};
timer8: timer@481c1000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x481c1000 0x400>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
status = "disabled";
};
timer9: timer@4833d000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x4833d000 0x400>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
status = "disabled";
};
timer10: timer@4833f000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x4833f000 0x400>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
status = "disabled";
};
timer11: timer@48341000 {
compatible = "ti,am4372-timer","ti,am335x-timer";
reg = <0x48341000 0x400>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
status = "disabled";
};
counter32k: counter@44e86000 {
compatible = "ti,am4372-counter32k","ti,omap-counter32k";
reg = <0x44e86000 0x40>;
ti,hwmods = "counter_32k";
};
rtc: rtc@44e3e000 {
compatible = "ti,am4372-rtc", "ti,am3352-rtc",
"ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "rtc";
clocks = <&clk_32768_ck>;
clock-names = "int-clk";
system-power-controller;
status = "disabled";
};
wdt: wdt@44e35000 {
compatible = "ti,am4372-wdt","ti,omap3-wdt";
reg = <0x44e35000 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
};
gpio0: gpio@44e07000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x44e07000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio1";
status = "disabled";
};
gpio1: gpio@4804c000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x4804c000 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio2";
status = "disabled";
};
gpio2: gpio@481ac000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x481ac000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio3";
status = "disabled";
};
gpio3: gpio@481ae000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x481ae000 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio4";
status = "disabled";
};
gpio4: gpio@48320000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x48320000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio5";
status = "disabled";
};
gpio5: gpio@48322000 {
compatible = "ti,am4372-gpio","ti,omap4-gpio";
reg = <0x48322000 0x1000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
ti,hwmods = "gpio6";
status = "disabled";
};
hwspinlock: spinlock@480ca000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x480ca000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
i2c0: i2c@44e0b000 {
compatible = "ti,am4372-i2c","ti,omap4-i2c";
reg = <0x44e0b000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "i2c1";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@4802a000 {
compatible = "ti,am4372-i2c","ti,omap4-i2c";
reg = <0x4802a000 0x1000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "i2c2";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@4819c000 {
compatible = "ti,am4372-i2c","ti,omap4-i2c";
reg = <0x4819c000 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "i2c3";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@48030000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x48030000 0x400>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi0";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmc1: mmc@48060000 {
compatible = "ti,omap4-hsmmc";
reg = <0x48060000 0x1000>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&edma 24 0>,
<&edma 25 0>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mmc2: mmc@481d8000 {
compatible = "ti,omap4-hsmmc";
reg = <0x481d8000 0x1000>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&edma 2 0>,
<&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mmc3: mmc@47810000 {
compatible = "ti,omap4-hsmmc";
reg = <0x47810000 0x1000>;
@ -633,282 +237,6 @@
status = "disabled";
};
spi1: spi@481a0000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x481a0000 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi1";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@481a2000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x481a2000 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi2";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@481a4000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x481a4000 0x400>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi3";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@48345000 {
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
reg = <0x48345000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "spi4";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mac: ethernet@4a100000 {
compatible = "ti,am4372-cpsw","ti,cpsw";
reg = <0x4a100000 0x800
0x4a101200 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
<&dpll_clksel_mac_clk>;
clock-names = "fck", "cpts", "50mclk";
assigned-clocks = <&dpll_clksel_mac_clk>;
assigned-clock-rates = <50000000>;
status = "disabled";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
ranges;
syscon = <&scm_conf>;
davinci_mdio: mdio@4a101000 {
compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x4a101000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
status = "disabled";
};
cpsw_emac0: slave@4a100200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@4a100300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@44e10650 {
compatible = "ti,am43xx-cpsw-phy-sel";
reg= <0x44e10650 0x4>;
reg-names = "gmii-sel";
};
};
epwmss0: epwmss@48300000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss0";
status = "disabled";
ecap0: ecap@48300100 {
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm0: pwm@48300200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss1: epwmss@48302000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48302000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss1";
status = "disabled";
ecap1: ecap@48302100 {
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm1: pwm@48302200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss2: epwmss@48304000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48304000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss2";
status = "disabled";
ecap2: ecap@48304100 {
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm2: pwm@48304200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss3: epwmss@48306000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48306000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss3";
status = "disabled";
ehrpwm3: pwm@48306200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48306200 0x80>;
clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss4: epwmss@48308000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x48308000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss4";
status = "disabled";
ehrpwm4: pwm@48308200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48308200 0x80>;
clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
epwmss5: epwmss@4830a000 {
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
reg = <0x4830a000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "epwmss5";
status = "disabled";
ehrpwm5: pwm@4830a200 {
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x4830a200 0x80>;
clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
tscadc: tscadc@44e0d000 {
compatible = "ti,am3359-tscadc";
reg = <0x44e0d000 0x1000>;
ti,hwmods = "adc_tsc";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adc_tsc_fck>;
clock-names = "fck";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
};
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
@ -938,53 +266,6 @@
dma-names = "tx", "rx";
};
rng: rng@48310000 {
compatible = "ti,omap4-rng";
ti,hwmods = "rng";
reg = <0x48310000 0x2000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
};
mcasp0: mcasp@48038000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp0";
reg = <0x48038000 0x2000>,
<0x46000000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
<0x46400000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10 2>,
<&edma 11 2>;
dma-names = "tx", "rx";
};
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "elm";
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
@ -1005,102 +286,6 @@
status = "disabled";
};
ocp2scp0: ocp2scp@483a8000 {
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp0";
usb2_phy1: phy@483a8000 {
compatible = "ti,am437x-usb2";
reg = <0x483a8000 0x8000>;
syscon-phy-power = <&scm_conf 0x620>;
clocks = <&usb_phy0_always_on_clk32k>,
<&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
};
};
ocp2scp1: ocp2scp@483e8000 {
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp1";
usb2_phy2: phy@483e8000 {
compatible = "ti,am437x-usb2";
reg = <0x483e8000 0x8000>;
syscon-phy-power = <&scm_conf 0x628>;
clocks = <&usb_phy1_always_on_clk32k>,
<&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
};
};
dwc3_1: omap_dwc3@48380000 {
compatible = "ti,am437x-dwc3";
ti,hwmods = "usb_otg_ss0";
reg = <0x48380000 0x10000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <1>;
ranges;
usb1: usb@48390000 {
compatible = "synopsys,dwc3";
reg = <0x48390000 0x10000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "otg";
status = "disabled";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
};
};
dwc3_2: omap_dwc3@483c0000 {
compatible = "ti,am437x-dwc3";
ti,hwmods = "usb_otg_ss1";
reg = <0x483c0000 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <1>;
ranges;
usb2: usb@483d0000 {
compatible = "synopsys,dwc3";
reg = <0x483d0000 0x10000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "otg";
status = "disabled";
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
};
};
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
@ -1114,16 +299,6 @@
status = "disabled";
};
hdq: hdq@48347000 {
compatible = "ti,am4372-hdq";
reg = <0x48347000 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&func_12m_clk>;
clock-names = "fck";
ti,hwmods = "hdq1w";
status = "disabled";
};
dss: dss@4832a000 {
compatible = "ti,omap3-dss";
reg = <0x4832a000 0x200>;
@ -1173,45 +348,8 @@
pool;
};
};
dcan0: can@481cc000 {
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
ti,hwmods = "d_can0";
clocks = <&dcan0_fck>;
clock-names = "fck";
reg = <0x481cc000 0x2000>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
dcan1: can@481d0000 {
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
ti,hwmods = "d_can1";
clocks = <&dcan1_fck>;
clock-names = "fck";
reg = <0x481d0000 0x2000>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
vpfe0: vpfe@48326000 {
compatible = "ti,am437x-vpfe";
reg = <0x48326000 0x2000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "vpfe0";
status = "disabled";
};
vpfe1: vpfe@48328000 {
compatible = "ti,am437x-vpfe";
reg = <0x48328000 0x2000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "vpfe1";
status = "disabled";
};
};
};
#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"

2505
arch/arm/boot/dts/am437x-l4.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

74
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -710,73 +710,123 @@
};
&prcm {
l4_wkup_cm: l4_wkup_cm@2800 {
wkup_cm: wkup-cm@2800 {
compatible = "ti,omap4-cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
l4_wkup_clkctrl: clk@20 {
l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
compatible = "ti,clkctrl";
reg = <0x20 0x34c>;
reg = <0x120 0x4>;
#clock-cells = <2>;
};
l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
compatible = "ti,clkctrl";
reg = <0x228 0xc>;
#clock-cells = <2>;
};
l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
compatible = "ti,clkctrl";
reg = <0x220 0x4>, <0x328 0x44>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@8300 {
mpu_cm: mpu-cm@8300 {
compatible = "ti,omap4-cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
mpu_clkctrl: clk@20 {
mpu_clkctrl: mpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@8400 {
gfx_l3_cm: gfx-l3-cm@8400 {
compatible = "ti,omap4-cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
gfx_l3_clkctrl: clk@20 {
gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@8500 {
l4_rtc_cm: l4-rtc-cm@8500 {
compatible = "ti,omap4-cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
l4_rtc_clkctrl: clk@20 {
l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l4_per_cm: l4_per_cm@8800 {
per_cm: per-cm@8800 {
compatible = "ti,omap4-cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
l4_per_clkctrl: clk@20 {
l3_clkctrl: l3-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xb04>;
reg = <0x20 0x3c>, <0x78 0x2c>;
#clock-cells = <2>;
};
l3s_clkctrl: l3s-clkctrl@68 {
compatible = "ti,clkctrl";
reg = <0x68 0xc>, <0x220 0x4c>;
#clock-cells = <2>;
};
pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
compatible = "ti,clkctrl";
reg = <0x320 0x4>;
#clock-cells = <2>;
};
l4ls_clkctrl: l4ls-clkctrl@420 {
compatible = "ti,clkctrl";
reg = <0x420 0x1a4>;
#clock-cells = <2>;
};
emif_clkctrl: emif-clkctrl@720 {
compatible = "ti,clkctrl";
reg = <0x720 0x4>;
#clock-cells = <2>;
};
dss_clkctrl: dss-clkctrl@a20 {
compatible = "ti,clkctrl";
reg = <0xa20 0x4>;
#clock-cells = <2>;
};
cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
compatible = "ti,clkctrl";
reg = <0xb20 0x4>;
#clock-cells = <2>;
};
};
};

2
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -555,7 +555,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

4
arch/arm/boot/dts/dra7-evm-common.dtsi
View File

@ -214,7 +214,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@ -232,7 +232,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";

4600
arch/arm/boot/dts/dra7-l4.dtsi Normal file
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File diff suppressed because it is too large Load Diff

1434
arch/arm/boot/dts/dra7.dtsi
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/boot/dts/dra72-evm-common.dtsi
View File

@ -530,7 +530,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@ -548,7 +548,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";

4
arch/arm/boot/dts/dra72x.dtsi
View File

@ -25,8 +25,8 @@
<0x58004300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>;
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
clock-names = "fck", "video1_clk";
};

6
arch/arm/boot/dts/dra74x.dtsi
View File

@ -103,9 +103,9 @@
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
clock-names = "fck", "video1_clk", "video2_clk";
};

2
arch/arm/boot/dts/dra76x.dtsi
View File

@ -24,7 +24,7 @@
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
SYSC_DRA7_MCAN_ENAWAKEUP)>;
ti,syss-mask = <1>;
clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>;
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
clock-names = "fck";
m_can0: mcan@1a00 {

159
arch/arm/boot/dts/dra7xx-clocks.dtsi
View File

@ -11,25 +11,25 @@
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
};
hdmi_clkin_ck: hdmi_clkin_ck {
@ -1526,44 +1526,82 @@
};
&cm_core_aon {
mpu_cm: mpu_cm@300 {
mpu_cm: mpu-cm@300 {
compatible = "ti,omap4-cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x300 0x100>;
mpu_clkctrl: clk@20 {
mpu_clkctrl: mpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
ipu_cm: ipu_cm@500 {
dsp1_cm: dsp1-cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
dsp1_clkctrl: dsp1-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
ipu_cm: ipu-cm@500 {
compatible = "ti,omap4-cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
ipu_clkctrl: clk@40 {
ipu1_clkctrl: ipu1-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x40 0x44>;
reg = <0x20 0x4>;
#clock-cells = <2>;
};
ipu_clkctrl: ipu-clkctrl@50 {
compatible = "ti,clkctrl";
reg = <0x50 0x34>;
#clock-cells = <2>;
};
};
rtc_cm: rtc_cm@700 {
dsp2_cm: dsp2-cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
dsp2_clkctrl: dsp2-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
rtc_cm: rtc-cm@700 {
compatible = "ti,omap4-cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
rtc_clkctrl: clk@40 {
rtc_clkctrl: rtc-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x40 0x8>;
reg = <0x20 0x28>;
#clock-cells = <2>;
};
};
@ -1571,160 +1609,207 @@
};
&cm_core {
coreaon_cm: coreaon_cm@600 {
coreaon_cm: coreaon-cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
coreaon_clkctrl: clk@20 {
coreaon_clkctrl: coreaon-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
};
l3main1_cm: l3main1_cm@700 {
l3main1_cm: l3main1-cm@700 {
compatible = "ti,omap4-cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
l3main1_clkctrl: clk@20 {
l3main1_clkctrl: l3main1-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x74>;
#clock-cells = <2>;
};
};
dma_cm: dma_cm@a00 {
ipu2_cm: ipu2-cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
ipu2_clkctrl: ipu2-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
dma_cm: dma-cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
dma_clkctrl: clk@20 {
dma_clkctrl: dma-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
emif_cm: emif_cm@b00 {
emif_cm: emif-cm@b00 {
compatible = "ti,omap4-cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xb00 0x100>;
emif_clkctrl: clk@20 {
emif_clkctrl: emif-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
atl_cm: atl_cm@c00 {
atl_cm: atl-cm@c00 {
compatible = "ti,omap4-cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xc00 0x100>;
atl_clkctrl: clk@0 {
atl_clkctrl: atl-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
l4cfg_cm: l4cfg_cm@d00 {
l4cfg_cm: l4cfg-cm@d00 {
compatible = "ti,omap4-cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd00 0x100>;
l4cfg_clkctrl: clk@20 {
l4cfg_clkctrl: l4cfg-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x84>;
#clock-cells = <2>;
};
};
l3instr_cm: l3instr_cm@e00 {
l3instr_cm: l3instr-cm@e00 {
compatible = "ti,omap4-cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe00 0x100>;
l3instr_clkctrl: clk@20 {
l3instr_clkctrl: l3instr-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
};
dss_cm: dss_cm@1100 {
dss_cm: dss-cm@1100 {
compatible = "ti,omap4-cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1100 0x100>;
dss_clkctrl: clk@20 {
dss_clkctrl: dss-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
};
l3init_cm: l3init_cm@1300 {
l3init_cm: l3init-cm@1300 {
compatible = "ti,omap4-cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1300 0x100>;
l3init_clkctrl: clk@20 {
l3init_clkctrl: l3init-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xd4>;
reg = <0x20 0x6c>, <0xe0 0x14>;
#clock-cells = <2>;
};
pcie_clkctrl: pcie-clkctrl@b0 {
compatible = "ti,clkctrl";
reg = <0xb0 0xc>;
#clock-cells = <2>;
};
gmac_clkctrl: gmac-clkctrl@d0 {
compatible = "ti,clkctrl";
reg = <0xd0 0x4>;
#clock-cells = <2>;
};
};
l4per_cm: l4per_cm@1700 {
l4per_cm: l4per-cm@1700 {
compatible = "ti,omap4-cm";
reg = <0x1700 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1700 0x300>;
l4per_clkctrl: clk@0 {
l4per_clkctrl: l4per-clkctrl@28 {
compatible = "ti,clkctrl";
reg = <0x0 0x20c>;
reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
#clock-cells = <2>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&abe_24m_fclk>;
};
l4sec_clkctrl: l4sec-clkctrl@1a0 {
compatible = "ti,clkctrl";
reg = <0x1a0 0x2c>;
#clock-cells = <2>;
};
l4per2_clkctrl: l4per2-clkctrl@c {
compatible = "ti,clkctrl";
reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
#clock-cells = <2>;
};
l4per3_clkctrl: l4per3-clkctrl@14 {
compatible = "ti,clkctrl";
reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
#clock-cells = <2>;
};
};
};
&prm {
wkupaon_cm: wkupaon_cm@1800 {
wkupaon_cm: wkupaon-cm@1800 {
compatible = "ti,omap4-cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1800 0x100>;
wkupaon_clkctrl: clk@20 {
wkupaon_clkctrl: wkupaon-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;

4
arch/arm/boot/dts/omap4-l4.dtsi
View File

@ -196,12 +196,12 @@
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x58000 0x4000>;
ranges = <0x0 0x58000 0x5000>;
hsi: hsi@0 {
compatible = "ti,omap4-hsi";
reg = <0x0 0x4000>,
<0x4a05c000 0x1000>;
<0x5000 0x1000>;
reg-names = "sys", "gdd";
clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;

2462
arch/arm/boot/dts/omap5-l4.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

688
arch/arm/boot/dts/omap5.dtsi
View File

@ -7,6 +7,7 @@
* Based on "omap4.dtsi"
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
@ -151,178 +152,13 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l4_cfg: l4@4a000000 {
compatible = "ti,omap5-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x22a000>;
scm_core: scm@2000 {
compatible = "ti,omap5-scm-core", "simple-bus";
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x800>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
};
scm_padconf_core: scm@2800 {
compatible = "ti,omap5-scm-padconf-core",
"simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x800>;
omap5_pmx_core: pinmux@40 {
compatible = "ti,omap5-padconf",
"pinctrl-single";
reg = <0x40 0x01b6>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap5_padconf_global: omap5_padconf_global@5a0 {
compatible = "syscon",
"simple-bus";
reg = <0x5a0 0xec>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5a0 0xec>;
pbias_regulator: pbias_regulator@60 {
compatible = "ti,pbias-omap5", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
cm_core_aon: cm_core_aon@4000 {
compatible = "ti,omap5-cm-core-aon",
"simple-bus";
reg = <0x4000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@8000 {
compatible = "ti,omap5-cm-core", "simple-bus";
reg = <0x8000 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
l4_wkup: interconnect@4ae00000 {
};
l4_wkup: l4@4ae00000 {
compatible = "ti,omap5-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4ae00000 0x2b000>;
l4_cfg: interconnect@4a000000 {
};
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x40>;
ti,hwmods = "counter_32k";
};
prm: prm@6000 {
compatible = "ti,omap5-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
scrm: scrm@a000 {
compatible = "ti,omap5-scrm";
reg = <0xa000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
omap5_pmx_wkup: pinmux@c840 {
compatible = "ti,omap5-padconf",
"pinctrl-single";
reg = <0xc840 0x003c>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
compatible = "ti,omap5-scm-wkup-pad-conf",
"simple-bus";
reg = <0xcda0 0x60>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xcda0 0x60>;
scm_wkup_pad_conf: scm_conf@0 {
compatible = "syscon", "simple-bus";
reg = <0x0 0x60>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x60>;
scm_wkup_pad_conf_clocks: clocks@0 {
#address-cells = <1>;
#size-cells = <0>;
};
};
};
l4_per: interconnect@48000000 {
};
ocmcram: ocmcram@40300000 {
@ -330,108 +166,6 @@
reg = <0x40300000 0x20000>; /* 128k */
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <127>;
ti,hwmods = "dma_system";
};
gpio1: gpio@4ae10000 {
compatible = "ti,omap4-gpio";
reg = <0x4ae10000 0x200>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@48055000 {
compatible = "ti,omap4-gpio";
reg = <0x48055000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@48057000 {
compatible = "ti,omap4-gpio";
reg = <0x48057000 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@48059000 {
compatible = "ti,omap4-gpio";
reg = <0x48059000 0x200>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@4805b000 {
compatible = "ti,omap4-gpio";
reg = <0x4805b000 0x200>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@4805d000 {
compatible = "ti,omap4-gpio";
reg = <0x4805d000 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@48051000 {
compatible = "ti,omap4-gpio";
reg = <0x48051000 0x200>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio7";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio8: gpio@48053000 {
compatible = "ti,omap4-gpio";
reg = <0x48053000 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio8";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
@ -451,217 +185,6 @@
#gpio-cells = <2>;
};
i2c1: i2c@48070000 {
compatible = "ti,omap4-i2c";
reg = <0x48070000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
};
i2c2: i2c@48072000 {
compatible = "ti,omap4-i2c";
reg = <0x48072000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
};
i2c3: i2c@48060000 {
compatible = "ti,omap4-i2c";
reg = <0x48060000 0x100>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
};
i2c4: i2c@4807a000 {
compatible = "ti,omap4-i2c";
reg = <0x4807a000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
};
i2c5: i2c@4807c000 {
compatible = "ti,omap4-i2c";
reg = <0x4807c000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c5";
};
hwspinlock: spinlock@4a0f6000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x4a0f6000 0x1000>;
ti,hwmods = "spinlock";
#hwlock-cells = <1>;
};
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
reg = <0x48098000 0x200>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
<&sdma 37>,
<&sdma 38>,
<&sdma 39>,
<&sdma 40>,
<&sdma 41>,
<&sdma 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
mcspi2: spi@4809a000 {
compatible = "ti,omap4-mcspi";
reg = <0x4809a000 0x200>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
<&sdma 45>,
<&sdma 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi3: spi@480b8000 {
compatible = "ti,omap4-mcspi";
reg = <0x480b8000 0x200>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>, <&sdma 16>;
dma-names = "tx0", "rx0";
};
mcspi4: spi@480ba000 {
compatible = "ti,omap4-mcspi";
reg = <0x480ba000 0x200>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
};
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
reg = <0x4806a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@4806c000 {
compatible = "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@48020000 {
compatible = "ti,omap4-uart";
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
uart4: serial@4806e000 {
compatible = "ti,omap4-uart";
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
uart5: serial@48066000 {
compatible = "ti,omap4-uart";
reg = <0x48066000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
};
uart6: serial@48068000 {
compatible = "ti,omap4-uart";
reg = <0x48068000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
};
mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
pbias-supply = <&pbias_mmc_reg>;
};
mmc2: mmc@480b4000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
};
mmc3: mmc@480ad000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
};
mmc4: mmc@480d1000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
dma-names = "tx", "rx";
};
mmc5: mmc@480d5000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480d5000 0x400>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc5";
ti,needs-special-reset;
dmas = <&sdma 59>, <&sdma 60>;
dma-names = "tx", "rx";
};
mmu_dsp: mmu@4a066000 {
compatible = "ti,omap4-iommu";
reg = <0x4a066000 0x100>;
@ -679,12 +202,6 @@
ti,iommu-bus-err-back;
};
keypad: keypad@4ae1c000 {
compatible = "ti,omap4-keypad";
reg = <0x4ae1c000 0x400>;
ti,hwmods = "kbd";
};
mcpdm: mcpdm@40132000 {
compatible = "ti,omap4-mcpdm";
reg = <0x40132000 0x7f>, /* MPU private access */
@ -755,55 +272,6 @@
status = "disabled";
};
mailbox: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
mbox_ipu: mbox_ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
mbox_dsp: mbox_dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
};
timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
clock-names = "fck";
};
timer2: timer@48032000 {
compatible = "ti,omap5430-timer";
reg = <0x48032000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
};
timer3: timer@48034000 {
compatible = "ti,omap5430-timer";
reg = <0x48034000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
};
timer4: timer@48036000 {
compatible = "ti,omap5430-timer";
reg = <0x48036000 0x80>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer4";
};
timer5: timer@40138000 {
compatible = "ti,omap5430-timer";
reg = <0x40138000 0x80>,
@ -843,37 +311,6 @@
ti,timer-pwm;
};
timer9: timer@4803e000 {
compatible = "ti,omap5430-timer";
reg = <0x4803e000 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
ti,timer-pwm;
};
timer10: timer@48086000 {
compatible = "ti,omap5430-timer";
reg = <0x48086000 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
ti,timer-pwm;
};
timer11: timer@48088000 {
compatible = "ti,omap5430-timer";
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
ti,timer-pwm;
};
wdt2: wdt@4ae14000 {
compatible = "ti,omap5-wdt", "ti,omap3-wdt";
reg = <0x4ae14000 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
};
dmm@4e000000 {
compatible = "ti,omap5-dmm";
reg = <0x4e000000 0x800>;
@ -905,99 +342,6 @@
hw-caps-temp-alert;
};
usb3: omap_dwc3@4a020000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss";
reg = <0x4a020000 0x10000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
dwc3: dwc3@4a030000 {
compatible = "snps,dwc3";
reg = <0x4a030000 0x10000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "peripheral";
};
};
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x4a080000 0x20>;
ranges;
ti,hwmods = "ocp2scp1";
usb2_phy: usb2phy@4a084000 {
compatible = "ti,omap-usb2";
reg = <0x4a084000 0x7c>;
syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy_cm_clk32k>,
<&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
};
usb3_phy: usb3phy@4a084400 {
compatible = "ti,omap-usb3";
reg = <0x4a084400 0x80>,
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy_cm_clk32k>,
<&sys_clkin>,
<&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
#phy-cells = <0>;
};
};
usbhstll: usbhstll@4a062000 {
compatible = "ti,usbhs-tll";
reg = <0x4a062000 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "usb_tll_hs";
};
usbhshost: usbhshost@4a064000 {
compatible = "ti,usbhs-host";
reg = <0x4a064000 0x800>;
ti,hwmods = "usb_host_hs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&l3init_60m_fclk>,
<&xclk60mhsp1_ck>,
<&xclk60mhsp2_ck>;
clock-names = "refclk_60m_int",
"refclk_60m_ext_p1",
"refclk_60m_ext_p2";
usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3";
reg = <0x4a064800 0x400>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
remote-wakeup-connected;
};
usbhsehci: ehci@4a064c00 {
compatible = "ti,ehci-omap";
reg = <0x4a064c00 0x400>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
};
bandgap: bandgap@4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
@ -1010,27 +354,6 @@
};
/* OCP2SCP3 */
ocp2scp@4a090000 {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x4a090000 0x20>;
ranges;
ti,hwmods = "ocp2scp3";
sata_phy: phy@4a096000 {
compatible = "ti,phy-pipe3-sata";
reg = <0x4A096000 0x80>, /* phy_rx */
<0x4A096400 0x64>, /* phy_tx */
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin>,
<&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
#phy-cells = <0>;
};
};
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
@ -1184,6 +507,7 @@
coefficients = <65 (-1791)>;
};
#include "omap5-l4.dtsi"
#include "omap54xx-clocks.dtsi"
&gpu_thermal {