net: phy: bcm7xxx: add support for 28nm EPHY
This commit adds support for the internal fast ethernet 10/100 PHY found in the BCM7260, BCM7268, and BCM7271 devices. Signed-off-by: Doug Berger <opendmb@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Doug Berger
David S. Miller
parent
cda792c3f9
commit
83ee102a69
@ -1,7 +1,7 @@
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/*
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* Broadcom BCM7xxx internal transceivers support.
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*
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* Copyright (C) 2014, Broadcom Corporation
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* Copyright (C) 2014-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -19,7 +19,7 @@
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/* Broadcom BCM7xxx internal PHY registers */
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/* 40nm only register definitions */
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/* EPHY only register definitions */
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#define MII_BCM7XXX_100TX_AUX_CTL 0x10
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#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
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#define MII_BCM7XXX_100TX_DISC 0x14
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@ -27,6 +27,19 @@
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#define MII_BCM7XXX_64CLK_MDIO BIT(12)
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#define MII_BCM7XXX_TEST 0x1f
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#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
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#define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
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#define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
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#define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
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#define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
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#define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
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#define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
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#define MII_BCM7XXX_SHD_3_AN_STAT 0xb
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#define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
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#define MII_BCM7XXX_AN_EEE_EN BIT(1)
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#define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
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#define MII_BCM7XXX_EEE_THRESH_DEF 0x50
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#define MII_BCM7XXX_SHD_3_TL4 0x23
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#define MII_BCM7XXX_TL4_RST_MSK (BIT(2) | BIT(1))
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/* 28nm only register definitions */
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#define MISC_ADDR(base, channel) base, channel
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@ -286,6 +299,181 @@ static int phy_set_clr_bits(struct phy_device *dev, int location,
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return v;
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}
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static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
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{
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int ret;
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/* set shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
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MII_BCM7XXX_SHD_MODE_2, 0);
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if (ret < 0)
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return ret;
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/* Set current trim values INT_trim = -1, Ext_trim =0 */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Cal reset */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_TL4);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MII_BCM7XXX_TL4_RST_MSK, 0);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Cal reset disable */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_TL4);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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0, MII_BCM7XXX_TL4_RST_MSK);
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if (ret < 0)
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goto reset_shadow_mode;
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reset_shadow_mode:
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/* reset shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
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MII_BCM7XXX_SHD_MODE_2);
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if (ret < 0)
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return ret;
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return 0;
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}
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/* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
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static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
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{
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int ret;
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/* set shadow mode 1 */
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ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
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MII_BRCM_FET_BT_SRE, 0);
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if (ret < 0)
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return ret;
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/* Enable auto-power down */
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ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
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MII_BRCM_FET_SHDW_AS2_APDE, 0);
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if (ret < 0)
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return ret;
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/* reset shadow mode 1 */
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ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
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MII_BRCM_FET_BT_SRE);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
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{
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int ret;
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/* set shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
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MII_BCM7XXX_SHD_MODE_2, 0);
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if (ret < 0)
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return ret;
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/* Advertise supported modes */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_AN_EEE_ADV);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MDIO_EEE_100TX);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Restore Defaults */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_PCS_CTRL_2);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MII_BCM7XXX_PCS_CTRL_2_DEF);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_EEE_THRESH);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MII_BCM7XXX_EEE_THRESH_DEF);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Enable EEE autonegotiation */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_AN_STAT);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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(MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
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if (ret < 0)
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goto reset_shadow_mode;
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reset_shadow_mode:
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/* reset shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
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MII_BCM7XXX_SHD_MODE_2);
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if (ret < 0)
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return ret;
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/* Restart autoneg */
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phy_write(phydev, MII_BMCR,
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(BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
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return 0;
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}
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static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
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{
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u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
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int ret = 0;
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pr_info_once("%s: %s PHY revision: 0x%02x\n",
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phydev_name(phydev), phydev->drv->name, rev);
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/* Dummy read to a register to workaround a possible issue upon reset
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* where the internal inverter may not allow the first MDIO transaction
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* to pass the MDIO management controller and make us return 0xffff for
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* such reads.
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*/
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phy_read(phydev, MII_BMSR);
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/* Apply AFE software work-around if necessary */
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if (rev == 0x01) {
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ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev);
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if (ret)
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return ret;
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}
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ret = bcm7xxx_28nm_ephy_eee_enable(phydev);
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if (ret)
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return ret;
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return bcm7xxx_28nm_ephy_apd_enable(phydev);
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}
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static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
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{
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int ret;
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/* Re-apply workarounds coming out suspend/resume */
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ret = bcm7xxx_28nm_ephy_config_init(phydev);
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if (ret)
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return ret;
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return genphy_config_aneg(phydev);
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}
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static int bcm7xxx_config_init(struct phy_device *phydev)
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{
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int ret;
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@ -434,6 +622,23 @@ static int bcm7xxx_28nm_probe(struct phy_device *phydev)
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.probe = bcm7xxx_28nm_probe, \
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}
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#define BCM7XXX_28NM_EPHY(_oui, _name) \
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{ \
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.phy_id = (_oui), \
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.phy_id_mask = 0xfffffff0, \
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.name = _name, \
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.features = PHY_BASIC_FEATURES, \
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.flags = PHY_IS_INTERNAL, \
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.config_init = bcm7xxx_28nm_ephy_config_init, \
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.config_aneg = genphy_config_aneg, \
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.read_status = genphy_read_status, \
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.resume = bcm7xxx_28nm_ephy_resume, \
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.get_sset_count = bcm_phy_get_sset_count, \
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.get_strings = bcm_phy_get_strings, \
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.get_stats = bcm7xxx_28nm_get_phy_stats, \
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.probe = bcm7xxx_28nm_probe, \
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}
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#define BCM7XXX_40NM_EPHY(_oui, _name) \
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{ \
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.phy_id = (_oui), \
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@ -450,6 +655,9 @@ static int bcm7xxx_28nm_probe(struct phy_device *phydev)
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static struct phy_driver bcm7xxx_driver[] = {
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
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BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
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BCM7XXX_28NM_EPHY(PHY_ID_BCM7268, "Broadcom BCM7268"),
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BCM7XXX_28NM_EPHY(PHY_ID_BCM7271, "Broadcom BCM7271"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
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@ -466,6 +674,9 @@ static struct phy_driver bcm7xxx_driver[] = {
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static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
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{ PHY_ID_BCM7250, 0xfffffff0, },
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{ PHY_ID_BCM7260, 0xfffffff0, },
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{ PHY_ID_BCM7268, 0xfffffff0, },
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{ PHY_ID_BCM7271, 0xfffffff0, },
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{ PHY_ID_BCM7278, 0xfffffff0, },
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{ PHY_ID_BCM7364, 0xfffffff0, },
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{ PHY_ID_BCM7366, 0xfffffff0, },
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@ -25,6 +25,9 @@
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#define PHY_ID_BCM57780 0x03625d90
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#define PHY_ID_BCM7250 0xae025280
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#define PHY_ID_BCM7260 0xae025190
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#define PHY_ID_BCM7268 0xae025090
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#define PHY_ID_BCM7271 0xae0253b0
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#define PHY_ID_BCM7278 0xae0251a0
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#define PHY_ID_BCM7364 0xae025260
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#define PHY_ID_BCM7366 0x600d8490
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