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Merge branch 'parisc-4.20-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux 

Pull parisc fix from Helge Deller:
 "Revert one patch which changed how spinlocks get released. It breaks
  the rwlock implementation in glibc"

* 'parisc-4.20-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: Revert "Release spinlocks using ordered store"
This commit is contained in:
Linus Torvalds 2018-11-14 13:42:41 -06:00
parent e2f8b472a7 86d4d068df
commit 857c34cd09
2 changed files with 10 additions and 6 deletions
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4
arch/parisc/include/asm/spinlock.h
View File

@ -37,8 +37,8 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
volatile unsigned int *a; volatile unsigned int *a;
a = __ldcw_align(x); a = __ldcw_align(x);
/* Release with ordered store. */ mb();
__asm__ __volatile__("stw,ma %0,0(%1)" : : "r"(1), "r"(a) : "memory"); *a = 1;
} }
static inline int arch_spin_trylock(arch_spinlock_t *x) static inline int arch_spin_trylock(arch_spinlock_t *x)

12
arch/parisc/kernel/syscall.S
View File

@ -640,7 +640,8 @@ cas_action:
sub,<> %r28, %r25, %r0 sub,<> %r28, %r25, %r0
2: stw %r24, 0(%r26) 2: stw %r24, 0(%r26)
/* Free lock */ /* Free lock */
stw,ma %r20, 0(%sr2,%r20) sync
stw %r20, 0(%sr2,%r20)
#if ENABLE_LWS_DEBUG #if ENABLE_LWS_DEBUG
/* Clear thread register indicator */ /* Clear thread register indicator */
stw %r0, 4(%sr2,%r20) stw %r0, 4(%sr2,%r20)
@ -654,7 +655,8 @@ cas_action:
3: 3:
/* Error occurred on load or store */ /* Error occurred on load or store */
/* Free lock */ /* Free lock */
stw,ma %r20, 0(%sr2,%r20) sync
stw %r20, 0(%sr2,%r20)
#if ENABLE_LWS_DEBUG #if ENABLE_LWS_DEBUG
stw %r0, 4(%sr2,%r20) stw %r0, 4(%sr2,%r20)
#endif #endif
@ -855,7 +857,8 @@ cas2_action:
cas2_end: cas2_end:
/* Free lock */ /* Free lock */
stw,ma %r20, 0(%sr2,%r20) sync
stw %r20, 0(%sr2,%r20)
/* Enable interrupts */ /* Enable interrupts */
ssm PSW_SM_I, %r0 ssm PSW_SM_I, %r0
/* Return to userspace, set no error */ /* Return to userspace, set no error */
@ -865,7 +868,8 @@ cas2_end:
22: 22:
/* Error occurred on load or store */ /* Error occurred on load or store */
/* Free lock */ /* Free lock */
stw,ma %r20, 0(%sr2,%r20) sync
stw %r20, 0(%sr2,%r20)
ssm PSW_SM_I, %r0 ssm PSW_SM_I, %r0
ldo 1(%r0),%r28 ldo 1(%r0),%r28
b lws_exit b lws_exit