Merge branches 'gart/fixes', 'amd-iommu/fixes+cleanups' and 'amd-iommu/fault-handling' into amd-iommu/2.6.32
This commit is contained in:
commit
85da07c409
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@ -198,7 +198,7 @@ extern bool amd_iommu_dump;
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#define DUMP_printk(format, arg...) \
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do { \
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if (amd_iommu_dump) \
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printk(KERN_INFO "AMD IOMMU: " format, ## arg); \
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printk(KERN_INFO "AMD-Vi: " format, ## arg); \
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} while(0);
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/*
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@ -337,6 +337,9 @@ struct amd_iommu {
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/* if one, we need to send a completion wait command */
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bool need_sync;
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/* becomes true if a command buffer reset is running */
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bool reset_in_progress;
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/* default dma_ops domain for that IOMMU */
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struct dma_ops_domain *default_dom;
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};
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@ -457,4 +460,7 @@ static inline void amd_iommu_stats_init(void) { }
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#endif /* CONFIG_AMD_IOMMU_STATS */
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/* some function prototypes */
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extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
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#endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
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@ -41,9 +41,7 @@ static DEFINE_RWLOCK(amd_iommu_devtable_lock);
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static LIST_HEAD(iommu_pd_list);
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static DEFINE_SPINLOCK(iommu_pd_list_lock);
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#ifdef CONFIG_IOMMU_API
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static struct iommu_ops amd_iommu_ops;
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#endif
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/*
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* general struct to manage commands send to an IOMMU
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@ -61,10 +59,7 @@ static u64* alloc_pte(struct protection_domain *dom,
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static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
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unsigned long start_page,
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unsigned int pages);
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#ifndef BUS_NOTIFY_UNBOUND_DRIVER
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#define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
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#endif
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static void reset_iommu_command_buffer(struct amd_iommu *iommu);
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#ifdef CONFIG_AMD_IOMMU_STATS
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@ -138,7 +133,25 @@ static int iommu_has_npcache(struct amd_iommu *iommu)
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*
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****************************************************************************/
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static void iommu_print_event(void *__evt)
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static void dump_dte_entry(u16 devid)
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{
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int i;
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for (i = 0; i < 8; ++i)
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pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
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amd_iommu_dev_table[devid].data[i]);
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}
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static void dump_command(unsigned long phys_addr)
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{
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struct iommu_cmd *cmd = phys_to_virt(phys_addr);
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int i;
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for (i = 0; i < 4; ++i)
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pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
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}
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static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
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{
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u32 *event = __evt;
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int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
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@ -147,7 +160,7 @@ static void iommu_print_event(void *__evt)
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int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
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u64 address = (u64)(((u64)event[3]) << 32) | event[2];
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printk(KERN_ERR "AMD IOMMU: Event logged [");
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printk(KERN_ERR "AMD-Vi: Event logged [");
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switch (type) {
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case EVENT_TYPE_ILL_DEV:
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@ -155,6 +168,7 @@ static void iommu_print_event(void *__evt)
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"address=0x%016llx flags=0x%04x]\n",
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PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
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address, flags);
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dump_dte_entry(devid);
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break;
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case EVENT_TYPE_IO_FAULT:
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printk("IO_PAGE_FAULT device=%02x:%02x.%x "
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@ -176,6 +190,8 @@ static void iommu_print_event(void *__evt)
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break;
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case EVENT_TYPE_ILL_CMD:
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printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
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reset_iommu_command_buffer(iommu);
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dump_command(address);
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break;
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case EVENT_TYPE_CMD_HARD_ERR:
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printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
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@ -209,7 +225,7 @@ static void iommu_poll_events(struct amd_iommu *iommu)
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tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
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while (head != tail) {
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iommu_print_event(iommu->evt_buf + head);
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iommu_print_event(iommu, iommu->evt_buf + head);
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head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
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}
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@ -296,8 +312,11 @@ static void __iommu_wait_for_completion(struct amd_iommu *iommu)
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status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
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writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
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if (unlikely(i == EXIT_LOOP_COUNT))
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panic("AMD IOMMU: Completion wait loop failed\n");
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if (unlikely(i == EXIT_LOOP_COUNT)) {
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spin_unlock(&iommu->lock);
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reset_iommu_command_buffer(iommu);
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spin_lock(&iommu->lock);
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}
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}
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/*
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@ -445,37 +464,67 @@ static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
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}
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/*
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* This function is used to flush the IO/TLB for a given protection domain
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* on every IOMMU in the system
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* This function flushes one domain on one IOMMU
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*/
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static void iommu_flush_domain(u16 domid)
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static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid)
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{
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unsigned long flags;
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struct amd_iommu *iommu;
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struct iommu_cmd cmd;
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INC_STATS_COUNTER(domain_flush_all);
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unsigned long flags;
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__iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
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domid, 1, 1);
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for_each_iommu(iommu) {
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spin_lock_irqsave(&iommu->lock, flags);
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__iommu_queue_command(iommu, &cmd);
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__iommu_completion_wait(iommu);
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__iommu_wait_for_completion(iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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spin_lock_irqsave(&iommu->lock, flags);
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__iommu_queue_command(iommu, &cmd);
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__iommu_completion_wait(iommu);
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__iommu_wait_for_completion(iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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void amd_iommu_flush_all_domains(void)
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static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
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{
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int i;
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for (i = 1; i < MAX_DOMAIN_ID; ++i) {
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if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
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continue;
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iommu_flush_domain(i);
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flush_domain_on_iommu(iommu, i);
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}
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}
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/*
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* This function is used to flush the IO/TLB for a given protection domain
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* on every IOMMU in the system
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*/
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static void iommu_flush_domain(u16 domid)
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{
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struct amd_iommu *iommu;
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INC_STATS_COUNTER(domain_flush_all);
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for_each_iommu(iommu)
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flush_domain_on_iommu(iommu, domid);
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}
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void amd_iommu_flush_all_domains(void)
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{
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struct amd_iommu *iommu;
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for_each_iommu(iommu)
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flush_all_domains_on_iommu(iommu);
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}
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static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
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{
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int i;
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for (i = 0; i <= amd_iommu_last_bdf; ++i) {
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if (iommu != amd_iommu_rlookup_table[i])
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continue;
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iommu_queue_inv_dev_entry(iommu, i);
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iommu_completion_wait(iommu);
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}
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}
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@ -485,8 +534,6 @@ void amd_iommu_flush_all_devices(void)
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int i;
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for (i = 0; i <= amd_iommu_last_bdf; ++i) {
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if (amd_iommu_pd_table[i] == NULL)
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continue;
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iommu = amd_iommu_rlookup_table[i];
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if (!iommu)
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@ -497,6 +544,22 @@ void amd_iommu_flush_all_devices(void)
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}
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}
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static void reset_iommu_command_buffer(struct amd_iommu *iommu)
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{
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pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
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if (iommu->reset_in_progress)
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panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
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iommu->reset_in_progress = true;
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amd_iommu_reset_cmd_buffer(iommu);
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flush_all_devices_for_iommu(iommu);
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flush_all_domains_on_iommu(iommu);
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iommu->reset_in_progress = false;
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}
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/****************************************************************************
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*
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* The functions below are used the create the page table mappings for
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@ -252,7 +252,7 @@ static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
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/* Function to enable the hardware */
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static void iommu_enable(struct amd_iommu *iommu)
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{
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printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
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printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
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dev_name(&iommu->dev->dev), iommu->cap_ptr);
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iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
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@ -434,6 +434,20 @@ static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
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return cmd_buf;
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}
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/*
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* This function resets the command buffer if the IOMMU stopped fetching
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* commands from it.
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*/
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void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
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{
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iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
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writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
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writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
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iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
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}
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/*
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* This function writes the command buffer address to the hardware and
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* enables it.
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@ -450,11 +464,7 @@ static void iommu_enable_command_buffer(struct amd_iommu *iommu)
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memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
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&entry, sizeof(entry));
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/* set head and tail to zero manually */
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writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
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writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
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iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
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amd_iommu_reset_cmd_buffer(iommu);
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}
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static void __init free_command_buffer(struct amd_iommu *iommu)
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@ -858,7 +868,7 @@ static int __init init_iommu_all(struct acpi_table_header *table)
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switch (*p) {
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case ACPI_IVHD_TYPE:
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DUMP_printk("IOMMU: device: %02x:%02x.%01x cap: %04x "
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DUMP_printk("device: %02x:%02x.%01x cap: %04x "
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"seg: %d flags: %01x info %04x\n",
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PCI_BUS(h->devid), PCI_SLOT(h->devid),
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PCI_FUNC(h->devid), h->cap_ptr,
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@ -902,7 +912,7 @@ static int __init iommu_setup_msi(struct amd_iommu *iommu)
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r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
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IRQF_SAMPLE_RANDOM,
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"AMD IOMMU",
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"AMD-Vi",
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NULL);
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if (r) {
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@ -1150,7 +1160,7 @@ int __init amd_iommu_init(void)
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if (no_iommu) {
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printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
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printk(KERN_INFO "AMD-Vi disabled by kernel command line\n");
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return 0;
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}
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@ -1248,16 +1258,16 @@ int __init amd_iommu_init(void)
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enable_iommus();
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printk(KERN_INFO "AMD IOMMU: device isolation ");
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printk(KERN_INFO "AMD-Vi: device isolation ");
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if (amd_iommu_isolate)
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printk("enabled\n");
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else
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printk("disabled\n");
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if (amd_iommu_unmap_flush)
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printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
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printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
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else
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printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
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printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
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out:
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return ret;
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