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ASoC: wm8510 pll settings 

When setting WM8510_MCLKDIV the pll was turned off.

When setting pll frequency you got twice the expected freq, because
the  code calculated  with postscaler of 8,  but  the hardware divide by 4.

Signed-off-by: Jonas Andersson <jonas@microbit.se>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Jonas Andersson 2009-03-04 08:24:26 +01:00 committed by Mark Brown
parent ec67624d33
commit 86027ae78c
2 changed files with 22 additions and 22 deletions
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40
sound/soc/atmel/playpaq_wm8510.c
View File

@ -164,41 +164,41 @@ static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
*/
switch (params_rate(params)) {
case 48000:
pll_out = 12288000;
mclk_div = WM8510_MCLKDIV_1;
bclk = WM8510_BCLKDIV_8;
break;
case 44100:
pll_out = 11289600;
mclk_div = WM8510_MCLKDIV_1;
bclk = WM8510_BCLKDIV_8;
break;
case 22050:
pll_out = 11289600;
pll_out = 24576000;
mclk_div = WM8510_MCLKDIV_2;
bclk = WM8510_BCLKDIV_8;
break;
case 16000:
pll_out = 12288000;
mclk_div = WM8510_MCLKDIV_3;
case 44100:
pll_out = 22579200;
mclk_div = WM8510_MCLKDIV_2;
bclk = WM8510_BCLKDIV_8;
break;
case 11025:
pll_out = 11289600;
case 22050:
pll_out = 22579200;
mclk_div = WM8510_MCLKDIV_4;
bclk = WM8510_BCLKDIV_8;
break;
case 8000:
pll_out = 12288000;
case 16000:
pll_out = 24576000;
mclk_div = WM8510_MCLKDIV_6;
bclk = WM8510_BCLKDIV_8;
break;
case 11025:
pll_out = 22579200;
mclk_div = WM8510_MCLKDIV_8;
bclk = WM8510_BCLKDIV_8;
break;
case 8000:
pll_out = 24576000;
mclk_div = WM8510_MCLKDIV_12;
bclk = WM8510_BCLKDIV_8;
break;
default:
pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
params_rate(params));

4
sound/soc/codecs/wm8510.c
View File

@ -336,7 +336,7 @@ static int wm8510_set_dai_pll(struct snd_soc_dai *codec_dai,
return 0;
}
pll_factors(freq_out*8, freq_in);
pll_factors(freq_out*4, freq_in);
wm8510_write(codec, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n);
wm8510_write(codec, WM8510_PLLK1, pll_div.k >> 18);
@ -367,7 +367,7 @@ static int wm8510_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
wm8510_write(codec, WM8510_GPIO, reg | div);
break;
case WM8510_MCLKDIV:
reg = wm8510_read_reg_cache(codec, WM8510_CLOCK) & 0x1f;
reg = wm8510_read_reg_cache(codec, WM8510_CLOCK) & 0x11f;
wm8510_write(codec, WM8510_CLOCK, reg | div);
break;
case WM8510_ADCCLK: